WO2018040519A1 - 一种半导体装置及制造方法 - Google Patents

一种半导体装置及制造方法 Download PDF

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Publication number
WO2018040519A1
WO2018040519A1 PCT/CN2017/074449 CN2017074449W WO2018040519A1 WO 2018040519 A1 WO2018040519 A1 WO 2018040519A1 CN 2017074449 W CN2017074449 W CN 2017074449W WO 2018040519 A1 WO2018040519 A1 WO 2018040519A1
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Prior art keywords
layer
sintered
circuit device
alloy
nano metal
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PCT/CN2017/074449
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English (en)
French (fr)
Inventor
林志荣
黄文浚
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华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP17844829.6A priority Critical patent/EP3503176B1/en
Publication of WO2018040519A1 publication Critical patent/WO2018040519A1/zh
Priority to US16/287,629 priority patent/US20190198422A1/en

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    • B82—NANOTECHNOLOGY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method of fabricating the same.
  • the structure includes an integrated circuit chip 1A02, a thermal interface material layer 1A04, and a heat sink 1A06.
  • the thermal interface material layer 1A04 has a plurality of metal particles 1A08 distributed in the form of a dispersed phase, and the heat generated during the operation of the integrated circuit chip 1A02 is poured into the heat sink 1A06 through the thermal interface material layer 1A04 on the back side of the chip, but the existing In the technology, since the limitation of the size of the circuit chip 1A02 leads to a low heat transfer effect, it has been difficult to meet the heat dissipation requirement of the high power chip.
  • Embodiments of the present invention provide a semiconductor device and a method of fabricating the same.
  • the contact area of the thermal interface material layer and the circuit device is increased by the provided encapsulation layer, the thermal conductivity of the overall thermal path is greatly improved, and the heat dissipation requirement of the high power circuit device can be better satisfied.
  • an embodiment of the present invention provides a semiconductor device including: a stacked circuit device and a heat sink; and a thermal interface material layer between the circuit device and the heat sink;
  • An outer surface of the circuit device is provided with an encapsulation layer;
  • the circuit device includes an integrated circuit die, the integrated circuit die has a pin, and one side of the integrated circuit die on which the pin is disposed is a mounting surface
  • the sidewall of the circuit device is a wall on the integrated circuit die adjacent to the mounting surface;
  • the thermal interface material layer has a first side facing the circuit device and the encapsulation layer and a second side facing the heat sink, and the first surface is thermally coupled to the circuit device and the encapsulation layer The second surface is thermally coupled to the heat sink.
  • the encapsulation layer is disposed around the circuit device, and the encapsulation layer and the circuit device are both thermally coupled with the thermal interface material layer, thereby increasing the contact area of the circuit device and the thermal interface material layer, and simultaneously, the circuit device sidewall
  • the heat generated on the surface can be transferred to the thermal interface material layer through the encapsulation layer and then transferred to the heat sink to improve the heat dissipation effect of the semiconductor device.
  • the laying area of the thermal interface material layer is increased, the area of the contact surface of the thermal interface material layer is increased, the interface stress is reduced, and the component reliability is correspondingly improved. Sex.
  • the encapsulation layer adopts a plastic sealing film layer, and the plastic sealing film layer has a good heat transfer effect, and can quickly transfer heat on the sidewall of the circuit device to the thermal interface material layer, thereby improving the heat dissipation efficiency of the circuit device.
  • the thermal interface material layer includes: a first alloy layer thermally coupled to the circuit device and the encapsulation layer; a nano metal particle layer thermally coupled to the first alloy layer, the nano metal particle layer including coupling a plurality of nano metal particles and an intermediate mixture, the intermediate mixture being filled between the plurality of nano metal particles; and a second alloy layer thermally coupled to the nano metal particle layer and the heat sink.
  • the thermal interface material in the embodiment of the present invention is used because the thermal interface material layer does not contain the polymer-based lower thermal conductive material in the silver-based material, but includes the nano-metal particles. It has a higher thermal conductivity and greatly improves the thermal conductivity of the overall thermal path, and can better meet the heat dissipation requirements of large power chips.
  • a contact of the first alloy layer and the nano metal particle layer forms a sintered continuous phase structure
  • a contact between the plurality of nano metal particles forms a sintered continuous phase structure
  • the second A sintered continuous phase structure is formed at the contact of the alloy layer with the nano metal particle layer.
  • the formed continuous sintering phase structure improves the connection effect between the two and improves the heat transfer between the two.
  • the nano metal particles comprise silver. Has a good heat transfer effect. And in a specific arrangement, the nano metal particles have a diameter between 50 and 200 nanometers.
  • the semiconductor device provided in this embodiment is used for a flip chip ball grid array package structure.
  • the first alloy layer includes a first adhesive layer and a first co-sintered layer, the first adhesive layer being thermally coupled to the circuit device and the encapsulation layer, the first co-sintered layer and the nano-metal particles
  • the layers are coupled, and a contact of the first co-sintered layer with the nano metal particle layer forms a sintered continuous phase structure.
  • the first backing layer comprises any of the following materials: titanium, chromium, nickel or nickel vanadium alloy, the first co-sintered layer comprising any of the following materials: silver, gold or copper. All of the above materials have good heat transfer effects.
  • the first alloy layer further includes a first buffer layer between the first adhesive layer and the first co-sintered layer, the first buffer layer comprising the following materials Any one: aluminum, copper, nickel or nickel vanadium alloy.
  • the second alloy layer includes a second adhesive layer and a second co-sintered layer
  • the second adhesive layer is thermally coupled to the heat sink
  • the second co-sintered layer and the nano metal particles The layer is thermally coupled, and the contact between the second co-sintered layer and the nano-metal particle layer forms a sintered continuous phase structure.
  • the second adhesive layer comprises any one of the following materials: titanium, chromium, nickel or nickel vanadium alloy
  • the second co-sintered layer comprises any one of the following materials: silver, gold Or copper. All of the above materials have good heat transfer effects.
  • the second alloy layer further includes a second buffer layer between the second adhesive layer and the second co-sintered layer, the second buffer layer comprising any of the following materials Species: aluminum, copper, nickel or nickel vanadium alloy.
  • the nano metal particles therein have a diameter of no more than 1 micrometer.
  • the intermediate mixture can be selected from different materials, and in a particular embodiment the intermediate mixture comprises any of the following materials: air or resin.
  • Embodiments of the present invention provide a method of fabricating a semiconductor device, comprising: encapsulating an encapsulation layer on a sidewall of a circuit device; wherein the circuit device includes an integrated circuit die, the integrated circuit die having a pin, One side of the integrated circuit die on which the pin is disposed is a mounting surface, and a sidewall of the circuit device is a wall adjacent to the mounting surface of the integrated circuit die;
  • a first side is thermally coupled to the circuit device and the encapsulation layer, the second side being thermally coupled to the heat sink.
  • the encapsulation layer is disposed around the circuit device, and the encapsulation layer and the circuit device are both thermally coupled with the thermal interface material layer, thereby increasing the contact area of the circuit device and the thermal interface material layer, and simultaneously, the circuit device sidewall
  • the heat generated can be transferred to the layer of thermal interface material through the encapsulation layer and then transferred to the heat sink to improve the semi-conductivity
  • the heat dissipation effect of the body device by laying a layer of encapsulation layer on the outer side of the circuit device, the laying area of the thermal interface material layer is increased, the area of the contact surface of the thermal interface material layer is increased, the interface stress is reduced, and the component reliability is correspondingly improved. Sex.
  • the thermal interface material layer has a first surface facing the circuit device and the encapsulation layer and a second surface facing the heat sink; specifically:
  • the nano metal particle layer is thermally coupled to the first alloy layer and the second alloy layer, respectively, wherein a side of the first alloy layer facing away from the nanoparticle layer is a first surface, and the second alloy layer faces away from One side of the nano metal particle layer is a second side.
  • the method further includes: forming a sintered continuous phase structure at a contact between the first alloy layer and the nano metal particle layer, forming a sintered continuous phase structure at a contact between the nano metal particles, and making the second alloy A contact of the layer with the nano metal particle layer forms a sintered continuous phase structure.
  • the nano metal particles therein have a diameter of no more than 1 micrometer.
  • the intermediate mixture therein includes any of the following materials: air or resin.
  • first alloy layer When the first alloy layer is specifically prepared, a first adhesive layer and a first co-sintered layer are formed, and the first adhesive layer is thermally coupled to the circuit device and the encapsulation layer to cause the first co-sintered layer Coupling with the nano metal particle layer and forming a sintered continuous phase structure at the contact of the first co-sintered layer and the nano metal particle layer.
  • the second alloy layer When specifically preparing the second alloy layer: forming a second adhesive layer and a second co-sintered layer, and thermally coupling the second adhesive layer to the heat sink to cause the second co-sintered layer and the nano metal
  • the particle layer is thermally coupled and forms a sintered continuous phase structure at the contact of the second co-sintered layer with the nano metal particle layer.
  • the encapsulating the encapsulation layer on the sidewall of the circuit device comprises using a plastic film as a material for manufacturing the encapsulation layer to surround the encapsulation layer on the sidewall.
  • the plastic film has a good heat transfer effect, and the preparation of the encapsulation layer by the provided plastic film improves the heat dissipation efficiency of the circuit device.
  • 1A is a cross-sectional view showing a package structure including a semiconductor device in the prior art
  • FIG. 1B is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 is a schematic diagram of a circuit device and an encapsulation layer of a semiconductor device according to a first embodiment of the present invention
  • FIG. 3 is a cross-sectional view showing an example of a thermal interface material layer thermally coupled to a circuit device and an encapsulation layer in the first embodiment
  • Figure 4 is a cross-sectional view showing a first embodiment of the first alloy layer of Figure 3;
  • Figure 5 is a cross-sectional view showing a second embodiment of the first alloy layer of Figure 3;
  • Figure 6 is a cross-sectional view showing a first embodiment of the second alloy layer of Figure 3;
  • Figure 7 is a cross-sectional view showing a second embodiment of the second alloy layer of Figure 3;
  • Figure 8 is a flow chart showing a method of fabricating a semiconductor device in accordance with a second embodiment of the present invention.
  • the present embodiment defines a side wall of the circuit device.
  • the side wall of the circuit device refers to a wall on the circuit device adjacent to a side (mounting surface) on which the pin is disposed, in FIG. 1B.
  • 1B is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, with the direction in which the semiconductor device is placed as a reference direction, and the sidewall of the circuit device is a side in the vertical direction shown in FIG. 1B.
  • An embodiment of the present invention provides a semiconductor device including: a stacked circuit device and a heat sink 105, and a thermal interface material layer 104 between the circuit device and the heat sink 105;
  • An encapsulation layer 120 is disposed around the sidewall of the circuit device; wherein the circuit device includes an integrated circuit die 103, the integrated circuit die 103 has a pin, and the transistor is disposed on the integrated circuit die 103 One side of the foot is a mounting surface, and the side wall of the circuit device is a wall of the integrated circuit die 103 adjacent to the mounting surface;
  • the thermal interface material layer 104 has a first side facing the circuit device and the encapsulation layer 120 and a second side facing the heat sink 105, and the first surface and the circuit device and the package Layer 120 is thermally coupled and the second side is thermally coupled to the heat sink 105.
  • FIG. 1B is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.
  • 2 is a top plan view showing the combination of the circuit device and the package layer in the embodiment.
  • 2 is a schematic diagram showing the structure of the circuit device (integrated circuit die 103) and the encapsulation layer 120 as seen from the top to the bottom with the placement direction of the device shown in FIG. 1B as a reference direction.
  • the circuit device adopts a regular rectangular shape.
  • FIG. 2 is merely for explaining the positional relationship between the circuit device and the package layer 120, and the shape of the circuit device is not limited to the above-described rectangle in FIG. The shape may be any other shape.
  • the encapsulation layer 120 provided in this embodiment is disposed around the sidewall of the circuit device, that is, the encapsulation layer 120 can be formed as a turn around the circuit device.
  • thermal interface material layer 104 is thermally coupled to integrated circuit die 103 and heat sink 105. In a specific arrangement, the thermal interface material layer 104 covers the top surface of the integrated circuit die 103 and the encapsulation layer 120 (ie, the side shown in FIG.
  • the encapsulation layer 120 forms a frame-shaped contact surface that is thermally coupled to the thermal interface material layer 104 (as shown in FIG. 2), and in a particular arrangement, the encapsulation layer 120 has a set thickness d
  • the frame edge of the frame contact surface has a certain width (the width is equal to the thickness of the package layer 120).
  • the coupling area is only the integrated circuit die. The top surface area of the 103, after the upper encapsulation layer 120 is increased, as shown in FIG.
  • the coupling area is the area of the top surface of the integrated circuit die 103 plus the area of the top surface of the encapsulation layer 120, which increases the thermal interface material layer.
  • 104 is the area of the thermal coupling surface with the integrated circuit die 103.
  • the connection strength of the thermal interface material layer 104 to the integrated circuit die 103 is increased due to the increase in the coupling area, and The interface stress is reduced (the overall stress is constant, but the contact area is increased, and the influence of stress under the unit area is reduced), and the reliability performance of the component is improved.
  • the encapsulation layer 120 is attached to the sidewall of the circuit device, heat on the sidewalls of the circuit device can be transferred to the thermal interface material layer 104 through the encapsulation layer 120 during heat dissipation, thereby further Diffusion onto the heat sink 105.
  • the heat dissipation of the circuit device is such that the heat of the top surface of the circuit device is dissipated through the path of the thermal interface material layer 104 - the heat sink 105, the side of the circuit device The heat on the wall is dissipated through the path of the encapsulation layer 120 - the thermal interface material layer 104 - the heat sink 105, thereby increasing the heat dissipation area of the circuit device, thereby improving the heat dissipation effect of the circuit device.
  • the encapsulation layer 120 adopts a plastic film layer, and the plastic film layer has a good encapsulation effect and a heat transfer effect, so that heat can be quickly transferred to the thermal interface material layer, thereby improving the heat dissipation effect of the circuit device. .
  • the entire semiconductor device includes a solder ball 108, a substrate 107, an adhesive 106, a metal bump (BUMP) 102, and a circuit device when using a flip chip ball grid array package structure.
  • the integrated circuit die 103) surrounds the encapsulation layer 120 (such as the plastic film layer) of the circuit device 103, the thermal interface material layer 104, and the heat sink 105.
  • Integrated circuit die 103 is coupled to substrate 107 by metal bumps 102.
  • the metal bumps 102 are protected by the underfill 101, and the encapsulation layer 120 is disposed around the integrated circuit die 103, and in a specific arrangement, in this embodiment, the thermal coupling includes different levels, different structures, or heat conduction between different devices. .
  • the thermal interface material layer 104 can be between the integrated circuit die 103 and the heat sink 105, and the substrate of the integrated circuit die 103 is thermally coupled to the thermal interface material layer 104, and the encapsulation layer is also associated with the thermal interface material layer 104. Thermally coupled. Heat from the integrated circuit die 103 reaches the heat sink 105 through the thermal interface material layer 104.
  • the integrated circuit die 103, the encapsulation layer 120 surrounding the circuit device 103, the thermal interface material layer 104, and the heat sink 105 may be used as part or all of a semiconductor device, and the semiconductor device may be used for, but not limited to, as shown in the figure.
  • FIG. 3 is a cross-sectional view showing the thermal interface material layer in the first embodiment thermally coupled to the circuit device and the encapsulation layer; wherein, in FIG. 3, only the thermal interface material layer 104 of FIG. 1B is connected to the integrated circuit die 103.
  • the upper half structure, the encapsulation layer 120 also only shows the upper half structure of the encapsulation layer 120, which does not include the underfill 101.
  • the thermal interface material layer 104 is thermally coupled to the integrated circuit die 103, the encapsulation layer 120, and the heat sink 105, and includes a first alloy layer 109, a nano metal particle layer 110, and a second alloy layer 112.
  • the first alloy layer 109 thermally couples the integrated circuit die 103 and the encapsulation layer 120 to the nano metal particle layer 110. More specifically, as shown in FIG. 3, the first alloy layer 109 can be over the integrated circuit die 103 and the encapsulation layer 120, under the nano metal particle layer 110. That is, the first alloy layer 109 can be between the integrated circuit die 103 and the nano metal particle layer 110.
  • the first alloy layer 109 increases the adhesion strength between the integrated circuit die 103 and the nano metal particle layer 110, and increases the coverage area of the first alloy layer 109 by the disposed encapsulation layer 120, that is, increases the first formation.
  • the area of the alloy layer 109 increases the area 104 of the formed thermal interface material layer.
  • the nano metal particle layer 110 includes nano metal particles and an intermediate mixture.
  • the intermediate mixture includes, but is not limited to, any of the following materials: air or resin.
  • the intermediate mixture is used to fill between the plurality of nano metal particles to form a plurality of nano metal particles.
  • Nano metal particles include, but are not limited to, silver.
  • the nano metal particles have a diameter of no more than 1 micron. In one embodiment, the nano metal particles have a diameter between 50 and 200 nanometers.
  • the nano metal particle layer 110 has a lower thermal resistance and forms a better heat conduction path.
  • the second alloy layer 112 is thermally coupled to the nano metal particle layer 110 and the heat sink 105. More specifically, as shown, the second alloy layer 112 can be positioned over the nano metal particle layer 110 below the heat sink 105. That is, the second alloy layer 112 can be located The nano metal particle layer 110 is between the heat sink 105 and the heat sink 105. The second alloy layer 112 increases the adhesion strength between the nano metal particle layer 110 and the heat sink 105.
  • the first alloy layer 109 forms a sintered continuous phase structure at the contact with the nano metal particle layer 110, the contact between the nano metal particles forms a sintered continuous phase structure, and the second alloy layer 112 and the nano metal particles
  • the contact of layer 110 forms a sintered continuous phase structure.
  • the sintered continuous phase structure herein includes, but is not limited to, due to the sintering behavior of the metal particles, the metal atoms in the vicinity of the metal particle interface diffuse to the metal particle interface to fuse together, so that the metal particles form a unitary structure.
  • the first alloy layer 109 includes a first via layer 114 and a first co-sintered layer 115.
  • the co-sintered layer herein includes, but is not limited to, a metal layer that is interfused with the layer of thermal interface material produced during the encapsulation process, the metal layer co-sintering with the particles in the layer of thermal interface material to form a heat flow path.
  • the first via layer 114 is thermally coupled to the integrated circuit die 103 and the encapsulation layer 120.
  • the first co-sintered layer 115 is thermally coupled to the nano-metal particle layer 110.
  • the contact of the first co-sintered layer 115 with the nano-metal particle layer 110 forms a sintered continuous phase structure.
  • the first bonding layer 114 may be located above the integrated circuit die 103 and the encapsulation layer 120, and the first co-sintering layer 115 may be located above the first bonding layer 114 under the nano metal particle layer 110.
  • the first adhesive layer 114 includes, but is not limited to, any of the following materials: titanium, chromium, nickel, or nickel/vanadium.
  • the first subsequent layer 114 increases the bond strength between the integrated circuit die 103 and the first co-sintered layer 115.
  • the first co-sintered layer 115 includes, but is not limited to, any of the following materials: silver, gold, or copper.
  • FIG. 5 is a cross-sectional view showing a second embodiment of the first alloy layer 109 of FIG. FIG. 5 also shows only the upper half of the encapsulation layer 120 and the integrated circuit die 103.
  • the first alloy layer 109 of FIG. 4 further includes a first buffer layer 116 at the first Next between layer 114 and first co-sintered layer 115.
  • the first buffer layer 116 includes, but is not limited to, any of the following materials: aluminum, copper, or nickel.
  • the first buffer layer 116 provides a stress buffering function in the deformation due to the heat treatment, reducing the risk of cracks between the integrated circuit die 103 and the thermal interface material layer 114 or between the thermal interface material layers 114, increasing the reliability of the semiconductor device.
  • FIG 6 is a cross-sectional view of the first embodiment of the second alloy layer 112 of Figure 3.
  • the second alloy layer 112 includes a second co-sintered layer 118 and a second subsequent layer 117.
  • the second co-sintered layer 118 is thermally coupled to the nano-metal particle layer 110.
  • the contact of the second co-sintered layer 118 with the nano-metal particle layer 110 forms a sintered continuous phase structure.
  • the second adhesive layer 117 is thermally coupled to the heat sink 105.
  • the second co-sintered layer 118 may be located above the nano-metal particle layer 110
  • the second subsequent layer 117 may be located above the second co-sintered layer 118 under the heat sink 105.
  • the second co-sintered layer 118 includes, but is not limited to, any of the following materials: silver, gold, or copper.
  • the second adhesive layer 117 includes, but is not limited to, any of the following materials: titanium, chromium, nickel, or nickel/vanadium. The second adhesive layer 117 increases the bonding strength between the second co-sintered layer 115 and the heat sink 105.
  • FIG. 7 is a cross-sectional view showing a second embodiment of the second alloy layer 112 of FIG. 3.
  • the second alloy layer 112 of FIG. 7 further includes a second buffer layer 119 between the second adhesive layer 117 and the second co-sintered layer 118.
  • the second buffer layer 119 includes, but is not limited to, any of the following materials: aluminum, copper, nickel, or nickel/vanadium.
  • the second buffer layer 119 provides a buffering function in the deformation due to the heat treatment, reducing the risk of cracks occurring between the thermal interface material layer and the heat sink 105 or the thermal interface material layer 114, increasing the reliability of the semiconductor device.
  • the thermal interface material layer in the embodiment of the present invention no longer contains the polymer-based lower thermal conductive material in the silver-gel-like material, but contains the nano-metal particles, the thermal interface material in the embodiment of the present invention has The higher thermal conductivity greatly improves the thermal conductivity of the overall thermal path, and can better meet the heat dissipation requirements of the large power chip.
  • the laying area of the material layer of the large thermal interface increases the area of the contact surface of the thermal interface material layer, reduces the interface stress, and correspondingly improves the reliability of the component.
  • FIG. 8 is a flow chart 700 of a method of fabricating a semiconductor device in accordance with a second embodiment of the present invention.
  • an encapsulation layer is circumferentially disposed on a sidewall of the circuit device, wherein the circuit device includes an integrated circuit die, the integrated circuit die has a pin, and the integrated circuit die One side of the pin is a mounting surface, and the side wall of the circuit device is a wall adjacent to the mounting surface of the integrated circuit die; in step 704, a thermal interface material layer is generated, the heat The interface material layer has a first side facing the circuit device and the encapsulation layer and a second side facing the heat sink; in step 706, thermally coupling the first side to the circuit device and the encapsulation layer The second surface is thermally coupled to the heat sink.
  • the circumferentially encapsulating the encapsulation layer on the sidewall of the circuit device comprises using a plastic film as a material for fabricating the encapsulation layer to surround the encapsulation layer on the sidewall.
  • the plastic film has a good heat transfer effect, and can quickly transfer heat on the sidewall of the circuit device to the thermal interface material layer, thereby improving the heat dissipation efficiency of the circuit device.
  • a thermal interface material layer is formed, the thermal interface material layer having a first surface facing the circuit device and the encapsulation layer and a second surface facing the heat sink; specifically:
  • a first alloy layer is formed.
  • a layer of nano metal particles is formed from the inter-coupled nano metal particles and the intermediate mixture.
  • the diameter of the nano metal particles is no more than 1 micrometer, for example, the diameter of the nano metal particles is between 50 and 200 nanometers.
  • the intermediate mixture includes, but is not limited to, any of the following materials: air or resin.
  • the nano metal particles include, but are not limited to, silver.
  • a second alloy layer is formed. The first alloy layer is thermally coupled to the nanometal particle layer and the circuit device and the encapsulation layer. The second alloy layer is thermally coupled to the nano metal particle layer and the heat sink.
  • the contact between the first alloy layer and the nano metal particle layer forms a sintered continuous phase structure
  • the contact between the nano metal particles forms a sintered continuous phase structure
  • the second alloy layer and the nano metal particles are formed.
  • the contact of the layer forms a sintered continuous phase structure.
  • the method can be used with, but is not limited to, a flip chip ball grid array package structure.
  • generating the first alloy layer includes forming a first bonding layer and a first co-sintering layer, and thermally coupling the first bonding layer to the circuit device and the encapsulation layer to form the first co-sintered layer and the nano-metal particle layer Coupling, and forming a sintered continuous phase structure at the contact of the first co-sintered layer with the nano metal particle layer.
  • the first adhesive layer includes, but is not limited to, any of the following materials: titanium, chromium, nickel, or nickel/vanadium.
  • the first co-sintered layer includes, but is not limited to, any of the following materials: silver, gold or copper.
  • generating the first alloy layer further includes creating a first buffer layer between the first adhesive layer and the first co-sintered layer.
  • the first buffer layer includes, but is not limited to, any of the following materials: aluminum, copper, nickel, or nickel/vanadium.
  • generating the second alloy layer includes forming a second adhesive layer and a second co-sintered layer, and thermally coupling the second adhesive layer to the heat sink to thermally couple the second sintered layer to the nano metal particle layer, And forming a sintered continuous phase structure at the contact of the second co-sintered layer and the nano metal particle layer.
  • the second adhesive layer includes, but is not limited to, any of the following materials: titanium, chromium, nickel, or nickel/vanadium.
  • the second co-sintered layer includes, but is not limited to, any of the following materials: silver, gold or copper.
  • generating the second alloy layer further includes creating a second buffer layer between the second adhesive layer and the second co-sintered layer.
  • the second buffer layer includes, but is not limited to, any of the following materials: aluminum, copper, nickel, or nickel/vanadium.
  • the circuit device can include an integrated circuit die.
  • Thermally coupling the first alloy layer to the circuit device and the encapsulation layer includes thermally coupling the first alloy layer to the substrate and the encapsulation layer in the integrated circuit die.

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Abstract

一种半导体装置及制造方法，该装置包括：层叠设置的电路器件（103）及散热片（105），以及位于电路器件及散热片之间的热界面材料层（104）；其中，电路器件侧壁上环绕设置有封装层（120）；热界面材料层的第一面与电路器件及封装层热耦合，第二面与散热片热耦合。在上述方案中，采用封装层及电路器件均与热界面材料层热耦合，增大了电路器件与热界面材料层的接触面积，同时，电路器件侧壁上产生的热量可以通过封装层传递到热界面材料层上，再传递到散热片上，进而提高半导体装置的散热效果。通过在电路器件的外侧环绕的一层封装层，来增大热界面材料层的铺设面积，增大了热界面材料层接触面的面积，降低了界面应力，并相应的提升了组件信赖性。

Description

一种半导体装置及制造方法
本申请要求在2016年08月31日提交中国专利局、申请号为201610799678.X、发明名称为“一种半导体装置及制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体装置及制造方法。
背景技术
图1A所示为现有技术中集成电路芯片及其部分封装结构的截面示例图。该结构包括集成电路芯片1A02、热界面材料层1A04及散热器1A06。其中，热界面材料层1A04中具有以分散相形式分布的多个金属颗粒1A08，集成电路芯片1A02于工作过程中产生的热通过芯片背面的热界面材料层1A04倒入散热器1A06，但现有技术中，由于电路芯片1A02的尺寸的限定导致传递热量的效果较低，已很难满足大功率芯片的散热需求。
发明内容
本发明实施例提供一种半导体装置及制造方法。该半导体装置中，通过设置的封装层增大热界面材料层与电路器件的接触面积，大幅度提高了整体热通路的热导效能，能更好地满足大功耗电路器件的散热需求。
第一方面，本发明实施例提供了一种半导体装置，包括：层叠设置的电路器件及散热片，以及位于所述电路器件及所述散热片之间的热界面材料层；其中，
所述电路器件侧壁上环绕设置有封装层；所述电路器件包括集成电路管芯，所述集成电路管芯具有管脚，所述集成电路管芯上设置所述管脚的一面为安装面，所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁；
所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面，且所述第一面与所述电路器件及所述封装层热耦合，所述第二面与所述散热片热耦合。
在上述方案中，由于采用封装层环绕电路器件设置，并且封装层及电路器件均与热界面材料层热耦合，从而增大了电路器件与热界面材料层的接触面积，同时，电路器件侧壁上产生的热量可以通过封装层传递到热界面材料层上，再传递到散热片上，进而提高半导体装置的散热效果。同时，通过在电路器件的外侧环绕的一层封装层，来增大热界面材料层的铺设面积，增大了热界面材料层接触面的面积，降低了界面应力，并相应的提升了组件信赖性。
其中的封装层采用塑封膜层，该塑封膜层具有良好的传热效果，可以快速的将电路器件侧壁上的热量传递到热界面材料层上，进而提高了电路器件的散热效率。
其中的热界面材料层包括：第一合金层，与所述电路器件及所述封装层热耦合；纳米金属颗粒层，与所述第一合金层热耦合，所述纳米金属颗粒层包括相互耦合的多个纳米金属颗粒及中间混合物，所述中间混合物填充于所述多个纳米金属颗粒之间；及第二合金层，与所述纳米金属颗粒层及所述散热片热耦合。由于采用的热界面材料层中不再包含银胶类材料中的高分子类较低热导材料，而是包含纳米金属颗粒，本发明实施例中的热界面材料 具有较高导热率，大幅度提高了整体热通路的热导效能，能更好地满足大功耗芯片的散热需求。
在具体设置时，所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构，所述多个纳米金属颗粒之间的接触处形成烧结连续相结构，且所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。通过形成的烧结连续相结构提高了两者之间连接效果，并且提高了两者之间热传递的效果。
在一个具体的实施方案中，所述纳米金属颗粒包括银。具有良好的传热效果。并且在具体设置时，所述纳米金属颗粒的直径处于50-200纳米之间。
本实施例提供的半导体装置用于倒装芯片球栅格阵列封装结构。
其中的第一合金层包括第一接着层和第一共烧结层，所述第一接着层与所述电路器件及所述封装层热耦合，所述第一共烧结层与所述纳米金属颗粒层耦合，且所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。采用上述结构，提高了第一合金层与电路器件及封装层热耦合的连接强度，并且具有良好的热传递效果。
在具体设置时，第一接着层包括以下材料中的任一种：钛、铬、镍或镍钒合金，所述第一共烧结层包括以下材料中的任一种：银、金或铜。上述材料均具有较好的热传递效果。
此外，作为一个优选的方案，所述第一合金层还包括第一缓冲层，位于所述第一接着层与所述第一共烧结层之间，所述第一缓冲层包括以下材料中的任一种：铝、铜、镍或镍钒合金。
在具体设置时，所述第二合金层包括第二接着层和第二共烧结层，所述第二接着层与所述散热片热耦合，所述第二共烧结层与所述纳米金属颗粒层热耦合，且所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。采用上述结构，提高了第二合金层与散热片热耦合的连接强度，并且具有良好的热传递效果。
且在具体设置时，其中的第二接着层包括以下材料中的任一种：钛、铬、镍或镍钒合金，所述第二共烧结层包括以下材料中的任一种：银、金或铜。上述材料均具有较好的热传递效果。
作为一个优选的方案，所述第二合金层还包括第二缓冲层，位于所述第二接着层与所述第二共烧结层之间，所述第二缓冲层包括以下材料中的任一种：铝、铜、镍或镍钒合金。
其中的纳米金属颗粒的直径不大于1微米。
中间混合物可以选择不同的材料，在一个具体的实施方式中所述中间混合物包括以下材料中的任一种：空气或树脂。
本发明实施例提供了一种制造半导体装置的方法，包括：在电路器件的侧壁上环绕设置封装层；其中，所述电路器件包括集成电路管芯，所述集成电路管芯具有管脚，所述集成电路管芯上设置所述管脚的一面为安装面，所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁；
生成热界面材料层，所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面；
将第一面与所述电路器件及所述封装层热耦合，所述第二面与所述散热片热耦合。
在上述方案中，由于采用封装层环绕电路器件设置，并且封装层及电路器件均与热界面材料层热耦合，从而增大了电路器件与热界面材料层的接触面积，同时，电路器件侧壁上产生的热量可以通过封装层传递到热界面材料层上，再传递到散热片上，进而提高半导 体装置的散热效果。同时，通过在电路器件的外侧环绕的一层封装层，来增大热界面材料层的铺设面积，增大了热界面材料层接触面的面积，降低了界面应力，并相应的提升了组件信赖性。
在具体制备时，所述生成热界面材料层，所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面；具体为：
生成第一合金层；
由相互耦合的多个纳米金属颗粒与中间混合物生成纳米金属颗粒层，使所述中间混合物填充于所述多个纳米金属颗粒之间；
生成第二合金层，
使所述纳米金属颗粒层分别与所述第一合金层及第二合金层热耦合；其中，所述第一合金层背离所述纳米颗粒层一面为第一面，所述第二合金层背离所述纳米金属颗粒层的一面为第二面。
还包括：使所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构，使所述纳米金属颗粒之间的接触处形成烧结连续相结构，且使所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
其中的纳米金属颗粒的直径不大于1微米。
其中的中间混合物包括以下材料中的任一种：空气或树脂。
在具体制备第一合金层时，生成第一接着层和第一共烧结层，并使所述第一接着层与所述电路器件及所述封装层热耦合，使所述第一共烧结层与所述纳米金属颗粒层耦合，且使所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
在具体制备第二合金层时：生成第二接着层和第二共烧结层，并使所述第二接着层与所述散热片热耦合，使所述第二共烧结层与所述纳米金属颗粒层热耦合，且使所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
其中的，所述在电路器件的侧壁上环绕设置封装层包括以塑封膜作为制造所述封装层的材料，以在所述侧壁上环绕设置所述封装层。塑封膜具有良好的热传递效果，通过设置的塑封膜制备封装层提高了电路器件的散热效率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A是现有技术中包括半导体装置的封装结构的截面示例图；
图1B是本发明第一实施例的包括半导体装置的截面示例图；
图2是本发明第一实施例提供的半导体装置的电路器件与封装层结合的示意图；
图3是第一实施例中热界面材料层与电路器件及封装层热耦合的截面示例图；
图4是图3中的第一合金层的第一实施例的截面示例图；
图5是图3中的第一合金层的第二实施例的截面示例图；
图6是图3中的第二合金层的第一实施例的截面示例图；
图7是图3中第二合金层的第二实施例的截面示例图；
图8是本发明第二实施例的一种制造半导体装置的方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为了方便描述，本实施例定义了电路器件的侧壁，在本实施例中电路器件的侧壁是指，电路器件上与设置有管脚的一面(安装面)相邻的壁，在图1B中，图1B为本发明第一实施例提供的半导体装置的截面示例图，以半导体装置的放置方向为参考方向，该电路器件的侧壁为图1B中示出的在竖直方向的一面。
本发明实施例提供了一种半导体装置，该半导体装置包括：层叠设置的电路器件及散热片105，以及位于所述电路器件及所述散热片105之间的热界面材料层104；其中，
所述电路器件侧壁上环绕设置有封装层120；其中，所述电路器件包括集成电路管芯103，所述集成电路管芯103具有管脚，所述集成电路管芯103上设置所述管脚的一面为安装面，所述电路器件侧壁为所述集成电路管芯103上与所述安装面相邻的壁；
所述热界面材料层104具有朝向所述电路器件及所述封装层120的第一面以及朝向所述散热片105的第二面，且所述第一面与所述电路器件及所述封装层120热耦合，所述第二面与所述散热片105热耦合。
一并参考图1B及图2，图1B是本发明第一实施例包括半导体装置的截面示例图。图2为本实施例中电路器件与封装层结合的俯视图。图2为以图1B所示的器件的放置方向为参考方向，从上向下看到的电路器件(集成电路管芯103)与封装层120结构的示意图。在图2中，电路器件采用规则的矩形形状，应当理解的是，图2仅仅是为了示意电路器件与封装层120之间的位置关系，其中的电路器件的形状不仅限于上述图2中的矩形形状，还可以是其他的任意形状；结合图1B及图2可以看出，本实施例提供的封装层120环绕电路器件的侧壁设置，即封装层120可以看成围绕电路器件转一周形成的一个包裹电路器件侧壁的结构。即如图1B所示，在电路器件包括集成电路管芯103及底部填充物101时，封装层120包裹住集成电路管芯103及底部填充物101的侧壁，并且封装层120的顶面(图2中能够看到的封装层的一面)与集成电路管芯103的顶面(图2中能够看到的集成电路管芯103的一面)齐平，并与集成电路管芯103的顶面共同组成与热界面材料层104连接的接触面。散热片105通过粘接胶106固定在基板107上，集成电路管芯103的管脚与基板107上的电路连接。热界面材料层104与集成电路管芯103及散热片105热耦合。在具体设置时，热界面材料层104覆盖在集成电路管芯103及封装层120的顶面(即图2中示出的一面)并热耦合，由于封装层120具有一定的厚度d(即框形面的宽度)，因此，封装层120形成一个与热界面材料层104进行热耦合的框形的接触面(如图2所示)，且在具体设置时，封装层120具有设定厚度d以保证能够封装住电路器件，因此，框形接触面的框边具有一定的宽度(该宽度等于封装层120的厚度)，具体的，在没有封装层120时，耦合面积仅为集成电路管芯103的顶面面积，在增加上封装层120后，如图2所示，耦合面积为集成电路管芯103的顶面的面积加上封装层120顶面的面积，增大了热界面材料层104在与集成电路管芯103热耦合面的面积。此外，由于耦合面积的增大，进而增加了热界面材料层104与集成电路管芯103的连接强度，并且 降低了界面应力(整体应力不变，但接触面积增大，降低单位面积下应力影响)，提升组件信赖性表现。
此外，在具体设置时，由于封装层120贴附在电路器件的侧壁上，因此，在散热时，电路器件中侧壁上的热量可以通过封装层120传递到热界面材料层104上，进而扩散到散热片105上，在采用上述结构时，可以看出，电路器件的散热方式为：电路器件的顶面的热量通过热界面材料层104—散热片105的路径进行散热，电路器件的侧壁上的热量通过封装层120—热界面材料层104—散热片105的路径进行散热，从而增大了电路器件的散热面积，进而提高了电路器件的散热效果。
在一个具体的实施方式中，该封装层120采用塑胶膜层，塑胶膜层具有良好的封装效果以及热传递效果，从而可以快速的将热量传递到热界面材料层，进而提高电路器件的散热效果。
如图1B及图2所示，整个半导体装置在采用倒装芯片球栅格阵列封装结构时，包括焊球108，基板107，粘接胶106，金属凸块(BUMP)102，电路器件(如集成电路管芯103)，环绕该电路器件103的封装层120(如塑封膜层)，热界面材料层104及散热片105。集成电路管芯103通过金属凸块102与基板107耦合。金属凸块102由底部填充物101保护，封装层120环绕集成电路管芯103设置，且在具体设置时，本实施例中，热耦合包括不同层次，不同结构，或不同装置间有热传导的情形。更详细地，热界面材料层104可位于集成电路管芯103及散热片105之间，且集成电路管芯103的衬底与热界面材料层104热耦合，封装层也与热界面材料层104热耦合。集成电路管芯103的热量通过热界面材料层104达到散热片105。
其中，集成电路管芯103、环绕该电路器件103的封装层120、热界面材料层104及散热片105可作为一种半导体装置的部分或全部组件，且该半导体装置可用于但不限于如图所示的倒装芯片球栅格阵列封装结构。
图3是第一实施例中热界面材料层与电路器件及封装层热耦合的截面示例图；其中，图3中仅示出了图1B中热界面材料层104与集成电路管芯103连接的上半部分结构，封装层120也仅示出了封装层120的上半部分结构，该上半部分结构不包括底部填充物101。热界面材料层104与集成电路管芯103、封装层120及散热片105热耦合，包括第一合金层109、纳米金属颗粒层110及第二合金层112。
第一合金层109将集成电路管芯103及封装层120与纳米金属颗粒层110热耦合。更具体地，如图3所示，第一合金层109可位于集成电路管芯103及封装层120之上，纳米金属颗粒层110之下。即，第一合金层109可位于集成电路管芯103与纳米金属颗粒层110之间。第一合金层109增加集成电路管芯103与纳米金属颗粒层110之间的接着强度，并通过设置的封装层120增大了第一合金层109的覆盖面积，即增大了形成的第一合金层109的面积，进而提高了形成的热界面材料层的面积104。
纳米金属颗粒层110包括纳米金属颗粒及中间混合物。中间混合物包括但不限于以下材料中的任一种：空气或树脂。中间混合物用于填充于多个纳米金属颗粒之间，使多个纳米金属颗粒形成整体。纳米金属颗粒包括但不限于银。纳米金属颗粒的直径不大于1微米。在一个实施例中，纳米金属颗粒的直径处于50-200纳米之间。纳米金属颗粒层110热阻较低，形成较好的导热通路。
第二合金层112与纳米金属颗粒层110及散热片105热耦合。更具体地，如图所示，第二合金层112可位于纳米金属颗粒层110之上，散热片105之下。即，第二合金层112可位于 纳米金属颗粒层110与散热片105之间。第二合金层112增加纳米金属颗粒层110与散热片105之间的接着强度。
在一个实施例中，第一合金层109与纳米金属颗粒层110的接触处形成烧结连续相结构，纳米金属颗粒之间的接触处形成烧结连续相结构，且第二合金层112与纳米金属颗粒层110的接触处形成烧结连续相结构。本文中的烧结连续相结构包括但不限于：因金属颗粒产生烧结行为，金属颗粒接口附近的金属原子扩散至金属颗粒界面融合在一起，使得金属颗粒形成一个整体的结构。
图4是图3中第一合金层109的第一实施例的截面示例图。图4也仅示出了封装层120与集成电路管芯103的上半部分结构，如图所示，第一合金层109包括第一接着层114和第一共烧结层115。本文中的共烧结层包括但不限于：在封装加工过程中产生的与热界面材料层互融的金属层，该金属层与热界面材料层中的颗粒共同烧结形成热流通路。第一接着层114与集成电路管芯103及封装层120热耦合。第一共烧结层115与纳米金属颗粒层110热耦合。第一共烧结层115与纳米金属颗粒层110的接触处形成烧结连续相结构。具体地，第一接着层114可位于集成电路管芯103及封装层120之上，第一共烧结层115可位于第一接着层114之上，纳米金属颗粒层110之下。第一接着层114包括但不限于以下材料中的任一种：钛、铬、镍或镍/钒。第一接着层114增加集成电路管芯103与第一共烧结层115之间的结合强度。第一共烧结层115包括但不限于以下材料中的任一种：银、金或铜。
图5是图3中第一合金层109的第二实施例的截面示例图。图5也仅示出了封装层120与集成电路管芯103的上半部分结构，与图3相比，图4中的第一合金层109还包括第一缓冲层116，位于所述第一接着层114与第一共烧结层115之间。第一缓冲层116包括但不限于以下材料中的任一种：铝、铜或镍。第一缓冲层116在因热处理产生的形变中提供应力缓冲功能，降低集成电路管芯103与热界面材料层114间或热界面材料层114中间产生裂缝的风险，增加该半导体装置的可靠性。
图6是图3中第二合金层112的第一实施例的截面示例图。如图所示，第二合金层112包括第二共烧结层118和第二接着层117。第二共烧结层118与纳米金属颗粒层110热耦合。第二共烧结层118与纳米金属颗粒层110的接触处形成烧结连续相结构。第二接着层117与散热片105热耦合。具体地，第二共烧结层118可位于纳米金属颗粒层110之上，第二接着层117可位于第二共烧结层118之上，散热片105之下。第二共烧结层118包括但不限于以下材料中的任一种：银、金或铜。第二接着层117包括但不限于以下材料中的任一种：钛、铬、镍或镍/钒。第二接着层117增加第二共烧结层115与散热片105之间的结合强度。
图7是图3中第二合金层112的第二实施例的截面示例图。与图6相比，图7中的第二合金层112还包括第二缓冲层119，位于第二接着层117与第二共烧结层118之间。第二缓冲层119包括但不限于以下材料中的任一种：铝、铜、镍或镍/钒。第二缓冲层119在因热处理产生的形变中提供缓冲功能，降低热界面材料层与散热片105间或热界面材料层114中间产生裂缝的风险，增加该半导体装置的可靠性。
综上，由于本发明实施例中的热界面材料层中不再包含银胶类材料中的高分子类较低热导材料，而是包含纳米金属颗粒，本发明实施例中的热界面材料具有较高导热率，大幅度提高了整体热通路的热导效能，能更好地满足大功耗芯片的散热需求，同时，通过在集成电路管芯103的外侧环绕一层封装层120，来增大热界面材料层的铺设面积，增大了热界面材料层接触面的面积，降低了界面应力，并相应的提升了组件信赖性。
图8是本发明第二实施例的一种制造半导体装置的方法的流程图700。如图所示，在步骤702中，在电路器件的侧壁上环绕设置封装层，其中，所述电路器件包括集成电路管芯，所述集成电路管芯具有管脚，所述集成电路管芯上设置所述管脚的一面为安装面，所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁；在步骤704中，生成热界面材料层，所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面；在步骤706中，将第一面与所述电路器件及所述封装层热耦合，所述第二面与所述散热片热耦合。
此外，所述在电路器件的侧壁上环绕设置封装层包括以塑封膜作为制造所述封装层的材料，以在所述侧壁上环绕设置所述封装层。塑封膜具有良好的传热效果，可以快速的将电路器件侧壁上的热量传递到热界面材料层上，进而提高了电路器件的散热效率。
在具体制备时，生成热界面材料层，所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面；具体为：
生成第一合金层。由相互耦合的纳米金属颗粒与中间混合物生成纳米金属颗粒层。纳米金属颗粒的直径不大于1微米，例如，纳米金属颗粒的直径处于50-200纳米之间。中间混合物包括但不限于以下材料中的任一种：空气或树脂。在一个实施例中，纳米金属颗粒包括但不限于银。生成第二合金层。使第一合金层将纳米金属颗粒层与电路器件及封装层热耦合。使第二合金层与纳米金属颗粒层及散热片热耦合。
在一个实施例中，使第一合金层与纳米金属颗粒层的接触处形成烧结连续相结构，使纳米金属颗粒之间的接触处形成烧结连续相结构，且使第二合金层与纳米金属颗粒层的接触处形成烧结连续相结构。
在一个实施例中，该方法可用于但不限于倒装芯片球栅格阵列封装结构。
在一个实施例中，生成第一合金层包括生成第一接着层和第一共烧结层，并使第一接着层与电路器件及封装层热耦合，使第一共烧结层与纳米金属颗粒层耦合，且使第一共烧结层与纳米金属颗粒层的接触处形成烧结连续相结构。第一接着层包括但不限于以下材料中的任一种：钛、铬、镍或镍/钒。第一共烧结层包括但不限于以下材料中的任一种：银、金或铜。在另一个实施例中，生成第一合金层还包括在第一接着层与第一共烧结层之间生成第一缓冲层。第一缓冲层包括但不限于以下材料中的任一种：铝、铜、镍或镍/钒。
在一个实施例中，生成第二合金层包括生成第二接着层和第二共烧结层，并使第二接着层与散热片热耦合，使第二共烧结层与纳米金属颗粒层热耦合，且使所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。第二接着层包括但不限于以下材料中的任一种：钛、铬、镍或镍/钒。第二共烧结层包括但不限于以下材料中的任一种：银、金或铜。在另一个实施例中，生成第二合金层还包括在第二接着层与第二共烧结层之间生成第二缓冲层。第二缓冲层包括但不限于以下材料中的任一种：铝、铜、镍或镍/钒。
电路器件可包括集成电路管芯。使第一合金层与电路器件及封装层热耦合包括使第一合金层与集成电路管芯中的衬底及封装层热耦合。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (17)

  1. 一种半导体装置，其特征在于，包括：层叠设置的电路器件及散热片，以及位于所述电路器件及所述散热片之间的热界面材料层；其中，
    所述电路器件侧壁上环绕设置有封装层；所述电路器件包括集成电路管芯，所述集成电路管芯具有管脚，所述集成电路管芯上设置所述管脚的一面为安装面，所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁；
    所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面，且所述第一面与所述电路器件及所述封装层热耦合，所述第二面与所述散热片热耦合。
  2. 如权利要求1所述的半导体装置，其特征在于，所述封装层为塑封膜层。
  3. 如权利要求1或2所述的半导体装置，其特征在于，所述热界面材料层包括：
    第一合金层，与所述电路器件及所述封装层热耦合；
    纳米金属颗粒层，与所述第一合金层热耦合，所述纳米金属颗粒层包括相互耦合的多个纳米金属颗粒及中间混合物，所述中间混合物填充于所述多个纳米金属颗粒之间；及
    第二合金层，与所述纳米金属颗粒层及所述散热片热耦合。
  4. 如权利要求3所述的半导体装置，其特征在于，所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构，所述多个纳米金属颗粒之间的接触处形成烧结连续相结构，且所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  5. 如权利要求1～4中任一项所述的半导体装置，其特征在于，用于倒装芯片球栅格阵列封装结构。
  6. 如权利要求3～5中任一项所述的半导体装置，其特征在于，第一合金层包括第一接着层和第一共烧结层，所述第一接着层与所述电路器件及所述封装层热耦合，所述第一共烧结层与所述纳米金属颗粒层耦合，且所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  7. 如权利要求6所述的半导体装置，其特征在于，所述第一接着层包括以下材料中的任一种：钛、铬、镍或镍钒合金，所述第一共烧结层包括以下材料中的任一种：银、金或铜。
  8. 如权利要求6或7所述的半导体装置，其特征在于，所述第一合金层还包括第一缓冲层，位于所述第一接着层与所述第一共烧结层之间，所述第一缓冲层包括以下材料中的任一种：铝、铜、镍或镍钒合金。
  9. 如权利要求3～8中任一项所述的半导体装置，其特征在于，所述第二合金层包括第二接着层和第二共烧结层，所述第二接着层与所述散热片热耦合，所述第二共烧结层与所述纳米金属颗粒层热耦合，且所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  10. 如权利要求8或9所述的半导体装置，其特征在于，所述第二合金层还包括第二缓冲层，位于所述第二接着层与所述第二共烧结层之间，所述第二缓冲层包括以下材料中的任一种：铝、铜、镍或镍钒合金。
  11. 如权利要求3～10中任一所述的半导体装置，其特征在于，所述中间混合物包括以下材料中的任一种：空气或树脂。
  12. 一种半导体装置的制造方法，其特征在于，包括：
    在电路器件的侧壁上环绕设置封装层；其中，所述电路器件包括集成电路管芯，所述集成电路管芯具有管脚，所述集成电路管芯上设置所述管脚的一面为安装面，所述电路器件侧壁为所述集成电路管芯上与所述安装面相邻的壁；
    生成热界面材料层，所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面；
    将第一面与所述电路器件及所述封装层热耦合，所述第二面与所述散热片热耦合。
  13. 如权利要求12所述的制造方法，其特征在于，所述生成热界面材料层，所述热界面材料层具有朝向所述电路器件及所述封装层的第一面以及朝向所述散热片的第二面；具体为：
    生成第一合金层；
    由相互耦合的多个纳米金属颗粒与中间混合物生成纳米金属颗粒层，使所述中间混合物填充于所述多个纳米金属颗粒之间；
    生成第二合金层，
    使所述纳米金属颗粒层分别与所述第一合金层及第二合金层热耦合；其中，所述第一合金层背离所述纳米颗粒层一面为第一面，所述第二合金层背离所述纳米金属颗粒层的一面为第二面。
  14. 如权利要求13所述的制造方法，其特征在于，还包括使所述第一合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构，使所述纳米金属颗粒之间的接触处形成烧结连续相结构，且使所述第二合金层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  15. 如权利要求13或14所述的制造方法，其特征在于，所述生成第一合金层包括：生成第一接着层和第一共烧结层，并使所述第一接着层与所述电路器件及所述封装层热耦合，使所述第一共烧结层与所述纳米金属颗粒层耦合，且使所述第一共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  16. 如权利要求13～15中任一所述的制造方法，其特征在于，所述生成第二合金层包括：生成第二接着层和第二共烧结层，并使所述第二接着层与所述散热片热耦合，使所述第二共烧结层与所述纳米金属颗粒层热耦合，且使所述第二共烧结层与所述纳米金属颗粒层的接触处形成烧结连续相结构。
  17. 如权利要求12～16所述的制造方法，其特征在于，所述在电路器件的侧壁上环绕设置封装层包括以塑封膜作为制造所述封装层的材料，以在所述侧壁上环绕设置所述封装层。
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Publication number Priority date Publication date Assignee Title
CN106356341A (zh) * 2016-08-31 2017-01-25 华为技术有限公司 一种半导体装置及制造方法
US11621211B2 (en) 2019-06-14 2023-04-04 Mediatek Inc. Semiconductor package structure
CN110648924A (zh) * 2019-09-04 2020-01-03 广东芯华微电子技术有限公司 大板扇出型芯片封装结构及其制作方法
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1885850A (zh) * 2005-06-21 2006-12-27 马维尔国际贸易有限公司 无线局域网通信模块和集成芯片封装
CN1917200A (zh) * 2005-08-19 2007-02-21 南茂科技股份有限公司 散热型球格阵列封装结构
CN106356341A (zh) * 2016-08-31 2017-01-25 华为技术有限公司 一种半导体装置及制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3608542B2 (ja) * 2001-10-22 2005-01-12 セイコーエプソン株式会社 半導体装置の製造方法
US20080023665A1 (en) * 2006-07-25 2008-01-31 Weiser Martin W Thermal interconnect and interface materials, methods of production and uses thereof
US7535099B2 (en) * 2006-09-26 2009-05-19 Intel Corporation Sintered metallic thermal interface materials for microelectronic cooling assemblies
US8030757B2 (en) * 2007-06-29 2011-10-04 Intel Corporation Forming a semiconductor package including a thermal interface material
US20100328895A1 (en) * 2007-09-11 2010-12-30 Dorab Bhagwagar Composite, Thermal Interface Material Containing the Composite, and Methods for Their Preparation and Use
US7838975B2 (en) * 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
KR20120053332A (ko) * 2010-11-17 2012-05-25 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR101411813B1 (ko) * 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
TWI529880B (zh) * 2013-06-19 2016-04-11 日月光半導體製造股份有限公司 半導體元件，半導體封裝結構及其製造方法
CN104241218A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种带有散热结构的倒装芯片塑封结构及制造方法
TWI563615B (en) * 2015-05-05 2016-12-21 Siliconware Precision Industries Co Ltd Electronic package structure and the manufacture thereof
CN105355610B (zh) * 2015-08-27 2019-01-18 华为技术有限公司 一种电路装置及制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1885850A (zh) * 2005-06-21 2006-12-27 马维尔国际贸易有限公司 无线局域网通信模块和集成芯片封装
CN1917200A (zh) * 2005-08-19 2007-02-21 南茂科技股份有限公司 散热型球格阵列封装结构
CN106356341A (zh) * 2016-08-31 2017-01-25 华为技术有限公司 一种半导体装置及制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3503176A4 *

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