TW201926607A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW201926607A
TW201926607A TW106141602A TW106141602A TW201926607A TW 201926607 A TW201926607 A TW 201926607A TW 106141602 A TW106141602 A TW 106141602A TW 106141602 A TW106141602 A TW 106141602A TW 201926607 A TW201926607 A TW 201926607A
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Taiwan
Prior art keywords
electronic
electronic component
conductive
package
electronic package
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TW106141602A
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English (en)
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TWI643302B (zh
Inventor
蔡文山
鄭子企
林長甫
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW106141602A priority Critical patent/TWI643302B/zh
Priority to CN201711353996.4A priority patent/CN109841605A/zh
Priority to US16/170,904 priority patent/US10600708B2/en
Application granted granted Critical
Publication of TWI643302B publication Critical patent/TWI643302B/zh
Publication of TW201926607A publication Critical patent/TW201926607A/zh

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

一種電子封裝件及其製法，係於承載結構上設置一具有導電體之電子元件，再以包覆層包覆該電子元件，之後將電子裝置設於該包覆層上，以利用該導電體電性連接該承載結構與該電子裝置，而降低該電子封裝件之整體厚度。

Description

電子封裝件及其製法
本發明係有關一種電子封裝件及其製法，尤指一種封裝堆疊結構及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，業界遂發展出堆疊複數封裝結構以形成封裝堆疊結構(Package on Package，POP)之封裝型態，此種封裝型態能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，而適用於各種輕薄短小型電子產品。
第1圖係為習知封裝堆疊結構1之剖面示意圖。如第1圖所示，該封裝堆疊結構1係包含有半導體元件11、下層封裝基板10、上層封裝基板12、複數支撐銲球13、電子裝置16(如記憶體晶片或記憶體封裝結構)以及封裝膠體14。該半導體元件11以覆晶方式設於該下層封裝基板10上，且該電子裝置16亦以覆晶方式設於於該上層封裝 基板12上。該些支撐銲球13係用以連結且電性耦接該下層封裝基板10與該上層封裝基板12。該封裝膠體14係包覆該些支撐銲球13與該半導體元件11。可選擇性地，形成底膠19於該半導體元件11與該下層封裝基板10之間。
惟，前述習知封裝堆疊結構1中，該上層封裝基板12係為有機封裝基板，其可為具有核心層120或無核心(coreless)型式，然其厚度d極厚，約為150至800微米(um)，故該封裝堆疊結構1之整體厚度D難以降低，因而無法符合現今終端電子產品輕薄短小之需求。
再者，即使採用厚度d最薄之上層封裝基板12，然因該支撐銲球13之高度R需大於該半導體元件11之高度r，以避免該半導體元件11碰撞該上層封裝基板12而損壞之問題，故該封裝堆疊結構1之整體厚度D因受限於該支撐銲球13之高度R而難以縮減至小於240微米。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種電子封裝件，係包括：承載結構；電子元件，係設於該承載結構上，其中，該電子元件具有相對之第一側與第二側，並以該第一側結合於該承載結構上；導電體，係形成於該電子元件中並連通該第一側與第二側且電性連接該承載結構；包覆層，係形成於該承載結構上以包覆該電子元件，且令該導電體外露出該包覆層；以及電子裝置，係接置於該包覆層 上且電性連接該導電體。
本發明復提供一種電子封裝件之製法，係包括：設置至少一電子元件於一承載結構上，其中，該電子元件具有相對之第一側與第二側，並以該第一側結合於該承載結構上，且於該電子元件中形成有複數連通該第一側與第二側且電性連接該承載結構之導電體；形成包覆層於該承載結構上以包覆該電子元件，且令該導電體外露出該包覆層；以及接置電子裝置於該包覆層上，且令該電子裝置電性連接該導電體。
前述之電子封裝件及其製法中，該電子元件於該第一側或第二側設有複數電極墊，以電性連接該承載結構。
前述之電子封裝件及其製法中，該導電體係凸伸出該電子元件之第二側。
前述之電子封裝件及其製法中，該電子裝置與該包覆層之間係形成有絕緣材。例如，該絕緣材係為介電材、封裝材或非導電性薄膜。
由上可知，本發明之電子封裝件及其製法，主要藉由該電子元件中形成該導電體，以利用該導電體電性連接該承載結構與該電子裝置，故相較於習知技術，本發明之電子封裝件能省略習知上層封裝基板與支撐銲球之配置，因而不僅能省略材料使用及製程步驟，且能大幅降低該電子封裝件之整體厚度，以符合電子產品輕薄短小的趨勢。
1‧‧‧封裝堆疊結構
10‧‧‧下層封裝基板
11‧‧‧半導體元件
12‧‧‧上層封裝基板
120‧‧‧核心層
13‧‧‧支撐銲球
14‧‧‧封裝膠體
16,26‧‧‧電子裝置
19,29‧‧‧底膠
2,3,4‧‧‧電子封裝件
20‧‧‧承載結構
21,41‧‧‧電子元件
21a‧‧‧第一側
21b‧‧‧第二側
210,410‧‧‧電極墊
22‧‧‧導電凸塊
23‧‧‧導電體
23a‧‧‧第一端部
23b‧‧‧第二端部
24,34‧‧‧包覆層
24a‧‧‧第一表面
24b‧‧‧第二表面
25‧‧‧銲錫材料
260‧‧‧導電元件
27,28‧‧‧絕緣材
42‧‧‧銲線
D,d,H,h,T,t‧‧‧厚度
R,r‧‧‧高度
第1圖係為習知封裝堆疊結構之剖面示意圖； 第2A至2D圖係為本發明之電子封裝件之製法之剖視示意圖；第2E圖係為第2D圖之另一實施例之局部剖視示意圖；以及第3及4圖係為第2D圖之其它不同實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2D圖，係為本發明之電子封裝件之製法之剖視示意圖。
如第2A圖所示，於一承載結構20上設置至少一具有 複數導電體23之電子元件21。
於本實施例中，該承載結構20係為如具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構，其具有複數線路層，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RIDL)。應可理解地，該承載結構亦可為其它可供承載如晶片等電子元件21之承載單元，例如導線架(leadframe)，並不限於上述。
再者，該電子元件21係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件21係為半導體晶片，其具有相對之第一側21a(於此視為作用面)與第二側21b(於此視為非作用面)，且該第一側21a具有複數電極墊210，令該電極墊210藉由複數如銲錫材料之導電凸塊22以覆晶方式電性連接該承載結構20。或者，如第4圖所示，該電子元件41亦可於該第二側21b(於此視為作用面)上配置該電極墊410，並藉由複數銲線42以打線方式電性連接該承載結構20。然而，有關該電子元件電性連接該承載結構之方式不限於上述。
又，該導電體23係以矽穿孔(Through-silicon via，簡稱TSV)製程製作成如銅柱之金屬柱以穿設於該電子元件21中，且該導電體23係具有相對之第一端部23a與第二端部23b，且該第一端部23a外露出該第一側21a，以令該第一端部23a藉由複數如銲錫材料之導電凸塊22電性連接該承載結構20。
另外，可選擇性形成底膠29於該承載結構20與該電子元件21之第一側21a之間，以包覆該些導電凸塊22。
如第2B圖所示，形成一包覆層24於該承載結構20上以包覆該電子元件21。
於本實施例中，利用壓合(lamination)或模壓(molding)或其它方式形成該包覆層24，其材質可為介電材或封裝材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝化合物(molding compound)，但並不限於上述。
再者，該包覆層24係定義有相對之第一表面24a與第二表面24b，使該包覆層24以其第一表面24a結合該承載結構20。
又，如第3圖所示，包覆層34可選擇性形成於該承載結構20與該電子元件21之第一側21a之間，以包覆該些導電凸塊22。
另外，如第4圖所示，該包覆層24係包覆該些銲線42。
如第2C圖所示，移除該包覆層24之部分材質與該電子元件21之部分材質，使該導電體23外露出該包覆層24，且該導電體23連通該電子元件21之第一側21a與第二側21b。
於本實施例中，該導電體23之第二端部23b係凸伸出該電子元件21之第二側21b。例如，係以整平製程移除該電子元件21之第二側21b之部分材質，使該導電體23之 第二端部23b與該電子元件21之第二側21b共平面(齊平)，再蝕刻該電子元件21之第二側21b之部分材質，以令該導電體23之第二端部23b凸伸出該電子元件21之第二側21b。
具體地，藉由研磨或切除等適當方式，移除該包覆層24之第二表面24b之部分材質、該導電體23之第二端部23b之部分材質與該電子元件21之第二側21b之部分材質，使該包覆層24之第二表面24b、該導電體23之第二端部23b與該電子元件21之第二側21b共平面(齊平)，此時，該電子元件21(或該包覆層24、或該導電體23)之厚度T係小於100微米。接著，以乾式蝕刻製程，如電漿方式、反應式離子蝕刻(Reactive Ion Etching，簡稱RIE)或其它蝕刻方式，移除該電子元件21之第二側21b約10微米厚度t之材質，以令該導電體23之第二端部23b凸伸出該電子元件21之第二側21b。
再者，有關該導電體23之第二端部23b外露出該包覆體24之方式並不限於上述，且該導電體23連通該電子元件21之第一側21a與第二側21b之方式也不限於上述。
另外，可於該承載結構20之底面(植球側)上形成複數如銲球之銲錫材料25，俾供接置一電路板。
如第2D圖所示，將一電子裝置26藉由複數導電元件260設於該包覆層24之第二表面24b上，且該電子裝置26係透過該些導電元件260電性連接該導電體23，以成為封裝堆疊(Package on Package，簡稱POP)型式之電子封裝件 2。
於本實施例中，該電子裝置26例如為高頻寬記憶體(High Bandwidth Memory，簡稱HBM)型式之封裝結構，且該導電元件260係例如含有銲錫材料之導電凸塊。
再者，於該電子裝置26設於該包覆層24之第二表面24b上後，藉由絕緣材27包覆該些導電元件260以保護該些導電元件260及增加該電子封裝件2之剛性強度，其中，該絕緣材27之材質係為介電材或封裝材。
或者，如第2E圖所示，可先於該電子裝置26上形成一包覆該些導電元件260之絕緣材28，以於該絕緣材28結合於該包覆層24之第二表面24b上，而使該些導電元件260對應銲接結合及電性連接該些導電體23時，得以透過該絕緣材28保護該些導電元件260及增加該電子封裝件2之剛性強度，其中，該絕緣材28可具有助銲(flux)之功能，其為非導電性薄膜(Non-conductive Film，簡稱NCF)，例如，異方性導電膠(Anisotropic conductive paste，簡稱ACP)、異方性導電膠膜(Anisotropic Conductive Film，簡稱ACF)。
因此，本發明之製法係藉由該電子元件21,41中形成該導電體23，以利用該導電體23電性連接該承載結構20與該電子裝置26，故相較於習知技術，本發明之電子封裝件能省略習知上層封裝基板與支撐銲球之配置，因而不僅能省略材料使用及製程步驟，以降低製作成本，且其整體厚度H(省略導電元件260)僅需考量該電子元件21,41之 最終厚度h(或該導電體23之厚度T)，因而能大幅降低該電子封裝件2,3,4之整體厚度H，使該厚度H小於240微米，以符合電子產品輕薄短小的趨勢。
本發明復提供一種電子封裝件2,3,4，係包括：一承載結構20、一電子元件21,41、複數導電體23、一包覆層24,34以及一電子裝置26。
所述之電子元件21,41係設於該承載結構20上，其中，該電子元件21係具有相對之第一側21a與第二側21b，該電子元件21係以第一側21a結合於該承載結構20上。
所述之導電體23係形成於該電子元件21,41中並連通該第一側21a與第二側21b且電性連接該承載結構20。
所述之包覆層24,34係形成於該承載結構20上以包覆該電子元件21,41，且令該導電體23外露出該包覆層24,34。
所述之電子裝置26係接置於該包覆層24,34上且電性連接該導電體23。
於一實施例中，該電子元件21,41係具有設於第一側21a或第二側21b之電極墊210,410，以電性連接該承載結構20。
於一實施例中，該導電體23係凸伸出該電子元件21,41之第二側21b。
於一實施例中，該電子裝置26與該包覆層24,34之間係形成有絕緣材27,28。例如，該絕緣材27,28係為介電材、封裝材或非導電性薄膜。
綜上所述，本發明之電子封裝件及其製法，主要藉由 在電子元件中形成導電體，以利用該導電體電性連接用以承載該電子元件之承載結構與設於該承載結構上之電子裝置，故本發明之電子封裝件及其製法不僅能省略習知上層封裝基板與支撐銲球之配置，且能降低製作成本及電子封裝件之整體厚度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (10)

  1. 一種電子封裝件，係包括：承載結構；電子元件，係設於該承載結構上，其中，該電子元件係具有相對之第一側與第二側，並以該第一側結合至該承載結構上；複數導電體，係形成於該電子元件中並連通該第一側與第二側且電性連接該承載結構；包覆層，係形成於該承載結構上以包覆該電子元件，且令該導電體外露出該包覆層；以及電子裝置，係接置於該包覆層上且電性連接該導電體。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件於該第一側或第二側設有複數電極墊，以電性連接該承載結構。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該導電體係凸伸出該電子元件之第二側。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該電子裝置與該包覆層之間係形成有絕緣材。
  5. 如申請專利範圍第4項所述之電子封裝件，其中，該絕緣材係為介電材、封裝材或非導電性薄膜。
  6. 一種電子封裝件之製法，係包括：設置至少一電子元件於一承載結構上，其中，該電子元件具有相對之第一側與第二側，並以該第一側結 合於該承載結構上，且於該電子元件中形成有複數連通該第一側與第二側且電性連接該承載結構之導電體；形成包覆層於該承載結構上以包覆該電子元件，且令該導電體外露出該包覆層；以及接置電子裝置於該包覆層上，且令該電子裝置電性連接該導電體。
  7. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該電子元件於該第一側或第二側設有複數電極墊，以電性連接該承載結構。
  8. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該導電體係凸伸出該電子元件之第二側。
  9. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該電子裝置與該包覆層之間係形成有絕緣材。
  10. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該絕緣材係為介電材、封裝材或非導電性薄膜。
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