TWI508273B - 影像感測元件封裝構件及其製作方法 - Google Patents

影像感測元件封裝構件及其製作方法 Download PDF

Info

Publication number
TWI508273B
TWI508273B TW100109413A TW100109413A TWI508273B TW I508273 B TWI508273 B TW I508273B TW 100109413 A TW100109413 A TW 100109413A TW 100109413 A TW100109413 A TW 100109413A TW I508273 B TWI508273 B TW I508273B
Authority
TW
Taiwan
Prior art keywords
image sensing
layer
package member
device package
sensing device
Prior art date
Application number
TW100109413A
Other languages
English (en)
Other versions
TW201143074A (en
Inventor
Shu Ming Chang
Tien Hao Huang
Original Assignee
Xintec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xintec Inc filed Critical Xintec Inc
Publication of TW201143074A publication Critical patent/TW201143074A/zh
Application granted granted Critical
Publication of TWI508273B publication Critical patent/TWI508273B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14636Interconnect structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14632Wafer-level processed structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687Wafer level processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • H01L2224/02313Subtractive methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02331Multilayer structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02371Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02372Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0239Material of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/024Material of the insulating layers therebetween
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13024Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29011Shape comprising apertures or cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/2908Plural core members being stacked
    • H01L2224/29082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/9202Forming additional connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14618Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

影像感測元件封裝構件及其製作方法
本發明係有關於光學元件封裝技術領域,特別是有關於一種具備多層重佈線路(multi-layer RDL)的影像感測元件封裝構件及其製作方法。
近年來,固態影像感測元件已被大量運用在手機、汽車以及電腦產業,然而,當固態影像感測元件朝向更高的圖元解析度與更小的圖元尺寸發展時,良率卻受到衝擊,而相機模組在組裝過程中的物理性污染,也會降低良率。因此,封裝半導體晶粒逐漸成為在業界中被廣泛採用的方案。其中,由於晶圓級技術在製程上具備經濟效益,逐漸成為較佳的解決方案。
晶圓級封裝較具挑戰性的層面之一,就是內部連結設計。在頂部、側面、底部接點三種選擇中,又以底部接點最具吸引力,因為它能使影像感測晶粒能正面朝上,以配合相機模組組裝所需的方向。由於高解析度影像感測器越來越需要高密度焊接墊,因此和焊接墊相容的直通矽晶穿孔技術(through silicon via,簡稱為TSV)也隨之受到注目。
本發明之主要目的即在提供一種採用直通矽晶穿孔技術及具備多層重佈線路的影像感測元件封裝構件及其製作方法。
本發明較佳實施例提供一種影像感測元件封裝構件,包含有:一影像感測晶粒,其具有一主動面以及相對於該主動面的一背面,且在該主動面上設有一影像感測元件區域以及一外接墊;一直通矽晶穿孔結構,貫穿該影像感測晶粒,連接該外接墊;一第一絕緣層,形成在該影像感測晶粒的該背面及該矽晶穿孔結構內;一第一重佈線路層,形成在該第一絕緣層上並與該外接墊電連接;一第二絕緣層,覆蓋該第一重佈線路層及該第一絕緣層;一第二重佈線路層,形成在該第二絕緣層上並與該第一重佈線路層電連接;以及一防焊層,覆蓋在該第二重佈線路層及該第二絕緣層上。
從另一角度來看,本發明提供一種影像感測元件封裝構件,包含有:一影像感測晶粒,其具有一主動面以及相對於該主動面的一背面,且在該主動面上設有一影像感測元件區域以及一外接墊;一直通矽晶穿孔結構,貫穿該影像感測晶粒,連接該外接墊;複數層重佈線路,形成在該像感測晶粒的該背面上;以及一防焊層,覆蓋在該複數層重佈線路上。其中在該防焊層中設有至少一開孔,曝露出一焊接墊,並在該焊接墊上設有一焊接錫球。在該防焊層中設有複數個假開孔,用來釋放應力。該複數層重佈線路至少包含有一防電磁干擾金屬圖案。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉較佳實施方式,並配合所附圖式,作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用,並非用來對本發明加以限制者。
本發明運用創新的連結技術,貫穿矽晶層直接連結至影像感測晶粒的外接墊;小巧的尺寸與連結的位置,讓封裝背面可支援高密度的球閘陣列封裝介面,使後續的封裝相容於表面黏著組裝製程。本發明可以相容於晶圓級封裝(wafer-level packaging,簡稱為WLP)製程並且採用直通矽晶穿孔技術,其中所謂的晶圓級封裝製程係在晶圓狀態時就封裝晶粒,再進行後段組裝製程,然後,晶圓再進行切割,成為獨立封裝晶粒。
請參閱第1圖,其為依據本發明一較佳實施例所繪示的影像感測元件封裝構件的剖面示意圖。如第1圖所示,影像感測元件封裝構件1包含有一影像感測晶粒10,其具有一主動面10a以及相對於主動面(active side)10a的一背面(backside)10b,且在主動面10a上設有一影像感測元件區域11以及外接墊12。影像感測元件區域11可以是CMOS影像感測元件,但不限於此。
在影像感測晶粒10的主動面10a上另覆蓋一封裝用光學蓋板20,例如,透鏡等級玻璃或石英,而在封裝用光學蓋板20與影像感測晶粒10的主動面10a之間另設有支撐堰體結構22,例如,環氧樹脂(epoxy resin)、聚亞醯胺(polyimide)、光阻或防焊阻劑(solder resist)材料等等,如此使光學蓋板20、支撐堰體結構22與影像感測晶粒10的主動面10a之間構成一密閉的凹穴結構24,而影像感測元件區域11就是位於凹穴結構24內部。此外,支撐堰體結構22與影像感測晶粒10的主動面10a之間可以利用接合材料(圖未示)進行黏合。
根據本發明之較佳實施例,影像感測元件封裝構件1另包含有一直通矽晶穿孔(TSV)結構13,其貫穿影像感測晶粒10,並連通影像感測晶粒10的主動面10a與背面10b,用來曝露出位於影像感測晶粒10的主動面10a上部分的外接墊12。在影像感測晶粒10的背面10b以及矽晶穿孔結構13的側壁上則順應的形成有第一絕緣層14,例如,氧化矽、氮化矽或氮氧化矽等等。此外,第一絕緣層14也可以採用有機高分子絕緣材料。
在第一絕緣層14上形成有一第一重佈線路層15,例如,鋁金屬線路圖案或者銅金屬線路圖案。第一重佈線路層15順應的覆蓋在矽晶穿孔結構13的側壁上以及底部,並且與外接墊12電連接。此外,第一重佈線路層15至少包含有一連接墊15a。在第一重佈線路層15以及第一絕緣層14上另有一第二絕緣層16,例如,氧化矽、氮化矽或氮氧化矽等等。第二絕緣層16也可以採用有機高分子絕緣材料。在第二絕緣層16中設有至少一開孔16a,曝露出部分的連接墊15a。
在第二絕緣層16上形成有一第二重佈線路層17,例如,鈦、銅、鎳、金、鋁或上述金屬之組合。第二重佈線路層17可以是由可焊接(soldable)金屬材料所構成者。第二重佈線路層17與第一重佈線路層15可以採用相同的導電材料或者不同的導電材料,也可以是不同的厚度。第二重佈線路層17填入開孔16a,並與曝露出的連接墊15a電連接。第二重佈線路層17至少包含有一焊接墊(solder pad)17a。在第二重佈線路層17以及第二絕緣層16上另有一防焊層18,例如,環氧樹脂、聚亞醯胺、光阻等等。在防焊層18中設有至少一開孔18a,曝露出部分的焊接墊17a。在焊接墊17a上則設有焊接錫球19。
請參閱第2圖,其為依據本發明另一較佳實施例所繪示的影像感測元件封裝構件的剖面示意圖。如第2圖所示,影像感測元件封裝構件1a同樣包含有一影像感測晶粒10,其具有一主動面10a以及相對於主動面10a的一背面10b,且在主動面10a上設有一影像感測元件區域11以及外接墊12。
同樣的,影像感測元件封裝構件1a包含有一直通矽晶穿孔結構13,其貫穿影像感測晶粒10,並連通影像感測晶粒10的主動面10a與背面10b,用來曝露出位於影像感測晶粒10的主動面10a上部分的外接墊12。在影像感測晶粒10的背面10b以及矽晶穿孔結構13的側壁上則順應的形成有第一絕緣層14,例如,氧化矽、氮化矽或氮氧化矽等等。第一絕緣層14也可以採用有機高分子絕緣材料。
根據本發明之另一較佳實施例,在第一絕緣層14上形成有一第一重佈線路層15,例如,鋁金屬線路圖案或者銅金屬線路圖案。第一重佈線路層15順應的覆蓋在矽晶穿孔結構13的側壁上以及底部,並且與外接墊12電連接。此外,第一重佈線路層15至少包含有一連接墊15a以及一防電磁干擾金屬圖案15b。在第一重佈線路層15以及第一絕緣層14上另有一第二絕緣層16,例如,氧化矽、氮化矽或氮氧化矽等等。在第二絕緣層16設有至少一開孔16a,曝露出部分的連接墊15a。
在第二絕緣層16上形成有一第二重佈線路層17,例如,鈦、銅、鎳、金、鋁或上述金屬之組合。第二重佈線路層17填入開孔16a,並與曝露出的連接墊15a電連接。第二重佈線路層17至少包含有一焊接墊17a。在第二重佈線路層17以及第二絕緣層16上另有一防焊層18,例如,環氧樹脂、聚亞醯胺、光阻等等。在防焊層18設有至少一開孔18a,曝露出部分的焊接墊17a。在焊接墊17a上則設有焊接錫球19。此外,在防焊層18設有複數個假開孔(dummy openings)18b,其中,假開孔18b可以是圓形、矩形、長條形、鋸齒形或不規則形狀。
第2圖中的影像感測元件封裝構件1a與第1圖中的影像感測元件封裝構件1的差別在於:(1)第2圖中的影像感測元件封裝構件1a具有一防電磁干擾金屬圖案15b,可以保護影像感測晶粒10免受電磁干擾;以及(2)第2圖中的影像感測元件封裝構件1a在防焊層18設有複數個假開孔18b,可以釋放形成在影像感測晶粒10的背面10b上的絕緣層所產生的應力,也可以用來作為破裂停止(crack stop)機制。
請參閱第3圖,其為依據本發明又另一較佳實施例所繪示的影像感測元件封裝構件的剖面示意圖。如第3圖所示,同樣的,在第二重佈線路層17以及第二絕緣層16上設有一防焊層18,例如,環氧樹脂、聚亞醯胺、光阻等等。在防焊層18設有至少一開孔18a,曝露出部分的焊接墊17a。在焊接墊17a上則設有焊接錫球19。在防焊層18設有複數個假開孔18b,其中,假開孔18b可以填入絕緣材料,以釋放影像感測晶粒10的背面10b上的應力。
第4圖至第11圖例示製作如第1圖中的影像感測元件封裝構件1的方法。首先,如第4圖所示,提供一影像感測晶圓100,其具有一主動面100a以及相對於主動面100a的一背面100b,且在主動面100a上設有至少一影像感測元件區域11以及外接墊12。影像感測元件區域11可以是CMOS影像感測元件,但不限於此。
在影像感測晶圓100的主動面100a上另覆蓋一封裝用光學蓋板20,例如,透鏡等級玻璃或石英,而在封裝用光學蓋板20與影像感測晶圓100的主動面100a之間另設有支撐堰體結構22,例如,環氧樹脂、聚亞醯胺、光阻或防焊阻劑材料等等,如此使光學蓋板20、支撐堰體結構22與影像感測晶圓100的主動面100a之間構成一密閉的凹穴結構24,而影像感測元件區域11就是位於凹穴結構24內部。此外,支撐堰體結構22與影像感測晶圓100的主動面100a之間可以利用接合材料(圖未示)進行黏合。接著,將影像感測晶圓100的背面100b研磨掉一預定厚度。
如第5圖所示,在完成晶圓晶背研磨製程之後,接著利用微影及蝕刻製程,從影像感測晶圓100的背面100b蝕刻出直通矽晶穿孔(TSV)結構13,其貫穿影像感測晶圓100,並連通影像感測晶圓100的主動面100a與背面100b,用來曝露出位於主動面100a上部分的外接墊12。
如第6圖所示,在影像感測晶圓100的背面100b以及矽晶穿孔結構13的側壁上順應的形成一第一絕緣層14,例如,氧化矽、氮化矽或氮氧化矽等等。第一絕緣層14也可以採用有機高分子絕緣材料。然後再利用微影及蝕刻製程,在矽晶穿孔結構13的底部上的第一絕緣層14中形成一開口14a,曝露出部分的外接墊12。
如第7圖所示,接下來,在第一絕緣層14上形成一第一重佈線路層15,例如,鋁金屬線路圖案或者銅金屬線路圖案。第一重佈線路層15順應的覆蓋在矽晶穿孔結構13的側壁上以及底部,並且與外接墊12電連接。此外,第一重佈線路層15至少包含有一連接墊15a。
如第8圖所示,接著,在第一重佈線路層15以及第一絕緣層14上形成一第二絕緣層16,例如,氧化矽、氮化矽或氮氧化矽等等。第二絕緣層16也可以採用有機高分子絕緣材料。然後再利用微影及蝕刻製程,在第二絕緣層16形成至少一開孔16a,曝露出部分的連接墊15a。
如第9圖所示,接下來,在第二絕緣層16上形成一第二重佈線路層17,例如,鈦、銅、鎳、金、鋁或上述金屬之組合。第二重佈線路層17也可以是由可焊接金屬材料所構成者。第二重佈線路層17與第一重佈線路層15可以採用相同的導電材料或者不同的導電材料,也可以是不同的厚度。第二重佈線路層17填入開孔16a,並與曝露出的連接墊15a電連接。第二重佈線路層17至少包含有一焊接墊17a。
如第10圖及第11圖所示,在第二重佈線路層17以及第二絕緣層16上形成一防焊層18,例如,環氧樹脂、聚亞醯胺、光阻等等。然後在防焊層18中形成至少一開孔18a,曝露出部分的焊接墊17a。然後,在開孔18a內的焊接墊17a上形成一焊接錫球19。最後,進行晶圓切割製程,形成如第1圖中的影像感測元件封裝構件1。熟習該項技藝人士應能理解第4圖至第11圖中雙層的重佈線路層的製作方法僅為示意,本發明並不限於雙層的重佈線路層,熟習該項技藝人士更可以利用所揭露的方法步驟形成多層的重佈線路層。
本發明的主要技術特徵至少包括:(1)採晶圓級封裝製程結合直通矽晶穿孔技術,並在影像感測晶粒的背面形成多層重佈線路,故在設計上允許更多數量的輸出輸入(I/O)接點,以及具備更彈性的線路佈局與成本上優勢;(2)在第一重佈線路層中可以形成防電磁干擾金屬圖案,可以保護影像感測晶粒免受電磁干擾;以及(3)在防焊層可以設有複數個假開孔,用來釋放絕緣層所產生的應力,也可以用來作為破裂停止機制。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
1...影像感測元件封裝構件
1a...影像感測元件封裝構件
10...影像感測晶粒
10a...主動面
10b...背面
11...影像感測元件區域
12...外接墊
13...直通矽晶穿孔結構
14...第一絕緣層
15...第一重佈線路層
15a...連接墊
15b...防電磁干擾金屬圖案
16...第二絕緣層
16a...開孔
17...第二重佈線路層
17a...焊接墊
18...防焊層
18a...開孔
18b...假開孔
19...焊接錫球
20...封裝用光學蓋板
22...支撐堰體結構
24...凹穴結構
100...影像感測晶圓
100a...主動面
100b...背面
第1圖為依據本發明一較佳實施例所繪示的影像感測元件封裝構件的剖面示意圖。
第2圖為依據本發明另一較佳實施例所繪示的影像感測元件封裝構件的剖面示意圖。
第3圖為依據本發明又另一較佳實施例所繪示的影像感測元件封裝構件的剖面示意圖。
第4圖至第11圖例示本發明影像感測元件封裝構件的製作方法。
1...影像感測元件封裝構件
10...影像感測晶粒
10a...主動面
10b...背面
11...影像感測元件區域
12...外接墊
13...直通矽晶穿孔結構
14...第一絕緣層
15...第一重佈線路層
15a...連接墊
16...第二絕緣層
16a...開孔
17...第二重佈線路層
17a...焊接墊
18...防焊層
18a...開孔
19...焊接錫球
20...封裝用光學蓋板
22...支撐堰體結構
24...凹穴結構

Claims (18)

  1. 一種影像感測元件封裝構件,包含有:一影像感測晶粒,其具有一主動面以及相對於該主動面的一背面,且在該主動面上設有一影像感測元件區域以及一外接墊;一直通矽晶穿孔結構,貫穿該影像感測晶粒,連接該外接墊;複數層重佈線路,形成在該像感測晶粒的該背面上;以及一防焊層,覆蓋在該複數層重佈線路上,其中在該防焊層中設有複數個假開孔,用來釋放應力。
  2. 如申請專利範圍第1項所述之影像感測元件封裝構件,其中在該影像感測晶粒的該主動面上另覆蓋一封裝用光學蓋板。
  3. 如申請專利範圍第2項所述之影像感測元件封裝構件,其中在該封裝用光學蓋板與該影像感測晶粒的該主動面之間另設有一支撐堰體結構。
  4. 如申請專利範圍第3項所述之影像感測元件封裝構件,其中在該支撐堰體結構包含有環氧樹脂、聚亞醯胺、光阻或防焊阻劑。
  5. 如申請專利範圍第1項所述之影像感測元件封裝構件,其中在該防焊層中設有至少一開孔,曝露出一焊接墊,並在該焊接墊上設有一焊接錫球。
  6. 如申請專利範圍第1項所述之影像感測元件封裝構件,其中在該複數個假開孔內填入一絕緣材料。
  7. 如申請專利範圍第1項所述之影像感測元件封裝構件,其中該複數層重佈線路至少包含有一防電磁干擾金屬圖案。
  8. 一種影像感測元件封裝構件,包含有:一影像感測晶粒,其具有一主動面以及相對於該主動面的一背面,且在該主動面上設有一影像感測元件區域以及一外接墊;一直通矽晶穿孔結構,貫穿該影像感測晶粒,連接該外接墊;以及複數層重佈線路,形成在該像感測晶粒的該背面上,其中該複數層重佈線路至少包含有一防電磁干擾金屬圖案。
  9. 如申請專利範圍第8項所述之影像感測元件封裝構件,其中在該影像感測晶粒的該主動面上另覆蓋一封裝用光學蓋板。
  10. 如申請專利範圍第9項所述之影像感測元件封裝構件,其中在該封裝用光學蓋板與該影像感測晶粒的該主動面之間另設有一支撐堰體結構。
  11. 如申請專利範圍第10項所述之影像感測元件封裝構件,其中在 該支撐堰體結構包含有環氧樹脂、聚亞醯胺、光阻或防焊阻劑。
  12. 如申請專利範圍第8項所述之影像感測元件封裝構件,其中另包含有一防焊層,覆蓋在該複數層重佈線路上。
  13. 如申請專利範圍第12項所述之影像感測元件封裝構件,其中在該防焊層中設有至少一開孔,曝露出一焊接墊,並在該焊接墊上設有一焊接錫球。
  14. 一種影像感測元件封裝構件的製作方法,包含有:提供一晶圓,其具有至少一主動面及至少一背面,且在該主動面上設有至少一影像感測元件區域及一外接墊;於晶圓的該主動面上覆蓋一光學蓋板;從該晶圓的該背面蝕刻出至少一直通矽晶穿孔結構,其貫穿該晶圓,曝露出位於該主動面上部分的該外接墊;於該晶圓的該背面及該矽晶穿孔結構的側壁上順應的形成一第一絕緣層;於該矽晶穿孔結構內的該第一絕緣層中形成一開口,曝露出部分的該外接墊;於該第一絕緣層上形成一第一重佈線路層,且該第一重佈線路層與該外接墊電連接,其中該第一重佈線路層至少包含有一防電磁干擾金屬圖案;於該第一重佈線路層上形成一第二絕緣層; 於該第二絕緣層形成至少一第一開孔,曝露部分該第一重佈線路層;以及於該第二絕緣層上形成一第二重佈線路層,該第二重佈線路層經由該第一開孔與該第一重佈線路層電連接。
  15. 如申請專利範圍第14項所述之影像感測元件封裝構件的製作方法,其中形成一第二重佈線路層之後另包含以下步驟:於該第二重佈線路層上形成一防焊層;於該防焊層中形成至少一第二開孔,曝露出部分的該第二重佈線路層;以及於該第二開孔上形成一焊接錫球。
  16. 如申請專利範圍第15項所述之影像感測元件封裝構件的製作方法,其中形成該第二開孔的同時,於該防焊層中形成複數個假開孔。
  17. 如申請專利範圍第16項所述之影像感測元件封裝構件的製作方法,其中該複數個假開孔,係用來釋該第一、第二放絕緣層所產生的應力。
  18. 如申請專利範圍第16項所述之影像感測元件封裝構件的製作方法,其中在該複數個假開孔內填入一絕緣材料。
TW100109413A 2010-03-19 2011-03-18 影像感測元件封裝構件及其製作方法 TWI508273B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US31540510P 2010-03-19 2010-03-19

Publications (2)

Publication Number Publication Date
TW201143074A TW201143074A (en) 2011-12-01
TWI508273B true TWI508273B (zh) 2015-11-11

Family

ID=44602594

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100109413A TWI508273B (zh) 2010-03-19 2011-03-18 影像感測元件封裝構件及其製作方法

Country Status (3)

Country Link
US (1) US8536672B2 (zh)
CN (2) CN102194781B (zh)
TW (1) TWI508273B (zh)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8314498B2 (en) * 2010-09-10 2012-11-20 Aptina Imaging Corporation Isolated bond pad with conductive via interconnect
CN102544040B (zh) * 2012-01-17 2014-06-25 中国科学院上海微系统与信息技术研究所 利用TSV技术实现GaAs图像传感器的圆片级封装方法
TWI497645B (zh) * 2012-08-03 2015-08-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US9196642B2 (en) * 2012-09-10 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Stress release layout and associated methods and devices
KR102018885B1 (ko) 2012-12-20 2019-09-05 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
TWI560825B (en) * 2013-02-08 2016-12-01 Xintec Inc Chip scale package structure and manufacturing method thereof
US8937009B2 (en) 2013-04-25 2015-01-20 International Business Machines Corporation Far back end of the line metallization method and structures
JP6299406B2 (ja) * 2013-12-19 2018-03-28 ソニー株式会社 半導体装置、半導体装置の製造方法、及び電子機器
US9679936B2 (en) * 2014-02-27 2017-06-13 Semiconductor Components Industries, Llc Imaging systems with through-oxide via connections
CN103956334B (zh) * 2014-05-07 2016-06-01 华进半导体封装先导技术研发中心有限公司 集成电路中rdl和tsv金属层一次成型方法
TWI603447B (zh) * 2014-12-30 2017-10-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI591764B (zh) * 2015-01-12 2017-07-11 精材科技股份有限公司 晶片封裝體及其製造方法
KR20160090972A (ko) 2015-01-22 2016-08-02 에스케이하이닉스 주식회사 이미지 센서 패키지 및 제조 방법
MA41414A (fr) 2015-01-28 2017-12-05 Centre Nat Rech Scient Protéines de liaison agonistes d' icos
US10217783B2 (en) 2015-04-08 2019-02-26 Semiconductor Components Industries, Llc Methods for forming image sensors with integrated bond pad structures
US9818776B2 (en) 2015-04-08 2017-11-14 Semiconductor Components Industries, Llc Integrating bond pad structures with light shielding structures on an image sensor
CN109742064B (zh) * 2015-04-27 2021-06-11 精材科技股份有限公司 晶片封装体及其制造方法
TWI624039B (zh) * 2015-05-28 2018-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
US10043761B2 (en) * 2015-10-19 2018-08-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR102508551B1 (ko) * 2015-12-11 2023-03-13 에스케이하이닉스 주식회사 웨이퍼 레벨 패키지 및 제조 방법
US9837360B2 (en) * 2015-12-11 2017-12-05 SK Hynix Inc. Wafer level packages and electronics system including the same
US9941230B2 (en) * 2015-12-30 2018-04-10 International Business Machines Corporation Electrical connecting structure between a substrate and a semiconductor chip
CN105655320B (zh) * 2016-01-11 2019-08-02 华天科技(昆山)电子有限公司 低成本芯片背部硅通孔互连结构及其制备方法
US9773829B2 (en) * 2016-02-03 2017-09-26 Omnivision Technologies, Inc. Through-semiconductor-via capping layer as etch stop layer
US20170256496A1 (en) * 2016-03-01 2017-09-07 Xintec Inc. Chip package and method for forming the same
US10209466B2 (en) 2016-04-02 2019-02-19 Intel IP Corporation Integrated circuit packages including an optical redistribution layer
TWI672779B (zh) * 2016-12-28 2019-09-21 曦威科技股份有限公司 指紋辨識裝置、使用其之行動裝置以及指紋辨識裝置的製造方法
KR101973445B1 (ko) 2017-11-07 2019-04-29 삼성전기주식회사 팬-아웃 센서 패키지 및 카메라 모듈
KR102486561B1 (ko) 2017-12-06 2023-01-10 삼성전자주식회사 재배선의 형성 방법 및 이를 이용하는 반도체 소자의 제조 방법
AU2020279254A1 (en) 2019-05-21 2021-01-14 Illumina, Inc. Sensors having an active surface
KR20210047062A (ko) * 2019-10-21 2021-04-29 삼성전자주식회사 인터포저 및 그 제조방법
US12050398B2 (en) * 2020-05-19 2024-07-30 Micron Technology, Inc. Semiconductor device and method of forming the same
KR20220021238A (ko) * 2020-08-13 2022-02-22 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR20220102900A (ko) 2021-01-14 2022-07-21 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지
CN116779690A (zh) * 2023-06-20 2023-09-19 东莞链芯半导体科技有限公司 传感器的封装结构及封装方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200924175A (en) * 2007-11-20 2009-06-01 Advanced Semiconductor Eng Optical sensor chip package process and structure thereof
TW200935574A (en) * 2007-12-27 2009-08-16 Advanced Chip Eng Tech Inc Inter-connecting structure for semiconductor device package and method of the same
CN101587903A (zh) * 2008-05-23 2009-11-25 精材科技股份有限公司 电子元件封装体及其制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3465617B2 (ja) * 1999-02-15 2003-11-10 カシオ計算機株式会社 半導体装置
US6166444A (en) * 1999-06-21 2000-12-26 United Microelectronics Corp. Cascade-type chip module
KR100381046B1 (ko) * 2000-03-31 2003-04-18 엘지.필립스 엘시디 주식회사 더미부를 가지는 테이프 캐리어 패키지와 이를 이용한 액정표시장치
JP2007134735A (ja) * 2000-07-11 2007-05-31 Seiko Epson Corp 光素子及びその製造方法並びに電子機器
TW504817B (en) * 2001-11-20 2002-10-01 Taiwan Semiconductor Mfg Method and structure to improve mold resin adhesion
US7061106B2 (en) * 2004-04-28 2006-06-13 Advanced Chip Engineering Technology Inc. Structure of image sensor module and a method for manufacturing of wafer level package
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
US7566650B2 (en) * 2005-09-23 2009-07-28 Stats Chippac Ltd. Integrated circuit solder bumping system
TWI273683B (en) * 2005-11-02 2007-02-11 Siliconware Precision Industries Co Ltd Semiconductor package and substrate structure thereof
US7361972B2 (en) * 2006-03-20 2008-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Chip packaging structure for improving reliability
CN100423250C (zh) * 2006-10-17 2008-10-01 晶方半导体科技(苏州)有限公司 双层引线封装结构及其制造方法
US7935568B2 (en) * 2006-10-31 2011-05-03 Tessera Technologies Ireland Limited Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
CN101369591B (zh) * 2007-08-17 2010-07-07 精材科技股份有限公司 影像感测元件封装体及其制作方法
US8138426B2 (en) * 2007-11-05 2012-03-20 Panasonic Corporation Mounting structure
CN101355066B (zh) * 2008-05-26 2011-05-18 苏州晶方半导体科技股份有限公司 封装结构及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200924175A (en) * 2007-11-20 2009-06-01 Advanced Semiconductor Eng Optical sensor chip package process and structure thereof
TW200935574A (en) * 2007-12-27 2009-08-16 Advanced Chip Eng Tech Inc Inter-connecting structure for semiconductor device package and method of the same
CN101587903A (zh) * 2008-05-23 2009-11-25 精材科技股份有限公司 电子元件封装体及其制作方法

Also Published As

Publication number Publication date
US8536672B2 (en) 2013-09-17
TW201143074A (en) 2011-12-01
CN102194781B (zh) 2015-11-04
CN102194781A (zh) 2011-09-21
CN105047629A (zh) 2015-11-11
CN105047629B (zh) 2018-03-06
US20110227186A1 (en) 2011-09-22

Similar Documents

Publication Publication Date Title
TWI508273B (zh) 影像感測元件封裝構件及其製作方法
US11501978B2 (en) Semiconductor device and manufacturing method thereof
TWI736715B (zh) 半導體結構及其製作方法
US10096553B2 (en) Metal pad for laser marking
TWI616957B (zh) 晶圓級封裝及其製作方法
US9502335B2 (en) Package structure and method for fabricating the same
US8940581B2 (en) Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US10431549B2 (en) Semiconductor package and manufacturing method thereof
TWI550802B (zh) 晶片封裝體及其製造方法
US7663213B2 (en) Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same
TWI529892B (zh) 晶片封裝體及其製造方法
TW201721771A (zh) 整合式扇出封裝及製造方法
US10249585B2 (en) Stackable semiconductor package and manufacturing method thereof
TW201320266A (zh) 半導體封裝件及其製法
TW202308095A (zh) 半導體封裝
TWI739650B (zh) 具有近零接合線厚度之三維堆疊半導體總成
JP2021158336A (ja) パッケージシールドを含むパッケージエッジに対する新規wlcspの信頼性の向上
US20240222330A1 (en) Semiconductor package
US20240347434A1 (en) Package for semiconductor
KR102046857B1 (ko) 반도체 패키지
KR20150141384A (ko) 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US20140246774A1 (en) Semiconductor device having a buffer layer and method of manufacturing the same