TWI739650B - 具有近零接合線厚度之三維堆疊半導體總成 - Google Patents

具有近零接合線厚度之三維堆疊半導體總成 Download PDF

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TWI739650B
TWI739650B TW109138553A TW109138553A TWI739650B TW I739650 B TWI739650 B TW I739650B TW 109138553 A TW109138553 A TW 109138553A TW 109138553 A TW109138553 A TW 109138553A TW I739650 B TWI739650 B TW I739650B
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semiconductor device
metallization
assembly
device package
metallization structure
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TW109138553A
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TW202129857A (zh
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歐文 Ｒ 菲
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美商美光科技公司
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Abstract

本文中揭示半導體裝置封裝總成及相關聯方法。在一些實施例中，該半導體裝置封裝總成包含：(1)一基底組件，其具有一前側及與第一側相對之一背側，該基底組件具有在該前側處之一第一金屬化結構，該第一金屬化結構曝露於該前側處之一接觸區域中；(2)一半導體裝置封裝，其具有一第一側及一第二側，該半導體裝置封裝具有在該第一側處之一第二金屬化結構；及(3)一金屬凸塊，其至少部分定位於凹部中且電耦合至該第二金屬化結構及該第一金屬化結構。

Description

具有近零接合線厚度之三維堆疊半導體總成
本技術係關於其中具有可堆疊半導體封裝之半導體總成。更特定言之，本技術之一些實施例係關於藉由三維堆疊(3DS)程序製造之半導體總成。在此等實施例中，半導體封裝在具有可忽略的(例如，近零)接合線厚度(BLT)且未使用矽穿孔(TSV)之情況下彼此直接電耦合。
經封裝半導體晶粒(包含記憶體晶片、微處理器晶片、邏輯晶片及成像器晶片)通常包含安裝於一基板上且包封於一塑膠保護罩中之一半導體晶粒。個別半導體晶粒可包含功能構件(諸如記憶體胞元、處理器電路、成像器裝置及其他電路)，以及電連接至功能構件之接合墊。半導體製造商不斷減小晶粒封裝之大小以配合於電子裝置之空間約束內。用於增大一半導體封裝之處理能力之一種途徑係在一單一封裝中將多個半導體晶粒垂直地彼此上下堆疊。可藉由使用TSV (其等需要多個處理步驟(諸如光微影)來構造)來使此等垂直堆疊之封裝中之晶粒電互連。
下文描述經堆疊半導體晶粒封裝及製造此等晶粒封裝之方法之數項實施例之具體細節。術語「半導體裝置」通常指代包含一或多個半導體材料之一固態裝置。例如，一半導體裝置可包含一半導體基板或晶圓、或自一晶圓或基板單粒化之一晶粒。在本發明各處，半導體晶粒大體上在半導體裝置之內容背景中進行描述，但其不限於此。
術語「半導體裝置封裝」可指代具有併入至一共同封裝中之一或多個半導體裝置之一配置。一半導體封裝可包含部分或完全囊封至少一個半導體裝置之一外殼或罩殼。術語「半導體裝置封裝總成」可指代包含多個經堆疊半導體裝置封裝之一總成。如本文中所使用，術語「垂直」、「橫向」、「上」及「下」可指代鑑於圖中所展示之定向，半導體裝置或封裝中之構件之相對方向或位置。然而，此等術語應被解釋為包含具有其他定向(諸如倒置或傾斜定向)之半導體裝置。
圖1係根據本技術之一實施例之一半導體裝置封裝總成100之一示意性橫截面視圖。如所展示，半導體裝置封裝總成100包含一基底組件101及堆疊於基底組件101上之多個半導體裝置封裝103。儘管所繪示實施例展示十三個(13個)分離之經堆疊半導體裝置封裝103，然將瞭解，在其他實施例中，半導體裝置封裝總成100可包含任何適合數目個(例如，10個、12個、14個、16個、18個等)經堆疊半導體裝置封裝103。半導體裝置封裝總成100包含覆蓋基底組件101及半導體裝置封裝103之一囊封材料104。在一些實施例中，囊封材料104可包含樹脂、塑膠、矽、氧化物、聚合物或其他適合介電材料。
如圖1中所展示，半導體裝置封裝103經由一金屬化結構108電耦合至電耦合器106。在一些實施例中，電耦合器106可包含焊料凸塊、焊料球、導電墊及/或其他適合裝置。金屬化結構108可包含導電材料(諸如金屬(例如，銅))，該等導電材料組態成界定將半導體裝置封裝103電連接至電耦合器106之一電路之跡線、通孔、平面等。藉由此配置，基底組件101及半導體裝置封裝103可經由電耦合器106及金屬化結構108電耦合至一外部裝置。
半導體裝置封裝總成100具有一垂直緊湊設計。例如，基底組件101及多個半導體裝置封裝103直接堆疊在一起使得多個半導體裝置封裝103之間之一接合線厚度(BLT)可為零或近零。在一些實施例中，基底組件101與鄰近半導體裝置封裝103之間之BLT亦可為零或近零。
在一些實施例中，基底組件101可在其中包含一或多個半導體組件102 (例如，積體電路)。基底組件101可為一電路板或常用於半導體裝置封裝中之其他類型之基板，或基底組件可為一半導體裝置，諸如一邏輯裝置、記憶體裝置或處理器。如所展示，基底組件101具有一第一側1011 (例如，一前側/作用側)及與第一側1011相對之一第二側1013 (例如，一背側/非作用側)。
基底組件101可包含在基底組件101之第一側1011處之一鈍化層1015。在一些實施例中，鈍化層1015可包含氧化物層、一惰性層(例如，不太可能與空氣起化學反應或受腐蝕之一層)，或其他適合保護層。例如，鈍化層1015可包含一保護膜。鈍化層1015保護基底組件101。在一些實施例中，基底組件101可藉由電耦合器(諸如焊料凸塊或焊料球)進一步耦合至一中介層基板。
如所展示，基底組件101包含電耦合至基底組件101中之半導體組件102之一金屬化結構105。在所繪示實施例中，金屬化結構105可包含界定跡線、通孔及/或平面之一或多個金屬化層。在一些實施例中，金屬化層可包含鋁(例如，鋁墊)、銅或其他適合金屬或導電材料。
在所繪示實施例中，可在一後段製程(BEOL)製程期間形成金屬化結構105。金屬化結構105可包含一接觸區域107，接觸區域107經組態以在半導體裝置封裝103堆疊於基底基板101上時與最下半導體裝置封裝103 (例如，電氣地且實體地)接觸。
在圖1中所展示之所繪示實施例中，個別半導體裝置封裝103具有一第一側1031 (例如，一前側/作用側/正面側(face side))及與第一側1031相對之一第二側1033 (例如，一背側/非作用側)。如所展示，個別半導體裝置封裝103亦可包含在半導體裝置封裝103之第一側1031處之一鈍化層1035以保護半導體裝置封裝103。在一些實施例中，鈍化層1035可包含氧化物層、一惰性層(例如，不太可能與空氣起化學反應或受腐蝕之一層)，或其他適合保護層。鈍化層1035可替代地為一預形成保護膜。
如所展示，個別半導體裝置封裝103亦可包含在半導體裝置封裝103之第二側1033處之一介電層1037以保護半導體裝置封裝103。在一些實施例中，介電層1037可為一介電膜。
個別半導體裝置封裝103亦可包含電耦合至半導體裝置封裝103中之一或多個半導體組件1032 (例如，積體電路等)之一金屬化結構109。金屬化結構109可延伸穿過半導體裝置封裝103之厚度。金屬化結構109可包含鋁、銅或其他適合金屬或導電材料之層。金屬化結構109可在一BEOL製程期間形成，且包含跡線、通孔或其他電構件之多個層。金屬化結構109可具有在第一側1031處之一導電墊109a及在背側1033處之一接觸區109b。
如圖1中所展示，基底組件101及最下半導體裝置封裝103以一「面對面」方式堆疊，使得基底組件101之第一側1011 (例如，「正面」側)面向最下半導體裝置封裝103之第一側1031 (例如，「正面」側)。最下半導體裝置封裝103上之鈍化層1035可直接接觸基底組件101上之鈍化層1015，使得最下半導體裝置封裝103與基底組件101之間存在零BLT。然而，在一些實施例中，最下半導體裝置封裝103與基底組件101之間可存在一極小間隙，使得存在近零BLT。亦如圖1中所展示，額外半導體裝置封裝103以一「面對背」方式堆疊於最下半導體裝置封裝103上方。例如，一個半導體裝置封裝103之第二側1033 (「背」側)直接耦合至一鄰近半導體裝置封裝103之第一側1031 (「正面」側)。藉由此配置，可快速地堆疊基底組件101及半導體裝置封裝103。隨著更多半導體裝置封裝103彼此堆疊，半導體裝置封裝總成100可具有更高裝置密度。
半導體裝置封裝總成100進一步包含在最下半導體裝置封裝103之第一側1031處之金屬凸塊111 (或金屬柱)。金屬凸塊111電耦合至最下半導體裝置封裝103之金屬化結構109及基底組件101之金屬化結構105 (例如，在接觸區域107處)。金屬凸塊111可由銦或其他適合導電材料製成。在一些實施例中，金屬凸塊111可藉由一退火程序(諸如在一段時間內在攝氏100度至攝氏200度下加熱金屬凸塊111)電耦合至基底組件101之第一金屬化層105。
個別半導體裝置封裝103具有在其等第二側1033處之一凹部113 (例如，一「凹坑(divot)」或「溝槽」)，且金屬凸塊115 (或金屬柱)可定位於凹部113中。金屬凸塊115可電耦合至鄰近半導體裝置封裝103之金屬化結構109。藉由此配置，本技術使基底組件101能夠在未在基底組件101或半導體裝置封裝103之任一者中使用TSV之情況下電耦合至半導體裝置封裝103。在一些實施例中，金屬凸塊115可藉由一退火程序(諸如將金屬凸塊115加熱至約攝氏100度至攝氏300度(例如，200°C)達約50秒至200秒(例如，100秒))電耦合至半導體裝置封裝103。
在一些實施例中，半導體裝置封裝總成100可為一記憶體裝置，其中半導體裝置封裝103係記憶體晶粒(例如，DRAM、LPDRAM、SRAM、快閃記憶體等)。在一些實施例中，基底組件101可為一邏輯裝置、處理器、及/或另一記憶體裝置。
圖2A至圖2J係根據本技術之用於製造一半導體裝置封裝203 (例如，圖1中所描述之半導體裝置封裝103)之一方法之示意性橫截面視圖。在圖2A至圖2J各處，相同元件符號指代相同組件。參考圖2A，在方法之此階段，半導體裝置封裝203具有具一第一側2031 (例如，一前側/作用側)及與第一側2031相對之一第二側2033 (例如，一背側/非作用側)之一基板2037。半導體裝置封裝203可具有在一BEOL製程期間形成之一金屬化結構205，金屬化結構205包含在基板2037中之第一金屬化層205a、第二金屬化層205b及第三金屬化層205c。在一些實施例中，第一金屬化層205a可包含鋁或另一適合金屬或導電材料。例如，第一金屬化層205a可為鋁墊。第二金屬化層205b可包含銅或另一適合金屬或導電材料，且第三金屬化層205c可包含銅或另一適合金屬或導電材料。金屬化結構205電耦合至半導體裝置封裝203中之一或多個半導體組件202 (例如，積體電路)。
在一些實施例中，半導體裝置封裝203亦可具有在金屬化結構205之一部分與基板2037之間之一障壁層217。例如，障壁層217可鄰近於第二金屬化層205b。障壁層217可由一金屬(諸如钽)製成以防止擴散至基板2037中。例如，第二金屬化層205b可包含銅，且障壁層217可由钽製成以抑制銅擴散至基板2037中。
圖2A展示在一鈍化層2035已經施覆至半導體裝置封裝203之第一側2031以保護半導體裝置封裝203之後的半導體裝置封裝203。在一些實施例中，鈍化層2035可包含氧化物層、一惰性層(例如，不太可能與空氣起化學反應或受腐蝕之一層)、其他適合保護層，或一預形成保護膜。半導體裝置封裝203亦可包含在第一側2031處之第一金屬化層205a上之一接觸區域207。
圖2B展示在金屬凸塊211已形成於接觸區域207上之後的半導體裝置封裝203。金屬凸塊211電耦合至金屬化結構205且經組態以提供至堆疊於半導體裝置封裝203上之另一半導體裝置封裝(例如，參見圖1)之一金屬化結構的電及機械連接。金屬凸塊211可由銦或其他適合導電材料製成。
在一些實施例中，金屬凸塊211可具有大約10 μm至20 μm、或更明確言之大約15 μm之一垂直尺寸VD。可藉由一電鍍程序來形成金屬凸塊211，其中將一晶種材料沈積於第一金屬化層205a之接觸區域207上，且接著將一導電材料鍍覆至晶種材料上以在第一金屬化層205a上形成金屬凸塊211。替代地，可藉由一噴墨程序、冷退火或其他適合方法來形成金屬凸塊211。
圖2C展示在半導體裝置封裝203已經由一接合層213耦合至一載體215之後的半導體裝置封裝203。載體215經組態以在下文參考圖2D至圖2J描述之製程中暫時固持且支撐半導體裝置封裝203。載體215可為可重用的或一次性的，諸如一玻璃載體、矽載體或一塑膠載體。在一些實施例中，接合層213可為一釋離帶(例如，氣體敏感或溫度敏感)、可流動黏著劑或其他適合材料。可使用一流體(氣體或液體)來溶解接合層213或使用一雷射來燒蝕接合層213以自載體215釋離半導體裝置封裝203。
圖2D繪示在基板2037已經薄化之後的半導體裝置封裝203。參考圖2D，基板2037可薄化至介於一薄化表面219與第一側2031之間之一厚度D。在一些實施例中，基板2037之厚度D之範圍可從5 μm至30 μm，且例如不超過30 μm、25 μm、20 μm、15 μm、10 μm或5 μm。
藉由將基板2037薄化至此程度，可在未使用TSV之情況下接達半導體裝置封裝203之金屬化結構205且將其電耦合至經堆疊半導體裝置封裝之其他金屬化結構或半導體組件。一般而言，為在一半導體結構中形成一TSV，半導體基板之最小厚度可為約50 μm。此比本技術之半導體裝置封裝203及半導體裝置封裝103 (圖1)厚200%至1000%。因此，由本技術提供之經改良方法係有利的，至少因為其提供具有較小厚度(或垂直尺寸)且可在未形成TSV之情況下堆疊的半導體裝置封裝。其對於製造緊湊半導體裝置或封裝尤其有利。
圖2E繪示在一第一經圖案化光阻層221已形成於半導體裝置封裝203之第二側2033 (背側/非作用側)上之後的程序之一階段。如所展示，第一經圖案化光阻層221具有多個開口223a-c (圖2E中僅展示三個開口，第一開口223a、第二開口223b及第三開口223c)。如所展示，第一開口223a及第三開口223c在半導體裝置封裝203之相對側上。第一開口223a及第三開口223c可用於在程序之一稍後階段中分離或「單粒化」半導體裝置封裝203。第二開口223b與半導體裝置封裝203中之金屬化結構205之至少一部分對準。
圖2F展示在開口226已經由第一開口223a及第三開口223c經形成穿過基板2037以曝露鈍化層2035之後的程序之一階段。可藉由蝕刻半導體裝置封裝203之基板2037而形成開口226。在相同蝕刻程序中，可透過第二開口223b在基板2037中形成一凹部225 (例如，一凹坑或溝槽) (例如，第二開口223b在朝向半導體裝置封裝203之第一側2031之方向上延伸)。凹部225可為曝露障壁層217之另一開口。如所展示，凹部225具有傾斜側壁(在凹部225之左側及右側兩者處，如圖2F中所展示)，此可促成將另一半導體裝置封裝之一金屬凸塊耦合至金屬化結構205。替代地，可在未形成經圖案化光阻層221之情況下藉由雷射燒蝕基板2037而形成開口226及凹部225。
圖2G展示在第一光阻層221已經移除且一介電層227已形成於半導體裝置封裝203之第二側2033上之後的程序之一階段。可藉由一化學氣相沈積(CVD)程序來形成介電層227，諸如一CVD原矽酸四乙酯(TEOS)層。替代地，可藉由一旋塗程序來形成介電層227。
圖2H及圖2I展示在一第二經圖案化光阻層229 (或一第二光圖案(photo-pattern)遮罩)已形成於半導體裝置封裝203之第二側2033 (背側/非作用側)上之後的程序之階段。第二經圖案化光阻層229填充第一開口223a及第三開口223c，且具有與金屬結構205對準之一開口231。圖2I展示在開口231內之介電層227及障壁層217已經移除以透過一開口2133曝露第三金屬化層205c之後的程序之一階段。在一些實施例中，未移除障壁層217。考量是否移除障壁層217之因素包含例如障壁層217、第三金屬化層205c及金屬凸塊211中所使用之材料之類型。
圖2J展示在已移除第二光阻層229之後的程序之一階段。凹部225具有大於待附接至金屬結構205之一金屬凸塊211 (以虛線展示)之橫向尺寸L 2的一橫向尺寸L 1。因而，凹部225之一側壁225a及介電層227之一側壁部分227a與金屬凸塊211之一側壁211a隔開。在程序之此階段，可移除載體215且可將一或多個半導體裝置封裝203彼此堆疊。
圖3A至圖3I係繪示根據本技術之形成一半導體裝置封裝之一方法之示意性橫截面視圖。在圖3A至圖3I各處，相同元件符號指代相似組件。參考圖3A，一半導體裝置封裝300具有一第一側301 (例如，一前側/作用側)及與第一側301相對之一第二側303 (例如，一背側/非作用側)。半導體裝置封裝300可具有一基板307及在一BEOL製程期間形成之一金屬化結構305，金屬化結構305包含第一金屬化層305a、第二金屬化層305b及第三金屬化層305c。半導體裝置封裝300可具有耦合至金屬化結構305中之構件之導電通孔331。在圖3A至圖3I中所展示之所繪示實施例中，導電通孔331耦合至第二金屬化層305b。在其他實施例中，導電通孔331可耦合至其他金屬化層(例如，第一金屬化層305a或第三金屬化層305c)。金屬化層305a至305c可包含形成一或多個電路(例如，一帶電電路(live circuit)、一開路等)之導電跡線、墊、導電平面及/或電組件(例如，電容器、電阻器等)。
基板307可為由矽或其他適合材料形成之一半導體基板，且積體電路可形成於基板上/中以形成記憶體裝置、邏輯裝置或處理器。在所繪示實施例中，金屬化結構305電耦合至基板307中之一半導體組件302 (例如，積體電路)。第一金屬化層305a可包含鋁或其他適合金屬或導電材料，且形成為一或多個墊。在一些實施例中，第二金屬化層305b及第三金屬化層305c可包含銅或其他適合金屬或導電材料。
在一些實施例中，半導體裝置封裝300可具有在金屬化結構305之一部分與基板307之間之一障壁層(圖3A中未展示，類似於圖2A中所展示之障壁層217)。障壁層可替代地鄰近於第二金屬化層305b。在一些實施例中，障壁層可由一金屬(諸如钽)製成，且第二金屬化層305b可包含銅，使得鉭障壁層抑制銅擴散至基板307中。
半導體裝置封裝300亦可包含在半導體裝置封裝300之第一側301處之類似於圖2A中所展示之鈍化層2035的一鈍化層(未展示)。鈍化層可保護半導體裝置封裝300。在一些實施例中，鈍化層可包含氧化物層、一惰性層(例如，不太可能與空氣起化學反應或受腐蝕之一層)，或其他適合保護層或保護膜。
如圖3A中所展示，半導體裝置封裝300包含一中心金屬凸塊308a及在中心金屬凸塊308a之兩側處之側金屬凸塊308b (圖3A中展示四個側金屬凸塊308b)。如所展示，中心金屬凸塊308a具有大於側金屬凸塊308b之垂直尺寸的一垂直尺寸。例如，中心金屬凸塊308a可具有大約10 μm至20 μm之一垂直尺寸VDC，且側金屬凸塊308b可具有大約5 μm至10 μm之一垂直尺寸VDS。垂直尺寸VDC可為大約15 μm，而垂直尺寸VDS可為大約7.5 μm。中心金屬凸塊308a比側金屬凸塊308b高，使得在半導體裝置封裝300堆疊於另一半導體裝置封裝上時，中心金屬凸塊308a可定位於該半導體裝置封裝之一腔中，如下文關於圖3G及圖3H描述。
中心金屬凸塊308a及側金屬凸塊308b電耦合至金屬化結構305且經組態以與另一半導體裝置封裝之一金屬化層電接觸(例如，參見圖3H)。在一些實施例中，金屬凸塊308a、308b可包含銦凸塊。在其他實施例中，金屬凸塊308a、308b可包含其他適合導電材料。
在一些實施例中，中心金屬凸塊308a及側金屬凸塊308b可為藉由一電鍍程序形成之柱。例如，可藉由具有鄰近於第一金屬化層305a之一晶種材料而形成金屬凸塊308a、308b，且可將導電材料鍍覆至晶種材料上。在其他實施例中，可藉由一噴墨程序或其他適合方法來形成金屬凸塊308a、308b。在一些實施例中，金屬凸塊308a、308b可經冷退火(例如，在200°C下)。
圖3B展示在半導體裝置封裝300已經倒置且經由一黏著劑316耦合至一載體315之後的半導體裝置封裝300。載體315經組態以在下文關於圖3C至圖3H描述之製程中固持且支撐半導體裝置封裝300。載體315可為由玻璃、矽或塑膠製成之一可重用載體或一不可重用載體。將金屬凸塊308a及308b嵌入於黏著劑316中，黏著劑316可為樹脂或其他適合材料之一部分固化層。
圖3C繪示在基板307已經薄化之後的半導體裝置封裝300。參考圖3C，半導體裝置封裝300可經薄化使得一薄化表面319與半導體裝置封裝203之第一側2031之間之一深度H 1係大約10 μm。深度H 1之範圍可從5 μm至30 μm，且更明確言之，深度H 1不超過30 μm、25 μm、20 μm、15 μm、10 μm或5 μm。
藉由將基板307薄化至此程度，可在未使用一TSV之情況下接達金屬化結構305且將其電耦合至另一半導體裝置封裝之其他金屬化層或半導體組件。一般而言，為在一半導體結構中形成一TSV，半導體結構可被薄化之半導體結構之最小深度係約50 μm。因此，由本技術提供之經改良方法係有利的，至少部分因為其可製造且堆疊具有較小深度(或垂直尺寸)之半導體裝置封裝且無需形成TSV之處理步驟。其對於製造緊湊半導體裝置或封裝尤其有利。
圖3C亦展示在一塗佈層333已形成於薄化表面319上之後的半導體封裝300。塗佈層可為在後續處理(諸如下文關於圖3D及圖3E論述之光微影及其他程序)中保護薄化基板307的氧化物層。
圖3D繪示在一經圖案化光阻層321 (或一光圖案遮罩)已形成於半導體裝置封裝300之第二側303 (背側/非作用側)上之後的半導體封裝300。如所展示，光阻層321具有多個開口323a-c (識別為第一開口323a、第二開口323b及第三開口323c)。第一開口323a及第三開口323c形成於半導體裝置封裝300之相對側上，且可稍後在程序中用於分離或「單粒化」半導體裝置封裝300。第二開口323b在中線處，且更特定言之其可與中心金屬凸塊308a對準。
圖3E展示在通道326a、326c已經由第一開口323a及第三開口323c經形成穿過半導體裝置封裝300之後的半導體裝置封裝300。可藉由透過開口323a、323c蝕刻基板307而形成通道326a、326c。
在與形成通道326a、326c相同之程序中，可經由第二開口323b形成穿過基板307及金屬化結構305之一部分的一腔326b。腔326b可延伸至第二金屬化層305b且藉此曝露第二金屬化層305b之一部分。
圖3F展示在光阻層321及塗佈層333已經移除且一介電層327已形成於半導體裝置封裝300之第二側303上之後的半導體裝置封裝300。在一些實施例中，可藉由一化學氣相沈積(CVD)程序來形成介電層327，諸如一CVD原矽酸四乙酯(TEOS)層。替代地，可藉由一旋塗程序或施覆一預形成介電膜而形成介電層327。在一些實施例中，亦可移除基板307之一部分以進一步薄化基板。在此等實施例中，如圖3F中所指示之深度H 2可小於深度H 1。
圖3G展示在已移除通道326a及326c之底部及腔326b之底部處之介電層327之部分之後的半導體裝置封裝300。在一些實施例中，可藉由一蝕刻程序來移除介電層327之部分。如圖3G中所展示，在移除腔326b內之介電層327之部分之後，第二金屬化層305b之一部分曝露於腔326b中。
圖3H展示在連接位點350 (圖3H中展示四個連接位點350)已形成於半導體裝置封裝300之第二側303上之後的半導體裝置封裝300。連接位點350與側金屬凸塊308b對準，且經組態以依一堆疊配置耦合至另一半導體裝置封裝之側金屬凸塊(類似於上文所論述之側金屬凸塊308b)且與該等側金屬凸塊接觸。在一些實施例中，可藉由一遮蔽/蝕刻程序來形成多個連接位點350。多個連接位點350可由一金屬(諸如鋁、鈦、銅等)製成。
圖3I展示在載體315已經移除且相同組態之另一半導體裝置封裝300a堆疊於半導體裝置封裝300上之後的半導體裝置封裝300。如所展示，半導體封裝300a之中心金屬凸塊308a經對準且定位於半導體裝置封裝300之腔326b中，且電耦合至半導體裝置封裝300之第二金屬化層305b。半導體裝置封裝300a之側金屬凸塊308b分別與半導體裝置封裝300之對應連接位點350對準且電耦合至該等對應連接位點350。以此方式，數個半導體裝置封裝300可以零或近零BLT且在未形成穿過基板307之TSV之情況下彼此堆疊。
圖4A至圖4D繪示處理與關於圖1所描述之半導體裝置封裝總成100類似或相同之半導體裝置封裝總成401之方法，但半導體裝置封裝亦可用於晶粒堆疊中。半導體裝置封裝總成401之各者具有一正面側4011及一背側4013。在圖4A中，藉由一暫時載體403承載半導體裝置封裝總成401。多個半導體裝置封裝總成401之各者包含在背側4013處之一基底基板(例如，圖1中之基底組件101)及在正面側4011處之多個半導體裝置封裝(例如，半導體裝置封裝103或203)。在所繪示實施例中，半導體裝置封裝總成401之背側4013耦合至暫時載體403，使得裝置封裝總成401彼此隔開。
圖4B展示在已藉由一囊封材料405覆蓋半導體裝置封裝總成401之後的總成。在一些實施例中，囊封材料405可包含樹脂、塑膠、矽、氧化物、聚合物或其他適合介電材料。
圖4C展示在已自半導體裝置封裝總成401卸離暫時載體403之後的總成。在圖4C中，與圖4B相比，半導體裝置封裝總成401倒置。可移除圖4C中所展示之總成之一上部(例如，在如所指示之平面P上方之部分)使得可曝露半導體裝置封裝總成401之金屬化結構4018。
圖4D展示在聚合物層407已形成於半導體裝置封裝總成401上之後的總成。方法可包含使用聚合物層407來形成一重佈結構409。重佈結構409電耦合至個別半導體裝置封裝總成401中之金屬化層4018。在一些實施例中，重佈結構409可包含銅或其他適合導電材料。
如圖4D中所展示，多個連接器411可形成於重佈結構409上且電耦合至重佈結構409。連接器411進一步電耦合至半導體裝置封裝之金屬化結構及個別半導體裝置封裝總成401中之基底組件。在一些實施例中，連接器411可為球柵陣列(BGA)，包含一焊料球、一墊或其他適合連接裝置。接著，可藉由在由圖4D中所展示之虛線指示之位置處切穿囊封材料405而「單粒化」或分離半導體裝置封裝總成401。
圖5A至圖5D繪示根據本技術之處理半導體裝置封裝總成501之方法。在圖5A中，藉由一暫時載體503承載半導體裝置封裝總成501，且半導體裝置封裝總成501之各者具有一正面側5011及一背側5013。在此實施例中，半導體裝置封裝總成501之正面側5011耦合至暫時載體503，與圖4A及圖4B中之背側5013相反。半導體裝置封裝總成501經隔開使得其等稍後可在一單粒化程序期間分離。
圖5B展示在已藉由一囊封材料505覆蓋半導體裝置封裝總成501之後的總成。在一些實施例中，囊封材料505可包含樹脂、塑膠、矽、氧化物、聚合物或其他適合介電材料。
圖5C展示在已自半導體裝置封裝總成501卸離暫時載體503之後的總成。在圖5C中，與圖5B相比，藉由囊封材料505覆蓋之半導體裝置封裝總成501倒置。
圖5D展示在聚合物層507已形成於半導體裝置封裝總成501上之後的總成。方法可包含使用聚合物結構507來形成一重佈結構509。重佈結構509電耦合至個別半導體裝置封裝總成501中之金屬化層(例如，金屬化結構105或205)。在一些實施例中，重佈結構509可包含銅或其他適合導電材料。
如圖5D中所展示，多個連接器511可形成於重佈結構509上且電耦合至重佈結構509。連接器511進一步電耦合至半導體裝置封裝之金屬化結構及個別半導體裝置封裝總成501中之基底組件。在一些實施例中，連接器511可為BGA連接器，其包含一焊料球、一墊或其他適合連接裝置。接著，可藉由在由圖5D中所展示之虛線指示之位置處切穿囊封材料505而「單粒化」或分離半導體裝置封裝總成501。
具有上文關於圖1至圖5D所描述之特徵之半導體裝置之任一者可併入至大量更大及/或更複雜系統之任何者中，該等系統之一代表性實例係圖6中示意性地展示之一系統600。系統600可包含一處理器601、一記憶體603 (例如，SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置605及/或其他子系統或組件607。上文關於圖1至圖5D所描述之半導體總成、裝置及裝置封裝可包含於圖6中所展示之元件之任何者中。結果系統600可經組態以執行各種各樣的適合運算、處理、儲存、感測、成像及/或其他功能之任何者。因此，系統600之代表性實例包含(而不限於)電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路設備、手持式裝置(例如，掌上型電腦、可穿戴電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等)、平板電腦、多處理器系統、基於處理器之或可程式化消費性電子器件、網路電腦及微型電腦。系統600之額外代表性實例包含燈、相機、車輛等。關於此等及其他實例，系統600可容置於一單一單元中或分佈於多個互連單元上(例如，透過一通信網路)。因此，系統600之組件可包含本端及/或遠端記憶體儲存裝置及各種各樣的適合電腦可讀媒體之任何者。
本發明不意欲為詳盡的或將本技術限制於本文中所揭示之精確形式。儘管本文中出於闡釋性目的揭示特定實施例，然各種等效修改在未偏離本技術之情況下係可行的，如相關技術之一般技術者將認知。在一些情況中，尚未詳細展示或描述眾所周知的結構及功能以避免不必要地使本技術之實施例之描述不清楚。儘管本文中可依一特定順序呈現方法之步驟，然替代實施例可依一不同順序執行步驟。類似地，可在其他實施例中組合或消除在特定實施例之內容背景中揭示之本技術之某些態樣。此外，雖然可已在本技術之某些實施例之內容背景中揭示與該等實施例相關聯之優點，但其他實施例亦可展現此等優點，且並非全部實施例皆需必然展現此等優點或本文中所揭示之其他優點以落在本技術之範疇內。因此，本發明及相關聯技術可涵蓋本文中未明確展示或描述之其他實施例。
在本發明各處，單數術語「一」、「一個」及「該」包含複數指涉物，除非上下文另有明確指示。類似地，關於兩個或更多個品項之一清單，除非字詞「或」明確限於僅意謂排除其他品項之一單一品項，否則「或」在此一清單中之使用應解釋為包含(a)清單中之任何單一品項、(b)清單中之全部品項、或(c)清單中之品項之任何組合。另外，術語「包括」在各處用於意謂至少包含(若干)所述特徵，使得不排除任何較大數目個相同特徵及/或額外類型之其他特徵。本文中對「一項實施例」、「一些實施例」或類似表述之引用意謂接合實施例描述之一特定特徵、結構、操作或特性可包含於本技術之至少一項實施例中。因此，此等片語或表述出現在本文中不一定皆指代相同實施例。此外，可在一或多項實施例中以任何適合方式組合各種特定特徵、結構、操作或特性。
自前文，將瞭解，本文中已出於繪示之目的描述本技術之特定實施例，但可作出各種修改而不偏離本發明之範疇。本技術除如藉由隨附發明申請專利範圍限制外並不受限。
100:半導體裝置封裝總成 101:基底組件 102:半導體組件 103:半導體裝置封裝 104:囊封材料 105:金屬化結構 106:電耦合器 107:接觸區域 108:金屬化結構 109:金屬化結構 109a:導電墊 109b:接觸區 111:金屬凸塊 113:凹部 115:金屬凸塊 1011:第一側 1013:第二側 1015:鈍化層 1031:第一側 1032:半導體組件 1033:第二側/背側 1035:鈍化層 1037:介電層 202:半導體組件 203:半導體裝置封裝 205:金屬化結構/金屬結構 205a:第一金屬化層 205b:第二金屬化層 205c:第三金屬化層 207:接觸區域 211:金屬凸塊 211a:側壁 213:接合層 215:載體 217:障壁層 219:薄化表面 221:第一經圖案化光阻層/第一光阻層 223a:第一開口 223b:第二開口 223c:第三開口 225:凹部 225a:側壁 226:開口 227:介電層 227a:側壁部分 229:第二經圖案化光阻層/第二光阻層 231:開口 2031:第一側 2033:第二側 2035:鈍化層 2037:基板 2133:開口 300:半導體裝置封裝/半導體封裝 300a:半導體裝置封裝/半導體封裝 301:第一側 302:半導體組件 303:第二側 305:金屬化結構 305a:第一金屬化層 305b:第二金屬化層 305c:第三金屬化層 307:基板 308a:中心金屬凸塊 308b:側金屬凸塊 315:載體 316:黏著劑 319:薄化表面 321:經圖案化光阻層 323a:第一開口 323b:第二開口 323c:第三開口 326a:通道 326b:腔 326c:通道 327:介電層 331:導電通孔 333:塗佈層 350:連接位點 401:半導體裝置封裝總成 403:暫時載體 405:囊封材料 407:聚合物層 409:重佈結構 411:連接器 4011:正面側 4013:背側 4018:金屬化結構/金屬化層 501:半導體裝置封裝總成 503:暫時載體 505:囊封材料 507:聚合物層/聚合物結構 509:重佈結構 511:連接器 5011:正面側 5013:背側 600:系統 601:處理器 603:記憶體 605:輸入/輸出裝置 607:其他子系統或組件 D:厚度 H 1:深度 H 2:深度 L 1:橫向尺寸 L 2:橫向尺寸 P:平面 VD:垂直尺寸 VDC:垂直尺寸 VDS:垂直尺寸
參考以下圖式可更佳地理解本技術之許多態樣。圖式中之組件不一定按比例。代替性地，重點在於繪示本技術之原理。
圖1係根據本技術之一半導體裝置封裝總成之一示意性橫截面視圖。
圖2A至圖2J係繪示根據本技術之形成一半導體裝置封裝之一方法之示意性橫截面視圖。
圖3A至圖3I係繪示根據本技術之形成一半導體裝置封裝之一方法之示意性橫截面視圖。
圖4A至圖4D係繪示根據本技術之處理多個半導體裝置封裝總成之一方法之示意性橫截面視圖。
圖5A至圖5D係繪示根據本技術之處理多個半導體裝置封裝總成之一方法之示意性橫截面視圖。
圖6係繪示根據本技術之併有一半導體總成之一系統之一方塊圖。
100:半導體裝置封裝總成 101:基底組件 102:半導體組件 103:半導體裝置封裝 104:囊封材料 105:金屬化結構 106:電耦合器 107:接觸區域 108:金屬化結構 109:金屬化結構 109a:導電墊 109b:接觸區 111:金屬凸塊 113:凹部 115:金屬凸塊 1011:第一側 1013:第二側 1015:鈍化層 1031:第一側 1032:半導體組件 1033:第二側/背側 1035:鈍化層 1037:介電層

Claims (27)

  1. 一種半導體裝置封裝總成，其包括： 一基底組件，其具有一前側及一背側，該基底組件具有在該前側處之一第一金屬化結構，且該第一金屬化結構曝露於該前側處之一接觸區域中； 一半導體裝置晶粒堆疊，各半導體裝置晶粒具有一第一側、具有一凹部之一第二側、及一第二金屬化結構，該第二金屬化結構具有在該第一側處之一接觸墊及曝露於該第二側處之該凹部中之一接觸區；及 金屬凸塊，其等至少部分定位於該半導體裝置晶粒之該等第二側處之該等凹部中，其中該等金屬凸塊電耦合至一個半導體裝置總成之一第二金屬化結構之該等接觸墊及一鄰近半導體裝置總成之一接觸區，且其中額外金屬凸塊耦合至該半導體裝置晶粒之一最下半導體裝置晶粒之該接觸墊及該基底組件之該第一金屬化結構； 其中該半導體裝置封裝在無矽穿孔之情況下經由該第一金屬化結構及該第二金屬化結構彼此電耦合且電耦合至該基底組件。
  2. 如請求項1之半導體裝置封裝總成，其中該等金屬凸塊跨不超過20 μm之一距離自一個半導體裝置之該接觸墊延伸至一鄰近半導體裝置之該接觸區。
  3. 如請求項1之半導體裝置封裝總成，其中該金屬凸塊係一中心金屬凸塊，且其中該半導體裝置封裝總成進一步包括定位於該中心金屬凸塊之一個側處之一側金屬凸塊。
  4. 如請求項1之半導體裝置封裝總成，其中該等金屬凸塊之一垂直尺寸不超過15 μm。
  5. 如請求項1之半導體裝置封裝總成，其中該等金屬凸塊之一垂直尺寸係約10 μm。
  6. 如請求項1之半導體裝置封裝總成，其中該第一金屬化結構及該第二金屬化結構具有跡線及通孔而未使用自該半導體裝置堆疊晶粒之該第一側直接延伸至該第二側之一矽穿孔(TSV)。
  7. 如請求項1之半導體裝置封裝總成，其中該第一金屬化結構及該第二金屬化結構之至少一者包含鋁。
  8. 如請求項1之半導體裝置封裝總成，其中該第一金屬化結構及該第二金屬化結構之至少一者包含銅。
  9. 如請求項1之半導體裝置封裝總成，其中該第二金屬化結構包含第一金屬化層、第二金屬化層及第三金屬化層，且其中該第一金屬化層電耦合至該金屬凸塊。
  10. 如請求項9之半導體裝置封裝總成，其中該第一金屬化層包含鋁，且其中該第二金屬化層包含銅，且其中該第三金屬化層包含銅。
  11. 一種半導體裝置堆疊晶粒總成，其包括： 一第一半導體裝置晶粒，其具有一前側及一背側，該第一半導體裝置晶粒具有在該前側處之一第一金屬化結構及在該背側處之一第一基板，該第一金屬化結構經由一腔自該背側曝露； 一第二半導體裝置晶粒，其具有一第一側及一第二側，該第二半導體裝置晶粒具有在該第一側處之一第二金屬化結構及在該第二側處之一第二基板；及 一金屬柱，其至少部分定位於該腔中且電耦合至該第二金屬化結構及該第一金屬化結構。
  12. 如請求項11之半導體裝置堆疊晶粒總成，其中該金屬柱包含銦。
  13. 如請求項11之半導體裝置堆疊晶粒總成，其中該金屬柱係一中心金屬柱，且其中該半導體裝置堆疊晶粒總成進一步包括定位於該中心金屬柱之一個側處之一側金屬柱。
  14. 如請求項11之半導體裝置堆疊晶粒總成，其中該中心柱之一垂直尺寸不超過20 μm。
  15. 如請求項11之半導體裝置堆疊晶粒總成，其中該中心柱之一垂直尺寸係約10 μm。
  16. 如請求項11之半導體裝置堆疊晶粒總成，其中該第一金屬化結構及該第二金屬化結構在未使用一TSV之情況下電耦合。
  17. 如請求項11之半導體裝置堆疊晶粒總成，其中該第一金屬化結構及該第二金屬化結構之至少一者包含鋁。
  18. 如請求項11之半導體裝置堆疊晶粒總成，其中該第一金屬化結構及該第二金屬化結構之至少一者包含銅。
  19. 如請求項11之半導體裝置堆疊晶粒總成，其中該第二金屬化結構包含第一金屬化層、第二金屬化層及第三金屬化層，且其中該第一金屬化層電耦合至該金屬柱。
  20. 如請求項19之半導體裝置堆疊晶粒總成，其中該第一金屬化層包含鋁，且其中該第二金屬化層包含銅，且其中該第三金屬化層包含銅。
  21. 如請求項11之半導體裝置堆疊晶粒總成，其中該第一金屬化結構包含第一金屬化層、第二金屬化層及第三金屬化層，且其中該第三金屬化層電耦合至該金屬柱。
  22. 如請求項21之半導體裝置堆疊晶粒總成，其中該第一金屬化層包含鋁，且其中該第二金屬化層包含銅，且其中該第三金屬化層包含銅。
  23. 一種半導體裝置堆疊晶粒總成，其包括： 一第一半導體裝置晶粒，其具有一前側及一背側，該半導體裝置晶粒具有在該前側處之一第一金屬化結構，該第一金屬化結構經由一第一凹部自該背側曝露； 一第二半導體裝置晶粒，其具有一第一側及一第二側，該半導體裝置晶粒具有在該第一側處之一第二金屬化結構，該第二金屬化結構經由一第二凹部自該第二側曝露，該第二凹部與該第一凹部對準；及 一金屬凸塊，其至少部分定位於該第一凹部中且電耦合至該第二金屬化結構及該第一金屬化結構，其中該第一半導體裝置晶粒直接堆疊於該第二半導體裝置晶粒上，且該第一半導體裝置晶粒及該第二半導體裝置晶粒在無矽穿孔之情況下彼此電耦合。
  24. 如請求項23之半導體裝置堆疊晶粒總成，其中該金屬凸塊包含銦。
  25. 如請求項23之半導體裝置堆疊晶粒總成，其中該金屬凸塊係一中心金屬凸塊，且其中該半導體裝置堆疊晶粒總成進一步包括定位於該中心金屬凸塊之一個側處之一側金屬凸塊。
  26. 如請求項23之半導體裝置堆疊晶粒總成，其中該垂直尺寸不超過15 μm。
  27. 如請求項23之半導體裝置堆疊晶粒總成，其中該垂直尺寸係約10 μm。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018004930A1 (en) * 2016-06-30 2018-01-04 Intel Corporation Integrated circuit package assemblies including a chip recess
WO2018125213A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Recessed semiconductor die in a die stack to accommodate a component

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5199163A (en) * 1992-06-01 1993-04-06 International Business Machines Corporation Metal transfer layers for parallel processing
US5432999A (en) 1992-08-20 1995-07-18 Capps; David F. Integrated circuit lamination process
JP2003318178A (ja) * 2002-04-24 2003-11-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US20080237881A1 (en) * 2007-03-30 2008-10-02 Tony Dambrauskas Recessed solder socket in a semiconductor substrate
JP4937842B2 (ja) * 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2009181981A (ja) * 2008-01-29 2009-08-13 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US8202797B2 (en) * 2010-06-22 2012-06-19 Stats Chippac Ltd. Integrated circuit system with recessed through silicon via pads and method of manufacture thereof
KR102222485B1 (ko) * 2014-09-18 2021-03-04 에스케이하이닉스 주식회사 관통 전극을 갖는 반도체 소자, 이를 구비하는 반도체 패키지 및 반도체 소자의 제조방법
US10630296B2 (en) * 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10892250B2 (en) * 2018-12-21 2021-01-12 Powertech Technology Inc. Stacked package structure with encapsulation and redistribution layer and fabricating method thereof
US11309285B2 (en) * 2019-06-13 2022-04-19 Micron Technology, Inc. Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018004930A1 (en) * 2016-06-30 2018-01-04 Intel Corporation Integrated circuit package assemblies including a chip recess
US10186499B2 (en) * 2016-06-30 2019-01-22 Intel IP Corporation Integrated circuit package assemblies including a chip recess
WO2018125213A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Recessed semiconductor die in a die stack to accommodate a component
TW201841314A (zh) * 2016-12-30 2018-11-16 美商英特爾股份有限公司 在晶粒堆疊中用以容納組件之凹入的半導體晶粒

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