CN114902406A - 具有近零接合线厚度的三维堆叠半导体组合件 - Google Patents

具有近零接合线厚度的三维堆叠半导体组合件 Download PDF

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CN114902406A
CN114902406A CN202080091520.1A CN202080091520A CN114902406A CN 114902406 A CN114902406 A CN 114902406A CN 202080091520 A CN202080091520 A CN 202080091520A CN 114902406 A CN114902406 A CN 114902406A
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semiconductor device
metallization
metallization structure
device package
assembly
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CN202080091520.1A
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O·R·费伊
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本文中公开半导体装置封装组合件及相关联方法。在一些实施例中，所述半导体装置封装组合件包含：(1)基底组件，其具有前侧及与第一侧相对的背侧，所述基底组件具有在所述前侧处的第一金属化结构，所述第一金属化结构暴露于所述前侧处的接触区域中；(2)半导体装置封装，其具有第一侧及第二侧，所述半导体装置封装具有在所述第一侧处的第二金属化结构；及(3)金属凸块，其至少部分定位于凹部中且电耦合到所述第二金属化结构及所述第一金属化结构。

Description

具有近零接合线厚度的三维堆叠半导体组合件
技术领域
本技术涉及其中具有可堆叠半导体封装的半导体组合件。更特定来说，本技术的一些实施例涉及由三维堆叠(3DS)工艺制造的半导体组合件。在此类实施例中，半导体封装在具有可忽略的(例如，近零)接合线厚度(BLT)且未使用穿硅通路(TSV)的情况下彼此直接电耦合。
背景技术
经封装半导体裸片(包含存储器芯片、微处理器芯片、逻辑芯片及成像器芯片)通常包含安装于衬底上且包封于塑料保护罩中的半导体裸片。个别半导体裸片可包含功能特征(例如存储器单元、处理器电路、成像器装置及其它电路系统)，以及电连接到功能特征的接合垫。半导体制造商不断减小裸片封装的大小以配合于电子装置的空间约束内。用于增大半导体封装的处理能力的一种途径是在单个封装中将多个半导体裸片垂直地彼此上下堆叠。可通过使用TSV(其需要多个处理步骤(例如光刻)来构造)来使此类垂直堆叠的封装中的裸片电互连。
附图说明
参考以下图式可更好地理解本技术的许多方面。图式中的组件不一定按比例。代替性地，重点在于说明本技术的原理。
图1是根据本技术的半导体装置封装组合件的示意性横截面视图。
图2A到2J是说明根据本技术的形成半导体装置封装的方法的示意性横截面视图。
图3A到3I是说明根据本技术的形成半导体装置封装的方法的示意性横截面视图。
图4A到4D是说明根据本技术的处理多个半导体装置封装组合件的方法的示意性横截面视图。
图5A到5D是说明根据本技术的处理多个半导体装置封装组合件的方法的示意性横截面视图。
图6是说明根据本技术的并有半导体组合件的系统的框图。
具体实施方式
下文描述经堆叠半导体裸片封装及制造此类裸片封装的方法的数个实施例的具体细节。术语“半导体装置”通常是指包含一或多个半导体材料的固态装置。例如，半导体装置可包含半导体衬底或晶片、或从晶片或衬底单粒化的裸片。在本公开各处，半导体裸片大体上在半导体装置的上下文中进行描述，但其不限于此。
术语“半导体装置封装”可指具有并入到共同封装中的一或多个半导体装置的布置。半导体封装可包含部分或完全囊封至少一个半导体装置的外壳或罩壳。术语“半导体装置封装组合件”可指包含多个经堆叠半导体装置封装的组合件。如本文中所使用，术语“垂直”、“横向”、“上”及“下”可指鉴于图中所展示的定向，半导体装置或封装中的特征的相对方向或位置。然而，这些术语应被解释为包含具有其它定向(例如倒置或倾斜定向)的半导体装置。
图1是根据本技术的实施例的半导体装置封装组合件100的示意性横截面视图。如所展示，半导体装置封装组合件100包含基底组件101及堆叠于基底组件101上的多个半导体装置封装103。尽管所说明实施例展示十三个(13个)分离的经堆叠半导体装置封装103，但将了解，在其它实施例中，半导体装置封装组合件100可包含任何适合数目个(例如，10个、12个、14个、16个、18个等)经堆叠半导体装置封装103。半导体装置封装组合件100包含覆盖基底组件101及半导体装置封装103的囊封材料104。在一些实施例中，囊封材料104可包含树脂、塑料、硅、氧化物、聚合物或其它适合电介质材料。
如图1中所展示，半导体装置封装103经由金属化结构108电耦合到电耦合器106。在一些实施例中，电耦合器106可包含焊料凸块、焊料球、导电垫及/或其它适合装置。金属化结构108可包含导电材料(例如金属(例如，铜))，所述导电材料配置成界定将半导体装置封装103电连接到电耦合器106的电路系统的迹线、通路、平面等。通过此布置，基底组件101及半导体装置封装103可经由电耦合器106及金属化结构108电耦合到外部装置。
半导体装置封装组合件100具有垂直紧凑设计。例如，基底组件101及多个半导体装置封装103直接堆叠在一起使得多个半导体装置封装103之间的接合线厚度(BLT)可为零或近零。在一些实施例中，基底组件101与邻近半导体装置封装103之间的BLT也可为零或近零。
在一些实施例中，基底组件101可在其中包含一或多个半导体组件102(例如，集成电路系统)。基底组件101可为电路板或常用于半导体装置封装中的其它类型的衬底，或基底组件可为半导体装置，例如逻辑装置、存储器装置或处理器。如所展示，基底组件101具有第一侧1011(例如，前侧/有源侧)及与第一侧1011相对的第二侧1013(例如，背侧/非有源侧)。
基底组件101可包含在基底组件101的第一侧1011处的钝化层1015。在一些实施例中，钝化层1015可包含氧化物层、惰性层(例如，不太可能与空气起化学反应或受腐蚀的层)，或其它适合保护层。例如，钝化层1015可包含保护膜。钝化层1015保护基底组件101。在一些实施例中，基底组件101可通过电耦合器(例如焊料凸块或焊料球)进一步耦合到中介层衬底。
如所展示，基底组件101包含电耦合到基底组件101中的半导体组件102的金属化结构105。在所说明实施例中，金属化结构105可包含界定迹线、通路及/或平面的一或多个金属化层。在一些实施例中，金属化层可包含铝(例如，铝垫)、铜或其它适合金属或导电材料。
在所说明实施例中，可在后段工艺(BEOL)制造过程期间形成金属化结构105。金属化结构105可包含接触区域107，接触区域107经配置以在半导体装置封装103堆叠于基底衬底101上时与最下半导体装置封装103(例如，电气地且物理地)接触。
在图1中所展示的所说明实施例中，个别半导体装置封装103具有第一侧1031(例如，前侧/有源侧/正面侧(face side))及与第一侧1031相对的第二侧1033(例如，背侧/非有源侧)。如所展示，个别半导体装置封装103也可包含在半导体装置封装103的第一侧1031处的钝化层1035以保护半导体装置封装103。在一些实施例中，钝化层1035可包含氧化物层、惰性层(例如，不太可能与空气起化学反应或受腐蚀的层)，或其它适合保护层。钝化层1035可替代地为预形成保护膜。
如所展示，个别半导体装置封装103也可包含在半导体装置封装103的第二侧1033处的电介质层1037以保护半导体装置封装103。在一些实施例中，电介质层1037可为电介质膜。
个别半导体装置封装103也可包含电耦合到半导体装置封装103中的一或多个半导体组件1032(例如，集成电路系统等)的金属化结构109。金属化结构109可延伸穿过半导体装置封装103的厚度。金属化结构109可包含铝、铜或其它适合金属或导电材料的层。金属化结构109可在BEOL制造过程期间形成，且包含迹线、通路或其它电特征的多个层。金属化结构109可具有在第一侧1031处的导电垫109a及在背侧1033处的接触区109b。
如图1中所展示，基底组件101及最下半导体装置封装103以“面对面”方式堆叠，使得基底组件101的第一侧1011(例如，“正面”侧)面向最下半导体装置封装103的第一侧1031(例如，“正面”侧)。最下半导体装置封装103上的钝化层1035可直接接触基底组件101上的钝化层1015，使得最下半导体装置封装103与基底组件101之间存在零BLT。然而，在一些实施例中，最下半导体装置封装103与基底组件101之间可存在极小间隙，使得存在近零BLT。还如图1中所展示，额外半导体装置封装103以“面对背”方式堆叠于最下半导体装置封装103上方。例如，一个半导体装置封装103的第二侧1033(“背”侧)直接耦合到邻近半导体装置封装103的第一侧1031(“正面”侧)。通过此布置，可快速地堆叠基底组件101及半导体装置封装103。随着更多半导体装置封装103彼此堆叠，半导体装置封装组合件100可具有更高装置密度。
半导体装置封装组合件100进一步包含在最下半导体装置封装103的第一侧1031处的金属凸块111(或金属柱)。金属凸块111电耦合到最下半导体装置封装103的金属化结构109及基底组件101的金属化结构105(例如，在接触区域107处)。金属凸块111可由铟或其它适合导电材料制成。在一些实施例中，金属凸块111可通过退火工艺(例如在一段时间内在100摄氏度到200摄氏度下加热金属凸块111)电耦合到基底组件101的第一金属化层105a。
个别半导体装置封装103具有在其第二侧1033处的凹部113(例如，“凹坑(divot)”或“沟槽”)，且金属凸块115(或金属柱)可定位于凹部113中。金属凸块115可电耦合到邻近半导体装置封装103的金属化结构109。通过此布置，本技术使基底组件101能够在未在基底组件101或半导体装置封装103中的任一者中使用TSV的情况下电耦合到半导体装置封装103。在一些实施例中，金属凸块115可通过退火工艺(例如将金属凸块115加热到约100摄氏度到300摄氏度(例如，200℃)达约50秒到200秒(例如，100秒))电耦合到半导体装置封装103。
在一些实施例中，半导体装置封装组合件100可为存储器装置，其中半导体装置封装103是存储器裸片(例如，DRAM、LPDRAM、SRAM、快闪等)。在一些实施例中，基底组件101可为逻辑装置、处理器、及/或另一存储器装置。
图2A到2J是根据本技术的用于制造半导体装置封装203(例如，图1中所描述的半导体装置封装103)的方法的示意性横截面视图。在图2A到2J各处，相同元件符号指代相同组件。参考图2A，在方法的此阶段，半导体装置封装203具有具第一侧2031(例如，前侧/有源侧)及与第一侧2031相对的第二侧2033(例如，背侧/非有源侧)的衬底2037。半导体装置封装203可具有在BEOL制造过程期间形成的金属化结构205，金属化结构205包含在衬底2037中的第一金属化层205a、第二金属化层205b及第三金属化层205c。在一些实施例中，第一金属化层205a可包含铝或另一适合金属或导电材料。例如，第一金属化层205a可为铝垫。第二金属化层205b可包含铜或另一适合金属或导电材料，且第三金属化层205c可包含铜或另一适合金属或导电材料。金属化结构205电耦合到半导体装置封装203中的一或多个半导体组件202(例如，集成电路系统)。
在一些实施例中，半导体装置封装203也可具有在金属化结构205的一部分与衬底2037之间的势垒层217。例如，势垒层217可邻近于第二金属化层205b。势垒层217可由金属(例如钽)制成以防止扩散到衬底2037中。例如，第二金属化层205b可包含铜，且势垒层217可由钽制成以抑制铜扩散到衬底2037中。
图2A展示在钝化层2035已经施覆到半导体装置封装203的第一侧2031以保护半导体装置封装203之后的半导体装置封装203。在一些实施例中，钝化层2035可包含氧化物层、惰性层(例如，不太可能与空气起化学反应或受腐蚀的层)、其它适合保护层，或预形成保护膜。半导体装置封装203也可包含在第一侧2031处的第一金属化层205a上的接触区域207。
图2B展示在金属凸块211已形成于接触区域207上之后的半导体装置封装203。金属凸块211电耦合到金属化结构205且经配置以提供到堆叠于半导体装置封装203上的另一半导体装置封装(例如，参见图1)的金属化结构的电及机械连接。金属凸块211可由铟或其它适合导电材料制成。
在一些实施例中，金属凸块211可具有大约10μm到20μm、或更明确来说大约15μm的垂直尺寸VD。可通过电镀工艺来形成金属凸块211，其中将晶种材料沉积于第一金属化层205a的接触区域207上，且接着将一导电材料镀覆到晶种材料上以在第一金属化层205a上形成金属凸块211。替代地，可通过喷墨工艺、冷退火或其它适合方法来形成金属凸块211。
图2C展示在半导体装置封装203已经由接合层213耦合到载体215之后的半导体装置封装203。载体215经配置以在下文参考图2D到2J描述的制造过程中暂时固持且支撑半导体装置封装203。载体215可为可重用的或一次性的，例如玻璃载体、硅载体或塑料载体。在一些实施例中，接合层213可为释离带(例如，气体敏感或温度敏感)、可流动粘合剂或其它适合材料。可使用流体(气体或液体)来溶解接合层213或使用激光来烧蚀接合层213以从载体215释离半导体装置封装203。
图2D说明在衬底2037已经薄化之后的半导体装置封装203。参考图2D，衬底2037可薄化到介于薄化表面219与第一侧2031之间的厚度D。在一些实施例中，衬底2037的厚度D的范围可从5μm到30μm，且例如不超过30μm、25μm、20μm、15μm、10μm或5μm。
通过将衬底2037薄化到此程度，可在未使用TSV的情况下接达半导体装置封装203的金属化结构205且将其电耦合到经堆叠半导体装置封装的其它金属化结构或半导体组件。一般来说，为在半导体结构中形成TSV，半导体衬底的最小厚度可为约50μm。此比本技术的半导体装置封装203及半导体装置封装103(图1)厚200％到1000％。因此，由本技术提供的经改进方法是有利的，至少因为其提供具有较小厚度(或垂直尺寸)且可在未形成TSV的情况下堆叠的半导体装置封装。其对于制造紧凑半导体装置或封装尤其有利。
图2E说明在第一经图案化光致抗蚀剂层221已形成于半导体装置封装203的第二侧2033(背侧/非有源侧)上之后的工艺的阶段。如所展示，第一经图案化光致抗蚀剂层221具有多个开口223(图2E中仅展示三个开口，第一开口223a、第二开口223b及第三开口223c)。如所展示，第一开口223a及第三开口223c在基底组件203的相对侧上。第一开口223a及第三开口223c可用于在工艺的稍后阶段中分离或“单粒化”半导体装置封装203。第二开口223b与半导体装置封装203中的金属化结构205的至少一部分对准。
图2F展示在开口226已经由第一开口223a及第三开口223c经形成穿过衬底2037以暴露钝化层2035之后的工艺的阶段。可通过蚀刻半导体装置封装203的衬底2037而形成开口226。在相同蚀刻工艺中，可通过第二开口223b在衬底2037中形成一凹部225(例如，凹坑或沟槽)(例如，第二开口223b在朝向半导体装置封装203的第一侧2031的方向上延伸)。凹部225可为暴露势垒层217的另一开口。如所展示，凹部225具有倾斜侧壁(在凹部225的左侧及右侧两者处，如图2F中所展示)，此可促成将另一半导体装置封装的金属凸块耦合到金属化层205。替代地，可在未形成经图案化光致抗蚀剂层221的情况下通过激光烧蚀衬底2037而形成开口226及凹部225。
图2G展示在第一光致抗蚀剂层221已经移除且电介质层227已形成于半导体装置封装203的第二侧2033上之后的工艺的阶段。可通过化学气相沉积(CVD)工艺来形成电介质层227，例如CVD原硅酸四乙酯(TEOS)层。替代地，可通过旋涂工艺来形成电介质层227。
图2H及2I展示在第二经图案化光致抗蚀剂层229(或第二光图案(photo-pattern)掩模)已形成于半导体装置封装203的第二侧2033(背侧/非有源侧)上之后的工艺的阶段。第二经图案化光致抗蚀剂层229填充第一开口223a及第三开口223c，且具有与金属结构205对准的开口231。图2I展示在开口231内的电介质层227及势垒层217已经移除以通过开口2133暴露第三金属化层205c之后的工艺的阶段。在一些实施例中，未移除势垒层217。考虑是否移除势垒层217的因素包含例如势垒层217、第三金属化层205c及金属凸块211中所使用的材料的类型。
图2J展示在已移除第二光致抗蚀剂层229之后的工艺的阶段。凹部225具有大于待附接到金属结构205的金属凸块211(以虚线展示)的横向尺寸L2的横向尺寸L1。因而，凹部225的侧壁225a及电介质层227的侧壁部分227a与金属凸块211的侧壁211a隔开。在工艺的此阶段，可移除载体215且可将一或多个半导体装置封装203彼此堆叠。
图3A到3I是说明根据本技术的形成半导体装置封装的方法的示意性横截面视图。在图3A到3I各处，相同元件符号指代相似组件。参考图3A，半导体装置封装300具有第一侧301(例如，前侧/有源侧)及与第一侧301相对的第二侧303(例如，背侧/非有源侧)。半导体装置封装300可具有衬底307及在BEOL制造过程期间形成的金属化结构305，金属化结构305包含第一金属化层305a、第二金属化层305b及第三金属化层305c。半导体装置封装300可具有耦合到金属化结构305中的特征的导电通路331。在图3A到3I中所展示的所说明实施例中，导电通路331耦合到第二金属化层305b。在其它实施例中，导电通路331可耦合到其它金属化层(例如，第一金属化层305a或第三金属化层305c)。金属化层305a到305c可包含形成一或多个电路(例如，带电电路(live circuit)、开路等)的导电迹线、垫、导电平面及/或电组件(例如，电容器、电阻器等)。
衬底307可为由硅或其它适合材料形成的半导体衬底，且集成电路系统可形成于衬底上/中以形成存储器装置、逻辑装置或处理器。在所说明实施例中，金属化结构305电耦合到衬底307中的半导体组件302(例如，集成电路系统)。第一金属化层305a可包含铝或其它适合金属或导电材料，且形成为一或多个垫。在一些实施例中，第二金属化层305b及第三金属化层305c可包含铜或其它适合金属或导电材料。
在一些实施例中，半导体装置封装300可具有在金属化结构305的部分与衬底307之间的势垒层(图3A中未展示，类似于图2A中所展示的势垒层217)。势垒层可替代地邻近于第二金属化层305b。在一些实施例中，势垒层可由金属(例如钽)制成，且第二金属化层305b可包含铜，使得钽势垒层抑制铜扩散到衬底307中。
半导体装置封装300也可包含在半导体装置封装300的第一侧301处的类似于图2A中所展示的钝化层2035的钝化层(未展示)。钝化层可保护半导体装置封装300。在一些实施例中，钝化层可包含氧化物层、惰性层(例如，不太可能与空气起化学反应或受腐蚀的层)，或其它适合保护层或保护膜。
如图3A中所展示，半导体装置封装300包含中心金属凸块308a及在中心金属凸块308a的两侧处的侧金属凸块308b(图3A中展示四个侧金属凸块308b)。如所展示，中心金属凸块308a具有大于侧金属凸块308b的垂直尺寸的垂直尺寸。例如，中心金属凸块308a可具有大约10μm到20μm的垂直尺寸VDC，且侧金属凸块308b可具有大约5μm到10μm的垂直尺寸VDS。垂直尺寸VDC可为大约15μm，而垂直尺寸VDS可为大约7.5μm。中心金属凸块308a比侧金属凸块308b高，使得在半导体装置封装300堆叠于另一半导体装置封装上时，中心金属凸块308a可定位于所述半导体装置封装的腔中，如下文关于图3G及3H描述。
中心金属凸块308a及侧金属凸块308b电耦合到金属化结构305且经配置以与另一半导体装置封装的金属化层电接触(例如，参见图3H)。在一些实施例中，金属凸块308a、308b可包含铟凸块。在其它实施例中，金属凸块308a、308b可包含其它适合导电材料。
在一些实施例中，中心金属凸块308a及侧金属凸块308b可为通过电镀工艺形成的柱。例如，可通过具有邻近于第一金属化层305a的晶种材料而形成金属凸块308a、308b，且可将导电材料镀覆到晶种材料上。在其它实施例中，可通过喷墨工艺或其它适合方法来形成金属凸块308a、308b。在一些实施例中，金属凸块308a、308b可经冷退火(例如，在200℃下)。
图3B展示在半导体装置封装300已经倒置且经由粘合剂316耦合到载体315之后的半导体装置封装300。载体315经配置以在下文关于图3C到3H描述的制造过程中固持且支撑半导体装置封装300。载体315可为由玻璃、硅或塑料制成的可重用载体或不可重用载体。将金属凸块308a及308b嵌入于粘合剂316中，粘合剂316可为树脂或其它适合材料的部分固化层。
图3C说明在衬底307已经薄化之后的半导体装置封装300。参考图3C，半导体装置封装300可经薄化使得薄化表面319与半导体装置封装203的第一侧2031之间的深度H1是大约10μm。深度H1的范围可从5μm到30μm，且更明确来说，深度H1不超过30μm、25μm、20μm、15μm、10μm或5μm。
通过将衬底307薄化到此程度，可在未使用TSV的情况下接达金属化结构305且将其电耦合到另一半导体装置封装的其它金属化层或半导体组件。一般来说，为在半导体结构中形成TSV，半导体结构可被薄化的半导体结构的最小深度是约50μm。因此，由本技术提供的经改进方法是有利的，至少部分因为其可制造且堆叠具有较小深度(或垂直尺寸)的半导体装置封装且无需形成TSV的处理步骤。其对于制造紧凑半导体装置或封装尤其有利。
图3C还展示在涂覆层333已形成于薄化表面319上之后的半导体封装300。涂覆层可为在后续处理(例如下文关于图3D及3E论述的光刻及其它工艺)中保护薄化衬底307的氧化物层。
图3D说明在经图案化光致抗蚀剂层321(或光图案掩模)已形成于半导体装置封装300的第二侧303(背侧/非有源侧)上之后的半导体封装300。如所展示，光致抗蚀剂层321具有多个开口323(识别为第一开口323a、第二开口323b及第三开口323c)。第一开口323a及第三开口323c形成于半导体装置封装300的相对侧上，且可稍后在工艺中用于分离或“单粒化”半导体装置封装300。第二开口323b在中线处，且更特定来说其可与中心金属凸块308a对准。
图3E展示在通道326a、326c已经由第一开口323a及第三开口323c经形成穿过半导体装置封装300之后的半导体装置封装300。可凭借通过开口323a、323c蚀刻衬底307而形成通道326a、326c。
在与形成通道326a、326c相同的工艺中，可经由第二开口323b形成穿过衬底307及金属化结构305的一部分的腔326b。腔326b可延伸到第二金属化层305b且借此暴露第二金属化层305b的一部分。
图3F展示在光致抗蚀剂层321及涂覆层333已经移除且电介质层327已形成于半导体装置封装300的第二侧303上之后的半导体装置封装300。在一些实施例中，可通过化学气相沉积(CVD)工艺来形成电介质层327，例如CVD原硅酸四乙酯(TEOS)层。替代地，可通过旋涂工艺或施覆预形成电介质膜而形成电介质层327。在一些实施例中，也可移除衬底307的部分以进一步薄化衬底。在此类实施例中，如图3F中所指示的深度H2可小于深度H1。
图3G展示在已移除通道326a及326c的底部及腔326b的底部处的电介质层327的部分之后的半导体装置封装300。在一些实施例中，可通过蚀刻工艺来移除电介质层327的部分。如图3G中所展示，在移除腔326b内的电介质层327的部分之后，第二金属化层305b的部分暴露于腔326b中。
图3H展示在连接位点350(图3H中展示四个连接位点350)已形成于半导体装置封装300的第二侧303上之后的半导体装置封装300。连接位点350与侧金属凸块308b对准，且经配置以按堆叠布置耦合到另一半导体装置封装的侧金属凸块(类似于上文所论述的侧金属凸块308b)且与所述侧金属凸块接触。在一些实施例中，可通过掩蔽/蚀刻工艺来形成多个连接位点350。多个连接位点350可由金属(例如铝、钛、铜等)制成。
图3I展示在载体315已经移除且相同配置的另一半导体装置封装300a堆叠于半导体装置封装300上之后的半导体装置封装300。如所展示，半导体封装300a的中心金属凸块308a经对准且定位于半导体装置封装300的腔326b中，且电耦合到半导体装置封装300的第二金属化层305b。半导体装置封装300a的侧金属凸块308b分别与半导体装置封装300的对应连接位点350对准且电耦合到所述对应连接位点350。以此方式，数个半导体装置封装300可以零或近零BLT且在未形成穿过衬底307的TSV的情况下彼此堆叠。
图4A到4D说明处理与关于图1所描述的半导体装置封装组合件100类似或相同的半导体装置封装组合件401的方法，但半导体装置封装也可用于裸片堆叠中。半导体装置封装组合件401中的每一者具有正面侧4011及背侧4013。在图4A中，通过暂时载体403承载半导体装置封装组合件401。多个半导体装置封装组合件401中的每一者包含在背侧4013处的基底衬底(例如，图1中的基底组件101)及在正面侧4011处的多个半导体装置封装(例如，半导体装置封装103或203)。在所说明实施例中，半导体装置封装组合件401的背侧4013耦合到暂时载体403，使得装置封装组合件401彼此隔开。
图4B展示在已通过囊封材料405覆盖半导体装置封装组合件401之后的组合件。在一些实施例中，囊封材料405可包含树脂、塑料、硅、氧化物、聚合物或其它适合电介质材料。
图4C展示在已从半导体装置封装组合件401卸离暂时载体403之后的组合件。在图4C中，与图4B相比，半导体装置封装组合件401倒置。可移除图4C中所展示的组合件的上部(例如，在如所指示的平面P上方的部分)使得可暴露半导体装置封装组合件401的金属化结构4018。
图4D展示在聚合物层407已形成于半导体装置封装组合件401上之后的组合件。方法可包含使用聚合物层407来形成重布结构409。重布结构409电耦合到个别半导体装置封装组合件401中的金属化层4018。在一些实施例中，重布结构409可包含铜或其它适合导电材料。
如图4D中所展示，多个连接器411可形成于重布结构409上且电耦合到重布结构409。连接器411进一步电耦合到半导体装置封装的金属化结构及个别半导体装置封装组合件401中的基底组件。在一些实施例中，连接器411可为球栅阵列(BGA)，包含焊料球、垫或其它适合连接装置。接着，可通过在由图4D中所展示的虚线指示的位置处切穿囊封材料405而“单粒化”或分离半导体装置封装组合件401。
图5A到5D说明根据本技术的处理半导体装置封装组合件501的方法。在图5A中，通过暂时载体503承载半导体装置封装组合件501，且半导体装置封装组合件501中的每一者具有正面侧5011及背侧5013。在此实施例中，半导体装置封装组合件501的正面侧5011耦合到暂时载体503，与图4A及4B中的背侧5013相反。半导体装置封装组合件501经隔开使得其稍后可在单粒化工艺期间分离。
图5B展示在已通过囊封材料505覆盖半导体装置封装组合件501之后的组合件。在一些实施例中，囊封材料505可包含树脂、塑料、硅、氧化物、聚合物或其它适合电介质材料。
图5C展示在已从半导体装置封装组合件501卸离暂时载体503之后的组合件。在图5C中，与图5B相比，通过囊封材料505覆盖的半导体装置封装组合件501倒置。
图5D展示在聚合物层507已形成于半导体装置封装组合件501上之后的组合件。方法可包含使用聚合物结构507来形成重布结构509。重布结构509电耦合到个别半导体装置封装组合件501中的金属化层(例如，金属化结构105或205)。在一些实施例中，重布结构509可包含铜或其它适合导电材料。
如图5D中所展示，多个连接器511可形成于重布结构509上且电耦合到重布结构509。连接器511进一步电耦合到半导体装置封装的金属化结构及个别半导体装置封装组合件501中的基底组件。在一些实施例中，连接器511可为BGA连接器，其包含焊料球、垫或其它适合连接装置。接着，可通过在由图5D中所展示的虚线指示的位置处切穿囊封材料505而“单粒化”或分离半导体装置封装组合件501。
具有上文关于图1到5D所描述的特征的半导体装置中的任一者可并入到大量更大及/或更复杂系统中的任一者中，所述系统的代表性实例是图6中示意性地展示的系统600。系统600可包含处理器601、存储器603(例如，SRAM、DRAM、快闪及/或其它存储器装置)、输入/输出装置605及/或其它子系统或组件607。上文关于图1到5D所描述的半导体组合件、装置及装置封装可包含于图6中所展示的组件中的任一者中。结果系统600可经配置以执行各种各样的适合计算、处理、存储、感测、成像及/或其它功能中的任一者。因此，系统600的代表性实例包含(而不限于)计算机及/或其它数据处理器，例如桌面计算机、膝上型计算机、因特网设备、掌上型装置(例如，掌上计算机、穿戴式计算机、蜂窝或移动电话、个人数字助理、音乐播放器等)、平板计算机、多处理器系统、基于处理器的或可编程消费性电子器件、网络计算机及微型计算机。系统600的额外代表性实例包含灯、相机、车辆等。关于这些及其它实例，系统600可容置于单个单元中或分布于多个互连单元上(例如，通过通信网络)。因此，系统600的组件可包含本地及/或远程存储器存储装置及各种各样的适合计算机可读媒体中的任一者。
本公开不希望为详尽的或将本技术限制于本文中所公开的精确形式。尽管本文中出于说明性目的公开特定实施例，但各种等效修改在未偏离本技术的情况下是可行的，如相关领域的一般技术人员将认识到。在一些情况中，尚未详细展示或描述众所周知的结构及功能以避免不必要地使本技术的实施例的描述不清楚。尽管本文中可依特定顺序呈现方法的步骤，但替代实施例可依不同顺序执行步骤。类似地，可在其它实施例中组合或消除在特定实施例的上下文中公开的本技术的某些方面。此外，虽然可已在本技术的某些实施例的上下文中公开与所述实施例相关联的优点，但其它实施例也可展现此类优点，且并非全部实施例都需必然展现此类优点或本文中所公开的其它优点以落在本技术的范围内。因此，本公开及相关联技术可涵盖本文中未明确展示或描述的其它实施例。
在本公开各处，单数术语“一”、“一个”及“所述”包含复数指涉物，除非上下文另有明确指示。类似地，关于两个或更多个品项的列表，除非字词“或”明确限于仅意味着排除其它品项的单个品项，否则“或”在此列表中的使用应解释为包含(a)列表中的任何单个品项、(b)列表中的全部品项、或(c)列表中的品项的任何组合。另外，术语“包括”在各处用于意味着至少包含(若干)所述特征，使得不排除任何较大数目个相同特征及/或额外类型的其它特征。本文中对“一个实施例”、“一些实施例”或类似表述的引用意味着结合实施例描述的特定特征、结构、操作或特性可包含于本技术的至少一个实施例中。因此，此类词组或表述出现在本文中不一定都是指相同实施例。此外，可在一或多个实施例中以任何适合方式组合各种特定特征、结构、操作或特性。
从前文将了解，本文中已出于说明目的描述本技术的特定实施例，但可作出各种修改而不偏离本发明的范围。本技术除如通过所附权利要求限制外并不受限。

Claims (27)

1.一种半导体装置封装组合件，其包括：
基底组件，其具有前侧及背侧，所述基底组件具有在所述前侧处的第一金属化结构，且所述第一金属化结构暴露于所述前侧处的接触区域中；
半导体装置裸片堆叠，每一半导体装置裸片具有第一侧、具有凹部的第二侧、及第二金属化结构，所述第二金属化结构具有在所述第一侧处的接触垫及暴露于所述第二侧处的所述凹部中的接触区；及
金属凸块，其至少部分定位于所述半导体装置裸片的所述第二侧处的所述凹部中，其中所述金属凸块电耦合到一个半导体装置组合件的第二金属化结构的所述接触垫及邻近半导体装置组合件的接触区，且其中额外金属凸块耦合到所述半导体装置裸片中的最下半导体装置裸片的所述接触垫及所述基于组件的所述第一金属化结构；
其中所述半导体装置封装在无穿硅通路的情况下经由所述第一金属化结构及所述第二金属化结构彼此电耦合且电耦合到所述基底组件。
2.根据权利要求1所述的半导体装置封装组合件，其中所述金属凸块跨不超过20μm的距离从一个半导体装置的所述接触垫延伸到邻近半导体装置的所述接触区。
3.根据权利要求1所述的半导体装置封装组合件，其中所述金属凸块是中心金属凸块，且其中所述半导体装置封装组合件进一步包括定位于所述中心金属凸块的一个侧处的侧金属凸块。
4.根据权利要求1所述的半导体装置封装组合件，其中所述金属凸块的垂直尺寸不超过15μm。
5.根据权利要求1所述的半导体装置封装组合件，其中所述金属凸块的垂直尺寸是约10μm。
6.根据权利要求1所述的半导体装置封装组合件，其中所述第一金属化结构及所述第二金属化结构具有迹线及通路而未使用从所述半导体装置堆叠裸片的所述第一侧直接延伸到所述第二侧的穿硅通路(TSV)。
7.根据权利要求1所述的半导体装置封装组合件，其中所述第一金属化结构及所述第二金属化结构中的至少一者包含铝。
8.根据权利要求1所述的半导体装置封装组合件，其中所述第一金属化结构及所述第二金属化结构中的至少一者包含铜。
9.根据权利要求1所述的半导体装置封装组合件，其中所述第二金属化结构包含第一金属化层、第二金属化层及第三金属化层，且其中所述第一金属化层电耦合到所述金属凸块。
10.根据权利要求9所述的半导体装置封装组合件，其中所述第一金属化层包含铝，且其中所述第二金属化层包含铜，且其中所述第三金属化层包含铜。
11.一种半导体装置堆叠裸片组合件，其包括：
第一半导体装置裸片，其具有前侧及背侧，所述第一半导体装置裸片具有在所述前侧处的第一金属化结构及在所述背侧处的第一衬底，所述第一金属化结构经由腔从所述背侧暴露；
第二半导体装置裸片，其具有第一侧及第二侧，所述第二半导体装置裸片具有在所述第一侧处的第二金属化结构及在所述第二侧处的第二衬底；及
金属柱，其至少部分定位于所述腔中且电耦合到所述第二金属化结构及所述第一金属化结构。
12.根据权利要求11所述的半导体装置堆叠裸片组合件，其中所述金属柱包含铟。
13.根据权利要求11所述的半导体装置堆叠裸片组合件，其中所述金属柱是中心金属柱，且其中所述半导体装置堆叠裸片组合件进一步包括定位于所述中心金属柱的一个侧处的侧金属柱。
14.根据权利要求11所述的半导体装置堆叠裸片组合件，其中所述中心柱的垂直尺寸不超过20μm。
15.根据权利要求11所述的半导体装置堆叠裸片组合件，其中所述中心柱的垂直尺寸是约10μm。
16.根据权利要求11所述的半导体装置堆叠裸片组合件，其中所述第一金属化结构及所述第二金属化结构在未使用TSV的情况下电耦合。
17.根据权利要求11所述的半导体装置堆叠裸片组合件，其中所述第一金属化结构及所述第二金属化结构中的至少一者包含铝。
18.根据权利要求11所述的半导体装置堆叠裸片组合件，其中所述第一金属化结构及所述第二金属化结构中的至少一者包含铜。
19.根据权利要求11所述的半导体装置堆叠裸片组合件，其中所述第二金属化结构包含第一金属化层、第二金属化层及第三金属化层，且其中所述第一金属化层电耦合到所述金属柱。
20.根据权利要求19所述的半导体装置堆叠裸片组合件，其中所述第一金属化层包含铝，且其中所述第二金属化层包含铜，且其中所述第三金属化层包含铜。
21.根据权利要求11所述的半导体装置堆叠裸片组合件，其中所述第一金属化结构包含第一金属化层、第二金属化层及第三金属化层，且其中所述第三金属化层电耦合到所述金属柱。
22.根据权利要求21所述的半导体装置堆叠裸片组合件，其中所述第一金属化层包含铝，且其中所述第二金属化层包含铜，且其中所述第三金属化层包含铜。
23.一种半导体装置堆叠裸片组合件，其包括：
第一半导体装置裸片，其具有前侧及背侧，所述半导体装置裸片具有在所述前侧处的第一金属化结构，所述第一金属化结构经由第一凹部从所述背侧暴露；
第二半导体装置裸片，其具有第一侧及第二侧，所述半导体装置裸片具有在所述第一侧处的第二金属化结构，所述第二金属化结构经由第二凹部从所述第二侧暴露，所述第二凹部与所述第一凹部对准；及
金属凸块，其至少部分定位于所述第一凹部中且电耦合到所述第二金属化结构及所述第一金属化结构，其中所述第一半导体装置裸片直接堆叠于所述第二半导体装置裸片上，且所述第一半导体装置裸片及所述第二半导体装置裸片在无穿硅通路的情况下彼此电耦合。
24.根据权利要求23所述的半导体装置堆叠裸片组合件，其中所述金属凸块包含铟。
25.根据权利要求23所述的半导体装置堆叠裸片组合件，其中所述金属凸块是中心金属凸块，且其中所述半导体装置堆叠裸片组合件进一步包括定位于所述中心金属凸块的一个侧处的侧金属凸块。
26.根据权利要求23所述的半导体装置堆叠裸片组合件，其中所述垂直尺寸不超过15μm。
27.根据权利要求23所述的半导体装置堆叠裸片组合件，其中所述垂直尺寸是约10μm。
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