CN105047629B - 影像感测元件封装构件 - Google Patents
影像感测元件封装构件 Download PDFInfo
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- CN105047629B CN105047629B CN201510390848.4A CN201510390848A CN105047629B CN 105047629 B CN105047629 B CN 105047629B CN 201510390848 A CN201510390848 A CN 201510390848A CN 105047629 B CN105047629 B CN 105047629B
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- image sensor
- crystal grain
- active surface
- packing component
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- 238000012856 packing Methods 0.000 title claims abstract description 32
- 239000013078 crystal Substances 0.000 claims abstract description 37
- 238000003466 welding Methods 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 238000005538 encapsulation Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 238000007599 discharging Methods 0.000 claims description 3
- 239000012774 insulation material Substances 0.000 claims 1
- 238000002360 preparation method Methods 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 description 37
- 235000012431 wafers Nutrition 0.000 description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000000034 method Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229920000620 organic polymer Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000007769 metal material Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QRJOYPHTNNOAOJ-UHFFFAOYSA-N copper gold Chemical compound [Cu].[Au] QRJOYPHTNNOAOJ-UHFFFAOYSA-N 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
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Abstract
本发明公开一种影像感测元件封装构件及其制作方法,该影像感测元件封装构件,其包含有:一影像感测晶粒,其具有一主动面以及相对于该主动面的一背面,且在该主动面上设有一影像感测元件区域以及一外接垫;一直通硅晶穿孔结构,贯穿该影像感测晶粒,连接该外接垫;多层重布线路,形成在该像感测晶粒的该背面上;以及一防焊层,覆盖在该多层重布线路上。
Description
本发明申请是2011年3月21日提交的申请号为No.201110067998.3的名为“影像感测元件封装构件及其制作方法”的发明专利申请的分案申请。
技术领域
本发明涉及光学元件封装技术领域,特别是涉及一种具备多层重布线路(multi-layer RDL)的影像感测元件封装构件及其制作方法。
背景技术
近年来,固态影像感测元件已被大量运用在手机、汽车以及电脑产业,然而,当固态影像感测元件朝向更高的图元解析度与更小的图元尺寸发展时,合格却受到冲击,而相机模块在组装过程中的物理性污染,也会降低合格。因此,封装半导体晶粒逐渐成为在业界中被广泛采用的方案。其中,由于晶片级技术在制作工艺上具备经济效益,逐渐成为较佳的解决方案。
晶片级封装较具挑战性的层面之一,就是内部连结设计。在顶部、侧面、底部接点三种选择中,又以底部接点最具吸引力,因为它能使影像感测晶粒能正面朝上,以配合相机模块组装所需的方向。由于高解析度影像感测器越来越需要高密度焊接垫,因此和焊接垫相容的直通硅晶穿孔技术(through silicon via,简称为TSV)也随之受到注目。
发明内容
本发明的主要目的在于提供一种采用直通硅晶穿孔技术及具备多层重布线路的影像感测元件封装构件及其制作方法。
为达上述目的,本发明较佳实施例提供一种影像感测元件封装构件,包含有:一影像感测晶粒,其具有一主动面以及相对于该主动面的一背面,且在该主动面上设有一影像感测元件区域以及一外接垫;一直通硅晶穿孔结构,贯穿该影像感测晶粒,连接该外接垫;一第一绝缘层,形成在该影像感测晶粒的该背面及该硅晶穿孔结构内;一第一重布线路层,形成在该第一绝缘层上并与该外接垫电连接;一第二绝缘层,覆盖该第一重布线路层及该第一绝缘层;一第二重布线路层,形成在该第二绝缘层上并与该第一重布线路层电连接;以及一防焊层,覆盖在该第二重布线路层及该第二绝缘层上。
从另一角度来看,本发明提供一种影像感测元件封装构件,包含有:一影像感测晶粒,其具有一主动面以及相对于该主动面的一背面,且在该主动面上设有一影像感测元件区域以及一外接垫;一直通硅晶穿孔结构,贯穿该影像感测晶粒,连接该外接垫;多层重布线路,形成在该像感测晶粒的该背面上;以及一防焊层,覆盖在该多层重布线路上。其中在该防焊层中设有至少一开孔,曝露出一焊接垫,并在该焊接垫上设有一焊接锡球。在该防焊层中设有多个假开孔,用来释放应力。该多层重布线路至少包含有一防电磁干扰金属图案。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举较佳实施方式,并配合所附图式,作详细说明如下。然而如下的较佳实施方式与图式仅供参考与说明用,并非用来对本发明加以限制者。
附图说明
图1为本发明一较佳实施例所绘示的影像感测元件封装构件的剖面示意图;
图2为本发明另一较佳实施例所绘示的影像感测元件封装构件的剖面示意图。
图3为本发明又另一较佳实施例所绘示的影像感测元件封装构件的剖面示意图;
图4至图11例示本发明影像感测元件封装构件的制作方法。
主要元件符号说明
1 影像感测元件封装构件
1a 影像感测元件封装构件
10 影像感测晶粒
10a 主动面
10b 背面
11 影像感测元件区域
12 外接垫
13 直通硅晶穿孔结构
14 第一绝缘层
15 第一重布线路层
15a 连接垫
15b 防电磁干扰金属图案
16 第二绝缘层
16a 开孔
17 第二重布线路层
17a 焊接垫
18 防焊层
18a 开孔
18b 假开孔
19 焊接锡球
20 封装用光学盖板
22 支撑堰体结构
24 凹穴结构
100 影像感测晶片
100a 主动面
100b 背面
具体实施方式
本发明运用创新的连结技术,贯穿硅晶层直接连结至影像感测晶粒的外接垫;小巧的尺寸与连结的位置,让封装背面可支援高密度的球栅阵列封装介面,使后续的封装相容于表面粘着组装制作工艺。本发明可以相容于晶片级封装(wafer-level packaging,简称为WLP)制作工艺并且采用直通硅晶穿孔技术,其中所谓的晶片级封装制作工艺系在晶片状态时就封装晶粒,再进行后段组装制作工艺,然后,晶片再进行切割,成为独立封装晶粒。
请参阅图1,其为依据本发明一较佳实施例所绘示的影像感测元件封装构件的剖面示意图。如图1所示,影像感测元件封装构件1包含有一影像感测晶粒10,其具有一主动面10a以及相对于主动面(active side)10a的一背面(backside)10b,且在主动面10a上设有一影像感测元件区域11以及外接垫12。影像感测元件区域11可以是CMOS影像感测元件,但不限于此。
在影像感测晶粒10的主动面10a上另覆盖一封装用光学盖板20,例如,透镜等级玻璃或石英,而在封装用光学盖板20与影像感测晶粒10的主动面10a之间另设有支撑堰体结构22,例如,环氧树脂(epoxy resin)、聚亚酰胺(polyimide)、光致抗蚀剂或防焊阻剂(solder resist)材料等等,如此使光学盖板20、支撑堰体结构22与影像感测晶粒10的主动面10a之间构成一密闭的凹穴结构24,而影像感测元件区域11就是位于凹穴结构24内部。此外,支撑堰体结构22与影像感测晶粒10的主动面10a之间可以利用接合材料(图未示)进行粘合。
根据本发明的较佳实施例,影像感测元件封装构件1另包含有一直通硅晶穿孔(TSV)结构13,其贯穿影像感测晶粒10,并连通影像感测晶粒10的主动面10a与背面10b,用来曝露出位于影像感测晶粒10的主动面10a上部分的外接垫12。在影像感测晶粒10的背面10b以及硅晶穿孔结构13的侧壁上则顺应的形成有第一绝缘层14,例如,氧化硅、氮化硅或氮氧化硅等等。此外,第一绝缘层14也可以采用有机高分子绝缘材料。
在第一绝缘层14上形成有一第一重布线路层15,例如,铝金属线路图案或者铜金属线路图案。第一重布线路层15顺应的覆盖在硅晶穿孔结构13的侧壁上以及底部,并且与外接垫12电连接。此外,第一重布线路层15至少包含有一连接垫15a。在第一重布线路层15以及第一绝缘层14上另有一第二绝缘层16,例如,氧化硅、氮化硅或氮氧化硅等等。第二绝缘层16也可以采用有机高分子绝缘材料。在第二绝缘层16中设有至少一开孔16a,曝露出部分的连接垫15a。
在第二绝缘层16上形成有一第二重布线路层17,例如,钛、铜、镍、金、铝或上述金属之组合。第二重布线路层17可以是由可焊接(soldable)金属材料所构成者。第二重布线路层17与第一重布线路层15可以采用相同的导电材料或者不同的导电材料,也可以是不同的厚度。第二重布线路层17填入开孔16a,并与曝露出的连接垫15a电连接。第二重布线路层17至少包含有一焊接垫(solder pad)17a。在第二重布线路层17以及第二绝缘层16上另有一防焊层18,例如,环氧树脂、聚亚酰胺、光致抗蚀剂等等。在防焊层18中设有至少一开孔18a,曝露出部分的焊接垫17a。在焊接垫17a上则设有焊接锡球19。
请参阅图2,其为依据本发明另一较佳实施例所绘示的影像感测元件封装构件的剖面示意图。如图2所示,影像感测元件封装构件1a同样包含有一影像感测晶粒10,其具有一主动面10a以及相对于主动面10a的一背面10b,且在主动面10a上设有一影像感测元件区域11以及外接垫12。
同样的,影像感测元件封装构件1a包含有一直通硅晶穿孔结构13,其贯穿影像感测晶粒10,并连通影像感测晶粒10的主动面10a与背面10b,用来曝露出位于影像感测晶粒10的主动面10a上部分的外接垫12。在影像感测晶粒10的背面10b以及硅晶穿孔结构13的侧壁上则顺应的形成有第一绝缘层14,例如,氧化硅、氮化硅或氮氧化硅等等。第一绝缘层14也可以采用有机高分子绝缘材料。
根据本发明的另一较佳实施例,在第一绝缘层14上形成有一第一重布线路层15,例如,铝金属线路图案或者铜金属线路图案。第一重布线路层15顺应的覆盖在硅晶穿孔结构13的侧壁上以及底部,并且与外接垫12电连接。此外,第一重布线路层15至少包含有一连接垫15a以及一防电磁干扰金属图案15b。在第一重布线路层15以及第一绝缘层14上另有一第二绝缘层16,例如,氧化硅、氮化硅或氮氧化硅等等。在第二绝缘层16设有至少一开孔16a,曝露出部分的连接垫15a。
在第二绝缘层16上形成有一第二重布线路层17,例如,钛、铜、镍、金、铝或上述金属的组合。第二重布线路层17填入开孔16a,并与曝露出的连接垫15a电连接。第二重布线路层17至少包含有一焊接垫17a。在第二重布线路层17以及第二绝缘层16上另有一防焊层18,例如,环氧树脂、聚亚酰胺、光致抗蚀剂等等。在防焊层18设有至少一开孔18a,曝露出部分的焊接垫17a。在焊接垫17a上则设有焊接锡球19。此外,在防焊层18设有多个假开孔(dummyopenings)18b,其中,假开孔18b可以是圆形、矩形、长条形、锯齿形或不规则形状。
图2中的影像感测元件封装构件1a与图1中的影像感测元件封装构件1的差别在于:1)图2中的影像感测元件封装构件1a具有一防电磁干扰金属图案15b,可以保护影像感测晶粒10免受电磁干扰;以及2)图2中的影像感测元件封装构件1a在防焊层18设有多个假开孔18b,可以释放形成在影像感测晶粒10的背面10b上的绝缘层所产生的应力,也可以用来作为破裂停止(crack stop)机制。
请参阅图3,其为依据本发明又另一较佳实施例所绘示的影像感测元件封装构件的剖面示意图。如图3所示,同样的,在第二重布线路层17以及第二绝缘层16上设有一防焊层18,例如,环氧树脂、聚亚酰胺、光致抗蚀剂等等。在防焊层18设有至少一开孔18a,曝露出部分的焊接垫17a。在焊接垫17a上则设有焊接锡球19。在防焊层18设有多个假开孔18b,其中,假开孔18b可以填入绝缘材料,以释放影像感测晶粒10的背面10b上的应力。
图4至图11例示制作如图1中的影像感测元件封装构件1的方法。首先,如图4所示,提供一影像感测晶片100,其具有一主动面100a以及相对于主动面100a的一背面100b,且在主动面100a上设有至少一影像感测元件区域11以及外接垫12。影像感测元件区域11可以是CMOS影像感测元件,但不限于此。
在影像感测晶片100的主动面100a上另覆盖一封装用光学盖板20,例如,透镜等级玻璃或石英,而在封装用光学盖板20与影像感测晶片100的主动面100a之间另设有支撑堰体结构22,例如,环氧树脂、聚亚酰胺、光致抗蚀剂或防焊阻剂材料等等,如此使光学盖板20、支撑堰体结构22与影像感测晶片100的主动面100a之间构成一密闭的凹穴结构24,而影像感测元件区域11就是位于凹穴结构24内部。此外,支撑堰体结构22与影像感测晶片100的主动面100a之间可以利用接合材料(图未示)进行粘合。接着,将影像感测晶片100的背面100b研磨掉一预定厚度。
如图5所示,在完成晶片晶背研磨制作工艺之后,接着利用光刻及蚀刻制作工艺,从影像感测晶片100的背面100b蚀刻出直通硅晶穿孔(TSV)结构13,其贯穿影像感测晶片100,并连通影像感测晶片100的主动面100a与背面100b,用来曝露出位于主动面100a上部分的外接垫12。
如图6所示,在影像感测晶片100的背面100b以及硅晶穿孔结构13的侧壁上顺应的形成一第一绝缘层14,例如,氧化硅、氮化硅或氮氧化硅等等。第一绝缘层14也可以采用有机高分子绝缘材料。然后再利用光刻及蚀刻制作工艺,在硅晶穿孔结构13的底部上的第一绝缘层14中形成一开口14a,曝露出部分的外接垫12。
如图7所示,接下来,在第一绝缘层14上形成一第一重布线路层15,例如,铝金属线路图案或者铜金属线路图案。第一重布线路层15顺应的覆盖在硅晶穿孔结构13的侧壁上以及底部,并且与外接垫12电连接。此外,第一重布线路层15至少包含有一连接垫15a。
如图8所示,接着,在第一重布线路层15以及第一绝缘层14上形成一第二绝缘层16,例如,氧化硅、氮化硅或氮氧化硅等等。第二绝缘层16也可以采用有机高分子绝缘材料。然后再利用光刻及蚀刻制作工艺,在第二绝缘层16形成至少一开孔16a,曝露出部分的连接垫15a。
如图9所示,接下来,在第二绝缘层16上形成一第二重布线路层17,例如,钛、铜、镍、金、铝或上述金属之组合。第二重布线路层17也可以是由可焊接金属材料所构成者。第二重布线路层17与第一重布线路层15可以采用相同的导电材料或者不同的导电材料,也可以是不同的厚度。第二重布线路层17填入开孔16a,并与曝露出的连接垫15a电连接。第二重布线路层17至少包含有一焊接垫17a。
如图10及图11所示,在第二重布线路层17以及第二绝缘层16上形成一防焊层18,例如,环氧树脂、聚亚酰胺、光致抗蚀剂等等。然后在防焊层18中形成至少一开孔18a,曝露出部分的焊接垫17a。然后,在开孔18a内的焊接垫17a上形成一焊接锡球19。最后,进行晶片切割制作工艺,形成如图1中的影像感测元件封装构件1。熟悉该项技术人士应能理解图4至图11中双层的重布线路层的制作方法仅为示意,本发明并不限于双层的重布线路层,熟悉该项技术人士更可以利用所揭露的方法步骤形成多层的重布线路层。
本发明的主要技术特征至少包括:1)采晶片级封装制作工艺结合直通硅晶穿孔技术,并在影像感测晶粒的背面形成多层重布线路,故在设计上允许更多数量的输出输入(I/O)接点,以及具备更弹性的线路布局与成本上优势;2)在第一重布线路层中可以形成防电磁干扰金属图案,可以保护影像感测晶粒免受电磁干扰;以及3)在防焊层可以设有多个假开孔,用来释放绝缘层所产生的应力,也可以用来作为破裂停止机制。
以上所述仅为本发明的较佳实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (5)
1.一种影像感测元件封装构件,包含有:
影像感测晶粒,其具有主动面以及相对于该主动面的背面,且在该主动面上设有影像感测元件区域以及外接垫;
直通硅晶穿孔结构,贯穿该影像感测晶粒,连接该外接垫;
多层重布线路,形成在该像感测晶粒的该背面上,该多层重布线路至少包含有一防电磁干扰金属图案;以及
防焊层,其覆盖在该多层重布线路上,其中在该防焊层中设有多个假开孔,用来释放应力。
2.如权利要求1所述的影像感测元件封装构件,其中在该影像感测晶粒的该主动面上另覆盖一封装用光学盖板。
3.如权利要求2所述的影像感测元件封装构件,其中在该封装用光学盖板与该影像感测晶粒的该主动面之间另设有一支撑堰体结构。
4.如权利要求1所述的影像感测元件封装构件,其中在该防焊层中设有至少一开孔,曝露出一焊接垫,并在该焊接垫上设有一焊接锡球。
5.如权利要求1所述的影像感测元件封装构件,其中在该多个假开孔内填入一绝缘材料。
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