CN105047629A - 影像感测元件封装构件及其制作方法 - Google Patents
影像感测元件封装构件及其制作方法 Download PDFInfo
- Publication number
- CN105047629A CN105047629A CN201510390848.4A CN201510390848A CN105047629A CN 105047629 A CN105047629 A CN 105047629A CN 201510390848 A CN201510390848 A CN 201510390848A CN 105047629 A CN105047629 A CN 105047629A
- Authority
- CN
- China
- Prior art keywords
- image sensor
- crystal grain
- active surface
- packing component
- image sensing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title abstract description 14
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000013078 crystal Substances 0.000 claims description 37
- 238000012856 packing Methods 0.000 claims description 31
- 238000003466 welding Methods 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 238000005538 encapsulation Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 7
- 238000007599 discharging Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 38
- 235000012431 wafers Nutrition 0.000 description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229920000620 organic polymer Polymers 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02313—Subtractive methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0239—Material of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/024—Material of the insulating layers therebetween
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/2908—Plural core members being stacked
- H01L2224/29082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
本发明公开一种影像感测元件封装构件及其制作方法,该影像感测元件封装构件,其包含有:一影像感测晶粒,其具有一主动面以及相对于该主动面的一背面,且在该主动面上设有一影像感测元件区域以及一外接垫;一直通硅晶穿孔结构,贯穿该影像感测晶粒,连接该外接垫;多层重布线路,形成在该像感测晶粒的该背面上;以及一防焊层,覆盖在该多层重布线路上。
Description
本发明申请是2011年3月21日提交的申请号为No.201110067998.3的名为“影像感测元件封装构件及其制作方法”的发明专利申请的分案申请。
技术领域
本发明涉及光学元件封装技术领域,特别是涉及一种具备多层重布线路(multi-layerRDL)的影像感测元件封装构件及其制作方法。
背景技术
近年来,固态影像感测元件已被大量运用在手机、汽车以及电脑产业,然而,当固态影像感测元件朝向更高的图元解析度与更小的图元尺寸发展时,合格却受到冲击,而相机模块在组装过程中的物理性污染,也会降低合格。因此,封装半导体晶粒逐渐成为在业界中被广泛采用的方案。其中,由于晶片级技术在制作工艺上具备经济效益,逐渐成为较佳的解决方案。
晶片级封装较具挑战性的层面之一,就是内部连结设计。在顶部、侧面、底部接点三种选择中,又以底部接点最具吸引力,因为它能使影像感测晶粒能正面朝上,以配合相机模块组装所需的方向。由于高解析度影像感测器越来越需要高密度焊接垫,因此和焊接垫相容的直通硅晶穿孔技术(throughsiliconvia,简称为TSV)也随之受到注目。
发明内容
本发明的主要目的在于提供一种采用直通硅晶穿孔技术及具备多层重布线路的影像感测元件封装构件及其制作方法。
为达上述目的,本发明较佳实施例提供一种影像感测元件封装构件,包含有:一影像感测晶粒,其具有一主动面以及相对于该主动面的一背面,且在该主动面上设有一影像感测元件区域以及一外接垫;一直通硅晶穿孔结构,贯穿该影像感测晶粒,连接该外接垫;一第一绝缘层,形成在该影像感测晶粒的该背面及该硅晶穿孔结构内;一第一重布线路层,形成在该第一绝缘层上并与该外接垫电连接;一第二绝缘层,覆盖该第一重布线路层及该第一绝缘层;一第二重布线路层,形成在该第二绝缘层上并与该第一重布线路层电连接;以及一防焊层,覆盖在该第二重布线路层及该第二绝缘层上。
从另一角度来看,本发明提供一种影像感测元件封装构件,包含有:一影像感测晶粒,其具有一主动面以及相对于该主动面的一背面,且在该主动面上设有一影像感测元件区域以及一外接垫;一直通硅晶穿孔结构,贯穿该影像感测晶粒,连接该外接垫;多层重布线路,形成在该像感测晶粒的该背面上;以及一防焊层,覆盖在该多层重布线路上。其中在该防焊层中设有至少一开孔,曝露出一焊接垫,并在该焊接垫上设有一焊接锡球。在该防焊层中设有多个假开孔,用来释放应力。该多层重布线路至少包含有一防电磁干扰金属图案。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举较佳实施方式,并配合所附图式,作详细说明如下。然而如下的较佳实施方式与图式仅供参考与说明用,并非用来对本发明加以限制者。
附图说明
图1为本发明一较佳实施例所绘示的影像感测元件封装构件的剖面示意图;
图2为本发明另一较佳实施例所绘示的影像感测元件封装构件的剖面示意图。
图3为本发明又另一较佳实施例所绘示的影像感测元件封装构件的剖面示意图;
图4至图11例示本发明影像感测元件封装构件的制作方法。
主要元件符号说明
1影像感测元件封装构件
1a影像感测元件封装构件
10影像感测晶粒
10a主动面
10b背面
11影像感测元件区域
12外接垫
13直通硅晶穿孔结构
14第一绝缘层
15第一重布线路层
15a连接垫
15b防电磁干扰金属图案
16第二绝缘层
16a开孔
17第二重布线路层
17a焊接垫
18防焊层
18a开孔
18b假开孔
19焊接锡球
20封装用光学盖板
22支撑堰体结构
24凹穴结构
100影像感测晶片
100a主动面
100b背面
具体实施方式
本发明运用创新的连结技术,贯穿硅晶层直接连结至影像感测晶粒的外接垫;小巧的尺寸与连结的位置,让封装背面可支援高密度的球栅阵列封装介面,使后续的封装相容于表面粘着组装制作工艺。本发明可以相容于晶片级封装(wafer-levelpackaging,简称为WLP)制作工艺并且采用直通硅晶穿孔技术,其中所谓的晶片级封装制作工艺系在晶片状态时就封装晶粒,再进行后段组装制作工艺,然后,晶片再进行切割,成为独立封装晶粒。
请参阅图1,其为依据本发明一较佳实施例所绘示的影像感测元件封装构件的剖面示意图。如图1所示,影像感测元件封装构件1包含有一影像感测晶粒10,其具有一主动面10a以及相对于主动面(activeside)10a的一背面(backside)10b,且在主动面10a上设有一影像感测元件区域11以及外接垫12。影像感测元件区域11可以是CMOS影像感测元件,但不限于此。
在影像感测晶粒10的主动面10a上另覆盖一封装用光学盖板20,例如,透镜等级玻璃或石英,而在封装用光学盖板20与影像感测晶粒10的主动面10a之间另设有支撑堰体结构22,例如,环氧树脂(epoxyresin)、聚亚酰胺(polyimide)、光致抗蚀剂或防焊阻剂(solderresist)材料等等,如此使光学盖板20、支撑堰体结构22与影像感测晶粒10的主动面10a之间构成一密闭的凹穴结构24,而影像感测元件区域11就是位于凹穴结构24内部。此外,支撑堰体结构22与影像感测晶粒10的主动面10a之间可以利用接合材料(图未示)进行粘合。
根据本发明的较佳实施例,影像感测元件封装构件1另包含有一直通硅晶穿孔(TSV)结构13,其贯穿影像感测晶粒10,并连通影像感测晶粒10的主动面10a与背面10b,用来曝露出位于影像感测晶粒10的主动面10a上部分的外接垫12。在影像感测晶粒10的背面10b以及硅晶穿孔结构13的侧壁上则顺应的形成有第一绝缘层14,例如,氧化硅、氮化硅或氮氧化硅等等。此外,第一绝缘层14也可以采用有机高分子绝缘材料。
在第一绝缘层14上形成有一第一重布线路层15,例如,铝金属线路图案或者铜金属线路图案。第一重布线路层15顺应的覆盖在硅晶穿孔结构13的侧壁上以及底部,并且与外接垫12电连接。此外,第一重布线路层15至少包含有一连接垫15a。在第一重布线路层15以及第一绝缘层14上另有一第二绝缘层16,例如,氧化硅、氮化硅或氮氧化硅等等。第二绝缘层16也可以采用有机高分子绝缘材料。在第二绝缘层16中设有至少一开孔16a,曝露出部分的连接垫15a。
在第二绝缘层16上形成有一第二重布线路层17,例如,钛、铜、镍、金、铝或上述金属之组合。第二重布线路层17可以是由可焊接(soldable)金属材料所构成者。第二重布线路层17与第一重布线路层15可以采用相同的导电材料或者不同的导电材料,也可以是不同的厚度。第二重布线路层17填入开孔16a,并与曝露出的连接垫15a电连接。第二重布线路层17至少包含有一焊接垫(solderpad)17a。在第二重布线路层17以及第二绝缘层16上另有一防焊层18,例如,环氧树脂、聚亚酰胺、光致抗蚀剂等等。在防焊层18中设有至少一开孔18a,曝露出部分的焊接垫17a。在焊接垫17a上则设有焊接锡球19。
请参阅图2,其为依据本发明另一较佳实施例所绘示的影像感测元件封装构件的剖面示意图。如图2所示,影像感测元件封装构件1a同样包含有一影像感测晶粒10,其具有一主动面10a以及相对于主动面10a的一背面10b,且在主动面10a上设有一影像感测元件区域11以及外接垫12。
同样的,影像感测元件封装构件1a包含有一直通硅晶穿孔结构13,其贯穿影像感测晶粒10,并连通影像感测晶粒10的主动面10a与背面10b,用来曝露出位于影像感测晶粒10的主动面10a上部分的外接垫12。在影像感测晶粒10的背面10b以及硅晶穿孔结构13的侧壁上则顺应的形成有第一绝缘层14,例如,氧化硅、氮化硅或氮氧化硅等等。第一绝缘层14也可以采用有机高分子绝缘材料。
根据本发明的另一较佳实施例,在第一绝缘层14上形成有一第一重布线路层15,例如,铝金属线路图案或者铜金属线路图案。第一重布线路层15顺应的覆盖在硅晶穿孔结构13的侧壁上以及底部,并且与外接垫12电连接。此外,第一重布线路层15至少包含有一连接垫15a以及一防电磁干扰金属图案15b。在第一重布线路层15以及第一绝缘层14上另有一第二绝缘层16,例如,氧化硅、氮化硅或氮氧化硅等等。在第二绝缘层16设有至少一开孔16a,曝露出部分的连接垫15a。
在第二绝缘层16上形成有一第二重布线路层17,例如,钛、铜、镍、金、铝或上述金属的组合。第二重布线路层17填入开孔16a,并与曝露出的连接垫15a电连接。第二重布线路层17至少包含有一焊接垫17a。在第二重布线路层17以及第二绝缘层16上另有一防焊层18,例如,环氧树脂、聚亚酰胺、光致抗蚀剂等等。在防焊层18设有至少一开孔18a,曝露出部分的焊接垫17a。在焊接垫17a上则设有焊接锡球19。此外,在防焊层18设有多个假开孔(dummyopenings)18b,其中,假开孔18b可以是圆形、矩形、长条形、锯齿形或不规则形状。
图2中的影像感测元件封装构件1a与图1中的影像感测元件封装构件1的差别在于:1)图2中的影像感测元件封装构件1a具有一防电磁干扰金属图案15b,可以保护影像感测晶粒10免受电磁干扰;以及2)图2中的影像感测元件封装构件1a在防焊层18设有多个假开孔18b,可以释放形成在影像感测晶粒10的背面10b上的绝缘层所产生的应力,也可以用来作为破裂停止(crackstop)机制。
请参阅图3,其为依据本发明又另一较佳实施例所绘示的影像感测元件封装构件的剖面示意图。如图3所示,同样的,在第二重布线路层17以及第二绝缘层16上设有一防焊层18,例如,环氧树脂、聚亚酰胺、光致抗蚀剂等等。在防焊层18设有至少一开孔18a,曝露出部分的焊接垫17a。在焊接垫17a上则设有焊接锡球19。在防焊层18设有多个假开孔18b,其中,假开孔18b可以填入绝缘材料,以释放影像感测晶粒10的背面10b上的应力。
图4至图11例示制作如图1中的影像感测元件封装构件1的方法。首先,如图4所示,提供一影像感测晶片100,其具有一主动面100a以及相对于主动面100a的一背面100b,且在主动面100a上设有至少一影像感测元件区域11以及外接垫12。影像感测元件区域11可以是CMOS影像感测元件,但不限于此。
在影像感测晶片100的主动面100a上另覆盖一封装用光学盖板20,例如,透镜等级玻璃或石英,而在封装用光学盖板20与影像感测晶片100的主动面100a之间另设有支撑堰体结构22,例如,环氧树脂、聚亚酰胺、光致抗蚀剂或防焊阻剂材料等等,如此使光学盖板20、支撑堰体结构22与影像感测晶片100的主动面100a之间构成一密闭的凹穴结构24,而影像感测元件区域11就是位于凹穴结构24内部。此外,支撑堰体结构22与影像感测晶片100的主动面100a之间可以利用接合材料(图未示)进行粘合。接着,将影像感测晶片100的背面100b研磨掉一预定厚度。
如图5所示,在完成晶片晶背研磨制作工艺之后,接着利用光刻及蚀刻制作工艺,从影像感测晶片100的背面100b蚀刻出直通硅晶穿孔(TSV)结构13,其贯穿影像感测晶片100,并连通影像感测晶片100的主动面100a与背面100b,用来曝露出位于主动面100a上部分的外接垫12。
如图6所示,在影像感测晶片100的背面100b以及硅晶穿孔结构13的侧壁上顺应的形成一第一绝缘层14,例如,氧化硅、氮化硅或氮氧化硅等等。第一绝缘层14也可以采用有机高分子绝缘材料。然后再利用光刻及蚀刻制作工艺,在硅晶穿孔结构13的底部上的第一绝缘层14中形成一开口14a,曝露出部分的外接垫12。
如图7所示,接下来,在第一绝缘层14上形成一第一重布线路层15,例如,铝金属线路图案或者铜金属线路图案。第一重布线路层15顺应的覆盖在硅晶穿孔结构13的侧壁上以及底部,并且与外接垫12电连接。此外,第一重布线路层15至少包含有一连接垫15a。
如图8所示,接着,在第一重布线路层15以及第一绝缘层14上形成一第二绝缘层16,例如,氧化硅、氮化硅或氮氧化硅等等。第二绝缘层16也可以采用有机高分子绝缘材料。然后再利用光刻及蚀刻制作工艺,在第二绝缘层16形成至少一开孔16a,曝露出部分的连接垫15a。
如图9所示,接下来,在第二绝缘层16上形成一第二重布线路层17,例如,钛、铜、镍、金、铝或上述金属之组合。第二重布线路层17也可以是由可焊接金属材料所构成者。第二重布线路层17与第一重布线路层15可以采用相同的导电材料或者不同的导电材料,也可以是不同的厚度。第二重布线路层17填入开孔16a,并与曝露出的连接垫15a电连接。第二重布线路层17至少包含有一焊接垫17a。
如图10及图11所示,在第二重布线路层17以及第二绝缘层16上形成一防焊层18,例如,环氧树脂、聚亚酰胺、光致抗蚀剂等等。然后在防焊层18中形成至少一开孔18a,曝露出部分的焊接垫17a。然后,在开孔18a内的焊接垫17a上形成一焊接锡球19。最后,进行晶片切割制作工艺,形成如图1中的影像感测元件封装构件1。熟悉该项技术人士应能理解图4至图11中双层的重布线路层的制作方法仅为示意,本发明并不限于双层的重布线路层,熟悉该项技术人士更可以利用所揭露的方法步骤形成多层的重布线路层。
本发明的主要技术特征至少包括:1)采晶片级封装制作工艺结合直通硅晶穿孔技术,并在影像感测晶粒的背面形成多层重布线路,故在设计上允许更多数量的输出输入(I/O)接点,以及具备更弹性的线路布局与成本上优势;2)在第一重布线路层中可以形成防电磁干扰金属图案,可以保护影像感测晶粒免受电磁干扰;以及3)在防焊层可以设有多个假开孔,用来释放绝缘层所产生的应力,也可以用来作为破裂停止机制。
以上所述仅为本发明的较佳实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (6)
1.一种影像感测元件封装构件,包含有:
影像感测晶粒,其具有主动面以及相对于该主动面的背面,且在该主动面上设有影像感测元件区域以及外接垫;
直通硅晶穿孔结构,贯穿该影像感测晶粒,连接该外接垫;
多层重布线路,形成在该像感测晶粒的该背面上;以及
防焊层,其覆盖在该多层重布线路上,其中在该防焊层中设有多个假开孔,用来释放应力。
2.如权利要求1所述的影像感测元件封装构件,其中在该影像感测晶粒的该主动面上另覆盖一封装用光学盖板。
3.如权利要求2所述的影像感测元件封装构件,其中在该封装用光学盖板与该影像感测晶粒的该主动面之间另设有一支撑堰体结构。
4.如权利要求1所述的影像感测元件封装构件,其中在该防焊层中设有至少一开孔,曝露出一焊接垫,并在该焊接垫上设有一焊接锡球。
5.如权利要求1所述的影像感测元件封装构件,其中在该多个假开孔内填入一绝缘材料。
6.如权利要求1所述的影像感测元件封装构件,其中该多层重布线路至少包含有一防电磁干扰金属图案。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US31540510P | 2010-03-19 | 2010-03-19 | |
US61/315,405 | 2010-03-19 | ||
CN201110067998.3A CN102194781B (zh) | 2010-03-19 | 2011-03-21 | 影像感测元件封装构件及其制作方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110067998.3A Division CN102194781B (zh) | 2010-03-19 | 2011-03-21 | 影像感测元件封装构件及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105047629A true CN105047629A (zh) | 2015-11-11 |
CN105047629B CN105047629B (zh) | 2018-03-06 |
Family
ID=44602594
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110067998.3A Expired - Fee Related CN102194781B (zh) | 2010-03-19 | 2011-03-21 | 影像感测元件封装构件及其制作方法 |
CN201510390848.4A Active CN105047629B (zh) | 2010-03-19 | 2011-03-21 | 影像感测元件封装构件 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110067998.3A Expired - Fee Related CN102194781B (zh) | 2010-03-19 | 2011-03-21 | 影像感测元件封装构件及其制作方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8536672B2 (zh) |
CN (2) | CN102194781B (zh) |
TW (1) | TWI508273B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105655320A (zh) * | 2016-01-11 | 2016-06-08 | 华天科技(昆山)电子有限公司 | 低成本芯片背部硅通孔互连结构及其制备方法 |
CN107146795A (zh) * | 2016-03-01 | 2017-09-08 | 精材科技股份有限公司 | 晶片封装体及其制造方法 |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8314498B2 (en) * | 2010-09-10 | 2012-11-20 | Aptina Imaging Corporation | Isolated bond pad with conductive via interconnect |
CN102544040B (zh) * | 2012-01-17 | 2014-06-25 | 中国科学院上海微系统与信息技术研究所 | 利用TSV技术实现GaAs图像传感器的圆片级封装方法 |
TWI497645B (zh) * | 2012-08-03 | 2015-08-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9196642B2 (en) * | 2012-09-10 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress release layout and associated methods and devices |
KR102018885B1 (ko) | 2012-12-20 | 2019-09-05 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
TWI560825B (en) * | 2013-02-08 | 2016-12-01 | Xintec Inc | Chip scale package structure and manufacturing method thereof |
US8937009B2 (en) | 2013-04-25 | 2015-01-20 | International Business Machines Corporation | Far back end of the line metallization method and structures |
JP6299406B2 (ja) * | 2013-12-19 | 2018-03-28 | ソニー株式会社 | 半導体装置、半導体装置の製造方法、及び電子機器 |
US9679936B2 (en) * | 2014-02-27 | 2017-06-13 | Semiconductor Components Industries, Llc | Imaging systems with through-oxide via connections |
CN103956334B (zh) * | 2014-05-07 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | 集成电路中rdl和tsv金属层一次成型方法 |
TWI603447B (zh) * | 2014-12-30 | 2017-10-21 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
TWI591764B (zh) * | 2015-01-12 | 2017-07-11 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
KR20160090972A (ko) | 2015-01-22 | 2016-08-02 | 에스케이하이닉스 주식회사 | 이미지 센서 패키지 및 제조 방법 |
MA41414A (fr) | 2015-01-28 | 2017-12-05 | Centre Nat Rech Scient | Protéines de liaison agonistes d' icos |
US10217783B2 (en) | 2015-04-08 | 2019-02-26 | Semiconductor Components Industries, Llc | Methods for forming image sensors with integrated bond pad structures |
US9818776B2 (en) | 2015-04-08 | 2017-11-14 | Semiconductor Components Industries, Llc | Integrating bond pad structures with light shielding structures on an image sensor |
CN109742064B (zh) * | 2015-04-27 | 2021-06-11 | 精材科技股份有限公司 | 晶片封装体及其制造方法 |
TWI624039B (zh) * | 2015-05-28 | 2018-05-11 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
US10043761B2 (en) * | 2015-10-19 | 2018-08-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
KR102508551B1 (ko) * | 2015-12-11 | 2023-03-13 | 에스케이하이닉스 주식회사 | 웨이퍼 레벨 패키지 및 제조 방법 |
US9837360B2 (en) * | 2015-12-11 | 2017-12-05 | SK Hynix Inc. | Wafer level packages and electronics system including the same |
US9941230B2 (en) * | 2015-12-30 | 2018-04-10 | International Business Machines Corporation | Electrical connecting structure between a substrate and a semiconductor chip |
US9773829B2 (en) * | 2016-02-03 | 2017-09-26 | Omnivision Technologies, Inc. | Through-semiconductor-via capping layer as etch stop layer |
US10209466B2 (en) | 2016-04-02 | 2019-02-19 | Intel IP Corporation | Integrated circuit packages including an optical redistribution layer |
TWI672779B (zh) * | 2016-12-28 | 2019-09-21 | 曦威科技股份有限公司 | 指紋辨識裝置、使用其之行動裝置以及指紋辨識裝置的製造方法 |
KR101973445B1 (ko) | 2017-11-07 | 2019-04-29 | 삼성전기주식회사 | 팬-아웃 센서 패키지 및 카메라 모듈 |
KR102486561B1 (ko) | 2017-12-06 | 2023-01-10 | 삼성전자주식회사 | 재배선의 형성 방법 및 이를 이용하는 반도체 소자의 제조 방법 |
AU2020279254A1 (en) | 2019-05-21 | 2021-01-14 | Illumina, Inc. | Sensors having an active surface |
KR20210047062A (ko) * | 2019-10-21 | 2021-04-29 | 삼성전자주식회사 | 인터포저 및 그 제조방법 |
US12050398B2 (en) * | 2020-05-19 | 2024-07-30 | Micron Technology, Inc. | Semiconductor device and method of forming the same |
KR20220021238A (ko) * | 2020-08-13 | 2022-02-22 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
KR20220102900A (ko) | 2021-01-14 | 2022-07-21 | 삼성전자주식회사 | 반도체 칩 및 이를 포함하는 반도체 패키지 |
CN116779690A (zh) * | 2023-06-20 | 2023-09-19 | 东莞链芯半导体科技有限公司 | 传感器的封装结构及封装方法 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010035930A1 (en) * | 2000-03-31 | 2001-11-01 | Yun Sai Chang | Tape carrier package with dummy bending part and liquid crystal display employing the same |
TW504817B (en) * | 2001-11-20 | 2002-10-01 | Taiwan Semiconductor Mfg | Method and structure to improve mold resin adhesion |
CN1945818A (zh) * | 2006-10-17 | 2007-04-11 | 晶方半导体科技(苏州)有限公司 | 双层引线封装结构及其制造方法 |
TW200719446A (en) * | 2005-11-02 | 2007-05-16 | Siliconware Precision Industries Co Ltd | Semiconductor package and substrate structure thereof |
JP2007134735A (ja) * | 2000-07-11 | 2007-05-31 | Seiko Epson Corp | 光素子及びその製造方法並びに電子機器 |
US20070215985A1 (en) * | 2006-03-20 | 2007-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Novel chip packaging structure for improving reliability |
US20080099900A1 (en) * | 2006-10-31 | 2008-05-01 | Tessera Technologies Hungary Kft. | Wafer-level fabrication of lidded chips with electrodeposited dielectric coating |
CN101369591A (zh) * | 2007-08-17 | 2009-02-18 | 精材科技股份有限公司 | 影像感测元件封装体及其制作方法 |
CN101431867A (zh) * | 2007-11-05 | 2009-05-13 | 松下电器产业株式会社 | 安装结构体 |
US20090289317A1 (en) * | 2008-05-26 | 2009-11-26 | Guoping Yu | Packaging structure and method for fabricating the same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3465617B2 (ja) * | 1999-02-15 | 2003-11-10 | カシオ計算機株式会社 | 半導体装置 |
US6166444A (en) * | 1999-06-21 | 2000-12-26 | United Microelectronics Corp. | Cascade-type chip module |
US7061106B2 (en) * | 2004-04-28 | 2006-06-13 | Advanced Chip Engineering Technology Inc. | Structure of image sensor module and a method for manufacturing of wafer level package |
US7419852B2 (en) * | 2004-08-27 | 2008-09-02 | Micron Technology, Inc. | Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies |
US7566650B2 (en) * | 2005-09-23 | 2009-07-28 | Stats Chippac Ltd. | Integrated circuit solder bumping system |
TW200924175A (en) * | 2007-11-20 | 2009-06-01 | Advanced Semiconductor Eng | Optical sensor chip package process and structure thereof |
US20090166873A1 (en) * | 2007-12-27 | 2009-07-02 | Advanced Chip Engineering Technology Inc. | Inter-connecting structure for semiconductor device package and method of the same |
CN101587903B (zh) * | 2008-05-23 | 2011-07-27 | 精材科技股份有限公司 | 电子元件封装体及其制作方法 |
-
2011
- 2011-03-18 US US13/050,949 patent/US8536672B2/en active Active
- 2011-03-18 TW TW100109413A patent/TWI508273B/zh active
- 2011-03-21 CN CN201110067998.3A patent/CN102194781B/zh not_active Expired - Fee Related
- 2011-03-21 CN CN201510390848.4A patent/CN105047629B/zh active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010035930A1 (en) * | 2000-03-31 | 2001-11-01 | Yun Sai Chang | Tape carrier package with dummy bending part and liquid crystal display employing the same |
JP2007134735A (ja) * | 2000-07-11 | 2007-05-31 | Seiko Epson Corp | 光素子及びその製造方法並びに電子機器 |
TW504817B (en) * | 2001-11-20 | 2002-10-01 | Taiwan Semiconductor Mfg | Method and structure to improve mold resin adhesion |
TW200719446A (en) * | 2005-11-02 | 2007-05-16 | Siliconware Precision Industries Co Ltd | Semiconductor package and substrate structure thereof |
US20070215985A1 (en) * | 2006-03-20 | 2007-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Novel chip packaging structure for improving reliability |
CN1945818A (zh) * | 2006-10-17 | 2007-04-11 | 晶方半导体科技(苏州)有限公司 | 双层引线封装结构及其制造方法 |
US20080099900A1 (en) * | 2006-10-31 | 2008-05-01 | Tessera Technologies Hungary Kft. | Wafer-level fabrication of lidded chips with electrodeposited dielectric coating |
CN101369591A (zh) * | 2007-08-17 | 2009-02-18 | 精材科技股份有限公司 | 影像感测元件封装体及其制作方法 |
CN101431867A (zh) * | 2007-11-05 | 2009-05-13 | 松下电器产业株式会社 | 安装结构体 |
US20090289317A1 (en) * | 2008-05-26 | 2009-11-26 | Guoping Yu | Packaging structure and method for fabricating the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105655320A (zh) * | 2016-01-11 | 2016-06-08 | 华天科技(昆山)电子有限公司 | 低成本芯片背部硅通孔互连结构及其制备方法 |
CN105655320B (zh) * | 2016-01-11 | 2019-08-02 | 华天科技(昆山)电子有限公司 | 低成本芯片背部硅通孔互连结构及其制备方法 |
CN107146795A (zh) * | 2016-03-01 | 2017-09-08 | 精材科技股份有限公司 | 晶片封装体及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US8536672B2 (en) | 2013-09-17 |
TW201143074A (en) | 2011-12-01 |
CN102194781B (zh) | 2015-11-04 |
CN102194781A (zh) | 2011-09-21 |
TWI508273B (zh) | 2015-11-11 |
CN105047629B (zh) | 2018-03-06 |
US20110227186A1 (en) | 2011-09-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102194781B (zh) | 影像感测元件封装构件及其制作方法 | |
CN105280599B (zh) | 用于半导体器件的接触焊盘 | |
US8633091B2 (en) | Chip package and fabrication method thereof | |
KR100629498B1 (ko) | 마이크로 패키지, 멀티―스택 마이크로 패키지 및 이들의제조방법 | |
US8502393B2 (en) | Chip package and method for forming the same | |
TWI459483B (zh) | Manufacturing method of semiconductor device | |
US8766408B2 (en) | Semiconductor device and manufacturing method thereof | |
KR101429344B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
TWI529892B (zh) | 晶片封裝體及其製造方法 | |
US20090127682A1 (en) | Chip package structure and method of fabricating the same | |
US8476738B2 (en) | Electronic package with stacked semiconductor chips | |
US10340198B2 (en) | Semiconductor package with embedded supporter and method for fabricating the same | |
JP2009044110A (ja) | 半導体装置及びその製造方法 | |
US11139233B2 (en) | Cavity wall structure for semiconductor packaging | |
CN104495741A (zh) | 表面传感芯片封装结构及制作方法 | |
US20070170556A1 (en) | Semiconductor device having flange structure | |
CN103151274A (zh) | 半导体元件及其制造方法 | |
CN211929479U (zh) | 半导体器件 | |
US20230387059A1 (en) | Semiconductor device and method of fabricating the same | |
US11955439B2 (en) | Semiconductor package with redistribution structure and manufacturing method thereof | |
KR101605610B1 (ko) | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 | |
JP2005303039A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2003273154A (ja) | 半導体装置及びその製造方法 | |
CN211480029U (zh) | 一种图像传感器 | |
KR20010073946A (ko) | 딤플 방식의 측면 패드가 구비된 반도체 소자 및 그제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |