TWI459483B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
TWI459483B
TWI459483B TW097144917A TW97144917A TWI459483B TW I459483 B TWI459483 B TW I459483B TW 097144917 A TW097144917 A TW 097144917A TW 97144917 A TW97144917 A TW 97144917A TW I459483 B TWI459483 B TW I459483B
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TW
Taiwan
Prior art keywords
semiconductor
wiring
circuit
wafer
pad
Prior art date
Application number
TW097144917A
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English (en)
Other versions
TW200937545A (en
Inventor
Niichi Ito
Tetsuji Nakamura
Takamitsu Nagaosa
Hisashi Okamura
Original Assignee
Renesas Electronics Corp
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Publication date
Priority to JP2008042695A priority Critical patent/JP5342154B2/ja
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW200937545A publication Critical patent/TW200937545A/zh
Application granted granted Critical
Publication of TWI459483B publication Critical patent/TWI459483B/zh

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5286Arrangements of power or ground buses
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    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Description

半導體裝置之製造方法

本發明係關於一種半導體裝置之製造技術及半導體裝置,尤其係關於一種適用於形成與半導體晶片中之外部電性連接構造之有效技術。

於構築球柵陣列構造之LSI時,可考慮採用BGA(Ball Grid Array)型、使用再配線構造之CSP、或者凸塊電極構造之形態。

BGA型中,需要作為封裝之線結合,而再配線構造中,需要於半導體晶片之鈍化膜上進行再配線。上述封裝、再配線係連接於LSI晶片之IO區域中所設之焊墊。

與此相對,凸塊電極構造係於LSI晶片內之最上層金屬配線層中,進行向構成凸塊電極之焊錫球之連接,因此電源配線及GND配線不經由IO單元而直接連接於下層配線層,成為不具有焊墊之構造。

因此,如上所述,BGA型及再配線構造與凸塊電極構造之布局構造不同,因此當考慮於同一LSI中使上述兩種封裝形態混合存在時,必須分別另行製作用以於最上層配線上開口之專用遮罩。

於日本專利特開2003-273154號公報(專利文獻1)中揭示有一種技術,即,於半導體晶片區域之主動元件面之四角附近,形成具備線結合用焊墊區域及再配線用焊墊區域兩者之金屬配線層,進而利用鈍化膜覆蓋於該金屬配線層上,再對應於半導體晶片之安裝形態,而選擇性地去除線結合用焊墊區域、或再配線用焊墊區域中任一者上之鈍化膜而進行開口。藉此,不會使成本上升,並且不會使半導體裝置之尺寸增大,使得半導體晶片既可對應於帶有導線終端之封裝,又可對應於CSP(Chip Size Package,晶片尺寸封裝)。

日本專利特開平11-87400號公報(專利文獻2)揭示有一種技術,即,於用以將半導體晶片上所形成之積體電路電性連接於外部之焊墊部中,藉由對覆蓋焊墊部之保護膜進行選擇性開口而形成2個連接部,從而於線結合及凸塊連接中之任一種形態下均能與外部電性連接,藉此構造以提高半導體裝置之開發效率及量產效率。

[專利文獻1]

日本專利特開2003-273154號公報

[專利文獻2]

日本專利特開平11-87400號公報

然而,上述專利文獻1所揭示之技術係以再配線構造作為前提者。並且,通常之再配線構造係連接於與IO單元相連接之焊墊。因此,上述專利文獻1之情形,係必須準備與線結合用焊墊之數量相對應之再配線用焊墊區域。因此,當半導體晶片中所需之線結合用焊墊之數量增加時,再配線用焊墊區域以及形成於再配線上之凸塊電極之數量會相應地增加與此相同之數量。由此會產生半導體晶片(以下簡寫作晶片)之小型化受到阻礙之問題。

又,於上述專利文獻2中揭示之技術之情形時,若設為藉由凸塊電極來進行之安裝形態,則由於線結合用連接部係予以開口而成為一直露出之狀態,因而有可能會產生線結合用連接部之腐蝕等。又,若設為藉由線結合進行之安裝形態時,由於亦形成有凸塊電極,因而有可能會導致引線與凸塊電極短路。

又,本發明之另一目之在於提供一種可將半導體裝置小型化之技術。

本發明之上述以及其他目的與新穎之特徵,當應可根據本說明書之敍述及附圖而明瞭。

對本案所揭示之發明中之代表性發明之概要進行簡單說明如下。

(1)本發明之半導體裝置之製造方法包括以下步驟:(a)於藉由分割區域而劃分成複數個晶片區域之半導體基板上,於上述複數個晶片區域之各區域中形成積體電路;(b)於上述複數個晶片區域之各區域內,於上述積體電路之上層形成第1配線,該第1配線自第1電路區域延伸至第2電路區域,並與上述積體電路電性連接;(c)將上述第1電路區域之上述第1配線之一部分規定為第1焊墊,將上述第2電路區域之上述第1配線之一部分規定為第2焊墊;(d)於上述第1配線之存在下,於上述半導體基板上形成保護膜;(e)於上述第1焊墊上或上述第2焊墊上之上述保護膜上形成開口部;(f)沿著上述分割區域切斷上述半導體基板,分割成各個半導體晶片;(g)將上述半導體晶片分別安裝至安裝基板上,並經由接合線或凸塊電極而將上述半導體晶片分別與上述安裝基板電性連接;且,

當於上述(g)步驟中經由上述接合線而將上述半導體晶片分別與上述安裝基板電性連接時,於上述(e)步驟中上述開口部係形成於上述第1焊墊上之上述保護膜上,而於上述(g)步驟中於上述開口部下將上述接合線連接於上述第1焊墊,

當於上述(g)步驟中經由上述凸塊電極而將上述半導體晶片分別與上述安裝基板電性連接時,於上述(e)步驟中上述開口部係形成於上述第2焊墊上之上述保護膜上,進而於上述第2焊墊上形成上述凸塊電極,該凸塊電極於上述開口部下與上述第2焊墊連接。

(2)本發明之半導體裝置包括:半導體晶片,其主面上形成有積體電路,且被規定有第1電路區域及第2電路區域,上述第1電路區域沿著半導體晶片之外週而配置有複數個,且包含輸入輸出電路,上述第2電路區域配置於上述第1電路區域間;以及

凸塊電極,其形成於上述第2電路區域上,且與上述積體電路電性連接。

(3)本發明之半導體裝置係於上述(2)之半導體裝置中,規定有比上述第1電路區域及上述第2電路區域更靠近上述半導體晶片中心之第3電路區域,

上述第2電路區域及上述凸塊電極進而配置於上述第1電路區域與上述第3電路區域之間,

上述凸塊電極配置成,上述凸塊電極中,上述第1電路區域間之上述第2電路區域上之1個或相鄰之2個上述凸塊電極,以及上述第1電路區域與上述第3電路區域之間之上述第2電路區域上之1個或相鄰之2個上述凸塊電極成為正三角形之各頂點。

對藉由本案所揭示之發明中之代表性發明所獲得之效果進行簡單說明如下。(1)於利用線結合而安裝之晶片與利用凸塊電極而安裝之晶片中可將製造步驟共用化。(2)可將半導體裝置小型化。

於以下之實施形態中,有時為方便起見而分為複數個部分或實施形態進行說明,但除了特別明示之情形以外,該些部分或實施形態並非彼此無關,而是存在一方係另一方之部分或全部變形例、詳細、補充說明等之關係。

又,於以下之實施形態中,當言及要素之數等(包括個數、數值、量、範圍等)時,除了特別明示之情形以及原理上明確限定於特定數之情形等以外,並不限定於該特定數,既可為特定數以上亦可為特定數以下。

進而,於以下之實施形態中,其構成要素(亦包括要素步驟等)當然未必為必須,除了特別明示之情形以及於原理上明確認為係必須之情形等以外。又,於實施例等中,對於構成要素等,在說"由A組成"、"由A構成"時,除了特別明示僅該要素之情形等以外,當然並不排除該要素A以外之要素。

同樣地,於以下之實施形態中,當言及構成要素等之形狀、位置關係等時,除了特別明示之情形以及於原理上明確認為並非如此之情形等以外,包括實質上近似或類似於該形狀等之要素。此對於上述數值及範圍亦同樣適用。

又,於言及材料等時,除了特別明確記載並非如此時或者於原理上或狀況上並非如此時以外,特定之材料係主要之材料,並不排除次要之要素、添加物、附加要素等。例如,就矽構件而言,除了特別明示之情形等以外,不僅表示純淨之矽之情形,亦包括以添加雜質、矽為主要要素之二元、三元等之合金(例如SiGe)等。

又,於用以說明本實施形態之所有圖中,對於具有相同功能之要素原則上標註相同之符號,並省略其重複說明。

又,於本實施形態中所用之圖式中,即使為平面圖,有時為使圖式容易觀察,亦局部地標註有陰影。

以下,根據圖式詳細說明本發明之實施形態。

(實施形態1)本實施形態1之半導體裝置例如係BGA型之半導體裝置,圖1係對本實施形態1之半導體裝置中所含之晶片1之布局進行說明之平面圖。又,圖2係將圖1中之區域A1放大表示之主要部分平面圖,圖3及圖4表示沿著圖2中之A-A線之剖面,圖5及圖6表示沿著圖2中之B-B線之剖面,圖7及圖8表示沿著圖2中之C-C線之剖面,圖9及圖10表示沿著圖2中之D-D線之剖面。又,圖3及圖4表示了外部連接用電極(凸塊電極或者接合線連接用之接合墊)與信號用配線之連接狀態,圖5~圖10表示了外部連接用電極與電源‧GND(基準電位)用配線之連接狀態,圖3~圖10中之粗線箭頭表示電流路徑。圖11表示於圖1中之區域A2上所形成之配線之布局(平面)。

如圖1至圖11所示,於晶片1中,例如於由單晶矽構成之半導體基板2之主面上設有MISFET(Metal Insulator Semiconductor Field Effect Transistor,金屬絕緣體半導體場效電晶體)等半導體元件3以及與該半導體元件3電性連接之配線4~7等。配線4~6係藉由於例如由氧化矽等構成之層間絕緣膜8~10上所形成之配線形成用槽中埋入銅或銅合金而形成。又,對於形成於配線4之上層之配線5以及形成於配線5之上層之配線6所形成之槽,於底部設有與下層之配線進行連接用之孔,對該些槽及孔一併埋入銅或銅合金,從而成為與下層之配線進行連接用之插塞與配線一體形成之構造。再者,於形成有配線4~6之槽及孔之側壁及底面上,為防止形成配線4~6之銅向層間絕緣膜8~10等之擴散,而形成有鈦、氮化鈦、鉭或氮化鉭等之單層膜或該些單層膜之積層膜以作為阻障絕緣膜,但於圖3至圖10中省略了圖示。最上層之配線(第1配線)7例如係將鋁膜或鋁合金膜作為主導電層之配線,係藉由利用蝕刻對成膜於半導體基板2上之鋁膜或鋁合金膜進行圖案化而形成。於配線7上,例如形成有氧化矽等之絕緣膜(保護膜)11以及由氮化矽膜等之絕緣膜構成之表面保護膜(保護膜)12。又,本實施形態1中,作為保護膜而例示了氧化矽膜與氮化矽膜之積層膜,但並不限定於此,例如亦可為僅由氮化矽膜12等單層之絕緣膜而形成。

又,上述絕緣膜11及絕緣膜12之一部分被開口,成為上述配線7所露出之區域。

上述配線7之一部分成為自上述開口部露出之區域。該配線7所露出之區域係用以成為凸塊電極13所連接之凸塊連接部(第2焊墊)15、接合線14所連接之接合墊(第1焊墊)16及檢查用探針所接觸之測試用焊墊17之區域,其平面形狀與配線7之其他區域相比形成為寬幅。

最上層之配線7,於沿著晶片1之外週而配置之輸入輸出電路形成區域(第1電路區域)AIO中進行與下層之配線4、5、6之電性連接,並自輸入輸出電路形成區域AIO相對地向晶片1之平面內側之區域(第2電路區域)延伸。又,接合墊16及測試用焊墊17於平面上配置於該輸入輸出電路形成區域AIO中。

如圖3及圖4所示,成為信號用配線之配線7於輸入輸出電路形成區域AIO中與下層之配線4、5、6電性連接,並經由形成於輸入輸出電路形成區域AIO中之輸入輸出電路(包括半導體元件3)及配線4,而與形成於晶片1內部之邏輯(數位系)電路電性連接。

如圖5及圖6所示,成為與電源電位或基準電位電性連接之電源‧GND用配線之配線7於輸入輸出電路形成區域AIO中與下層之配線4、5、6電性連接,並經由配線4而進行對形成於晶片1內部之邏輯電路之供電。成為電源‧GND用配線之配線7所電性連接之電源‧GND用配線4、5、6成為下述構造,即:於相同之配線層中,複數條配線沿著相同之方向而延伸,而1個上層或下層之同電位之複數條配線沿著於平面上交叉之方向延伸(以下稱作網格構造)。圖5及圖6中,圖示了配線7於輸入輸出電路形成區域AIO中與1個下層之配線6相連接之示例,但除了輸入輸出電路形成區域AIO以外,於除此以外之部位亦可為配線7與配線6相連接之構造。

如圖7至圖11所示,於本實施形態1中,成為電源‧GND用配線之配線7呈狹縫構造,藉由與下層之配線6相連接而形成圖11所示之網格配線。再者,可明確的是,例如若設為將第1配線層作為電源配線、將第2配線層作為GND配線之構成,則即使為單一之配線層亦可構成網格配線。於輸入輸出電路形成區域AIO以外之區域(例如區域A2)中,亦於複數個部位連接於下層之配線6。於該區域(第2電路區域)A2中,於配線7之下層之配線層(第2配線層)中所形成之配線(第3配線)4、5、6亦呈網格構造。

如此,藉由將成為電源‧GND用配線之配線4、5、6、7設為網格構造,並設為於複數個部位與上層及下層之配線相連接之構造,從而可進行穩定之供電。又,於區域A2內之呈網格構造之配線7上,亦可設置凸塊連接部(第3焊墊)15,進而形成連接之凸塊電極13。

如圖2至圖10所示,於本實施形態1中,於晶片1藉由凸塊電極13來進行與外部之電性連接之情形,以及於晶片1藉由接合線14來進行與外部之電性連接之情形時,均於1條配線7上形成有凸塊連接部15及接合墊16這兩者。但並非於所有配線7上設有凸塊連接部15及接合墊16,亦存在未設有凸塊連接部15之接合墊16。

當晶片1藉由凸塊電極13進行與外部之電性連接時,於形成凸塊電極13之位置上之絕緣膜11以及表面保護膜12上形成抵達凸塊連接部15之開口部18,使接合墊16及測試用焊墊17為仍由絕緣膜11及表面保護膜12所覆蓋之狀態。之所以於形成凸塊電極13時使接合墊16及測試用焊墊17上為仍由絕緣膜11及表面保護膜12所覆蓋之狀態,係為防止因成為凸塊電極13之焊錫之回焊熱而導致接合墊16及測試用焊墊17熔融。

另一方面,當晶片1藉由接合線14進行與外部之電性連接時,於接合墊16及測試用焊墊17上之絕緣膜11以及表面保護膜12上形成分別抵達接合墊16及測試用焊墊17之開口部19、20,使凸塊連接部15上為仍由絕緣膜11及表面保護膜12所覆蓋之狀態。之所以於形成接合線14時使凸塊連接部15上為仍由絕緣膜11及表面保護膜12所覆蓋之狀態,係為防止自凸塊連接部15開始發生腐蝕。

再者,圖3、圖5、圖7及圖9中,圖示有實際上未形成之開口部19、20各自之開口位置19A、20A,圖4、圖6、圖8及圖10中亦圖示有實際上未形成之開口部18之開口位置18A。

如上所述,根據本實施形態1,於晶片1藉由凸塊電極13進行與外部之電性連接之情形以及晶片1藉由接合線14進行與外部之電性連接之情形時,直至形成最上層之配線7為止之晶片1可設為相同之布局。藉此,於晶片1藉由凸塊電極13進行與外部之電性連接之情形以及晶片1藉由接合線14進行與外部之電性連接之情形時,直至形成最上層之配線7為止,可使用相同之遮罩進行圖案形成,從而可將步驟共用化。其結果,可提高本實施形態1之半導體裝置之量產性,降低製造成本。

開口部18、19、20之布局驗證可藉由下述方式實施,即,於開口部18與開口部19、20中設為不同之層(亦可設為資料類型之切換),並製作分別相適合之布局驗證規則。再者,開口部18、19、20之布局驗證亦可藉由於使用接合線之情形與使用凸塊電極之情形時具有不同之上述開口部之資料類型或者層,從而使設計者於相同之規則檔案中分開使用開口部18、19、20之布局驗證規則,以選擇並使用上述層。

又,開口部18、19、20用之遮罩製作,係使用支援遮罩製作之資料檔案即MPD(Mask Pattern Data Specification,遮罩圖案資料規範),於使用凸塊電極13之情形時指定開口部18之層,於使用接合線14之情形時指定開口部19、20之層,從而分別製作專用之遮罩。藉由設為如此之晶圓位準下之處理方式,從而於使用凸塊電極13之情形以及使用接合線14之情形時可分開製作晶片1。

再者,關於開口部18、19、20之圖案轉印步驟,亦可不製作遮罩,而採用藉由電子束之直描方式。藉此,可削減遮罩製造所耗之成本。又,對於比配線7更下層之配線圖案,亦可採用藉由電子束之直描方式。

其次,對於本實施形態1之晶片1之製造步驟,使用圖12至圖15進行說明。如前所述,於使用凸塊電極13之情形以及使用接合線14之情形時,形成配線7為止之步驟均相同。

首先,如圖12所示,於形成有形成積體電路之半導體元件3以及配線4~6之半導體基板2上,堆積例如氧化矽膜而形成層間絕緣膜10A。

繼而,將藉由光微影技術進行了圖案化之光阻劑膜作為遮罩而對層間絕緣膜10A進行蝕刻,形成抵達配線6之接觸孔。

繼而,於包含該接觸孔內之層間絕緣膜10A上,堆積較薄之鈦膜或氮化鈦膜之單層膜,或者堆積該些單層膜之積層膜而形成阻障導電膜之後,於層間絕緣膜10A上堆積鎢膜,利用該鎢膜埋入接觸孔。繼而,將接觸孔外之阻障導電膜及鎢膜去除,藉此形成與配線6相連接之插塞7A。

其次,如圖13所示,於半導體基板2上依次堆積鈦膜、鋁膜(或鋁合金膜)及氮化鈦膜之後,藉由將光阻劑膜作為遮罩之乾式蝕刻而對該些鈦膜、鋁膜(或鋁合金膜)及氮化鈦膜進行圖案化,形成配線7。如前所述,於該步驟中,形成以及規定凸塊連接部15、接合墊16及測試用焊墊17。

繼而,於半導體基板1上依次堆積氧化矽膜及氮化矽膜,形成絕緣膜11及表面保護膜12。

以後之步驟於使用凸塊電極13之情形與使用接合線14之情形時不同。

於使用凸塊電極13之情形時,如圖14所示,將藉由光微影技術進行了圖案化之光阻劑膜作為遮罩而對表面保護膜12及絕緣膜11進行蝕刻,形成抵達配線7之開口部18。繼而,例如藉由非電解鍍敷法而於開口部18下之配線7上使金膜等導電性膜成膜,形成凸塊電極用基底膜13A。

其次,形成凸塊電極13。作為凸塊電極13之製造步驟,例如,藉由焊錫印刷技術將焊錫膏印刷至半導體基板2上之後,藉由回焊處理使焊錫膏熔融及再結晶化,於凸塊電極用基底膜13A上形成凸塊電極13(參照圖3、圖5、圖7及圖9)。作為該焊錫膏,例如可使用由錫、銀及銅所形成之無鉛焊錫。又,取代焊錫膏之使用,而將預先成形為球狀之焊錫球供給至開口部18上之後,對半導體基板2實施回焊處理,藉由亦可形成凸塊電極13。

隨後,沿著所劃分之晶片區域間之劃線(切割)區域切斷晶圓狀態之半導體基板2,分割成各個晶片1。所分割之晶片1可經由凸塊電極13而安裝至安裝基板上。於將晶片1配置於安裝基板上之後,對凸塊電極13進行回焊,繼而於晶片1與安裝基板之間填充底部填充樹脂,從而製造本實施形態1之半導體裝置。

於使用接合線14之情形時,如圖15所示,將藉由光微影技術進行了圖案化之光阻劑膜作為遮罩而對表面保護膜12及絕緣膜11進行蝕刻,於輸入輸出電路形成區域AIO中形成抵達配線7之開口部19、20。

繼而,於測試用焊墊17處進行藉由探頭之晶圓測試。進行藉由探頭之測試時,可藉由使探頭之針直接接觸至測試用焊墊17而進行。若利用實際用以形成接合線14之接合墊16進行測試,則有可能會因探頭針之應力而導致於接合墊16下之層間絕緣膜上發生裂紋等問題之產生。因此,本實施形態1中,分別形成有探頭測試用之測試用焊墊17之區域與實際用以形成接合線14之接合墊16之區域。

其次,沿著所劃分之晶片區域間之劃線(切割)區域(分割區域)切斷晶圓狀態之半導體基板2,分割成各個晶片1。所分割之晶片1使用DAF(Die Attached Film,晶片附加薄膜)等而搭載至安裝基板(例如多層配線基板)上。繼而,利用接合線14將開口部19A下之接合墊16與安裝基板之電極連接之後(參照圖4、圖6、圖8及圖10),藉由鑄模樹脂將晶片1及接合線14密封。隨後,於特定位置切斷鑄模樹脂及安裝基板,從而製造本實施形態1之半導體裝置。

此處,圖16及圖17係晶片1中之凸塊連接部15(或凸塊電極13)、接合墊16及測試用焊墊17附近之主要部分平面圖,圖16表示使用接合線14之情形時之平面,圖17表示使用凸塊電極13之情形。如前所述,接合墊16及測試用焊墊17配置於輸入輸出電路形成區域AIO中,於接合墊16及測試用焊墊17下形成有包含輸入輸出電路之輸入輸出電路單元IOC。

如此,於至此為止之本實施形態1中,對分別配置接合墊16及測試用焊墊17之情形進行了說明,但亦可如圖18及圖19所示般,設為使接合墊16與測試用焊墊17一體形成之平面尺寸較大之構造,或者設為省略了測試用焊墊17自身之構造。

又,關於最上層之配線7,係以將鋁作為主成分之構成進行了說明,但應明確的是,即使為銅等其他材質亦可獲得同樣之效果。又,亦可僅最上層之配線7係由鋁形成,而比其更下層之配線層係由以銅為主體之配線層形成。若對於層間絕緣膜10上形成配線6之情形進行例示,則於形成層間絕緣膜10之後,形成連接於下層之配線5之孔,隨後形成構成配線6之配線槽。其次,於孔及槽內,形成由鉭或氮化鉭等之導電性膜構成之阻障金屬膜,於該阻障金屬膜上形成以銅為主成分之導電性膜(銅膜)。繼而,將槽外部之阻障金屬膜及銅膜藉由CMP法等而除去,藉此可於孔及槽內埋入阻障金屬膜及銅膜,從而形成配線6以及將配線6與配線5連接之連接部。

然而,於本實施形態1中,當將晶片1與外部之例如記憶體電路等其他晶片電性連接時,設為使用接合線14之構造,例如設為配置於區域A3(參照圖1)中之接合墊16(配線7)成為用以與記憶體電路電性連接之介面之構成。另一方面,當無須使晶片1與外部之記憶體電路電性連接時,設為使用凸塊電極13之構造,例如藉由將於區域A3中為與外部之記憶體電路電性連接而設置之配線7上之凸塊電極13之形成予以省略,從而可將晶片1之尺寸縮小化。因此,於成為用以與外部之記憶體電路電性連接之介面之區域A3中,例如接合墊16為51個,凸塊電極13為10個。即,於本實施形態1中,形成於晶片1上之接合墊16之數量比凸塊連接部15之數量多。

再者,當成為使用凸塊電極13之構成時,成為用以與記憶體電路電性連接之介面之區域A3之配線7成為開放端,但對於如此之配線7必須實施提昇(pull up)或壓低(pull down)等處理,從而將其設計成,即使成為開放端亦不會妨礙形成於晶片1內之邏輯電路之動作。

圖20至圖23表示將本實施形態1之晶片1作為無線系統之控制器而安裝至模組基板21上時之示例,圖20及圖21分別係使用了上述接合線14時之平面圖及側面圖,圖22及圖23分別係使用了上述凸塊電極13時之平面圖及側面圖。於模組基板21上,除了晶片1以外,亦安裝著形成有進行高頻動作之RF(Radio Frequency,射頻)電路之RF晶片22以及旁路電容器晶片23等。旁路電容器晶片23為了電源穩定化而電性插入於電源線中。又,圖20至圖23中之箭頭表示各晶片間之信號之流動。

如前所述,當將使用了接合線14之晶片1安裝至模組基板21上時,形成有記憶體電路之記憶體晶片24亦可安裝至模組基板21上(參照圖20及圖21)。藉此,可搭載大量之韌件等程式,因而可提高整個無線系統之功能。

另一方面,當安裝有使用了凸塊電極13之晶片1時,由於成為不安裝記憶體晶片24之構成,因而能以最小構成來構築無線系統(參照圖22及圖23)。藉此,可將構築有該無線系統之模組之尺寸最小化,因此即使對於例如行動電話之類之模組安裝區域受到限定之機器,亦可適用無線系統。

(實施形態2)圖24係本實施形態2之晶片1之主要部分平面圖,圖示了相當於上述實施形態1中所示圖1中之區域A4之區域。

如圖24所示,於相對靠近晶片1之外週1A且沿著該外週1A之區域A4中,形成有輸入輸出電路單元IOC,於該輸入輸出電路單元IOC上,形成有上述實施形態1中亦有說明之接合墊16及測試用焊墊17。

如圖2所示,如上述實施形態1中亦有說明般,於1條配線7上亦形成有凸塊連接部15、接合墊16及測試用焊墊17。由於在輸入輸出電路單元IOC上形成有接合墊16及測試用焊墊17,因而將配線7引繞至凸塊電極13於平面上不會與輸入輸出電路單元IOC相重疊之區域,例如引繞至相對地晶片1之中心方向而配置凸塊連接部15。

此處,如圖24所示,於區域A4中,當可將輸入輸出電路單元IOC之配置布局設計成能夠確保可於鄰接之2個輸入輸出電路單元IOC間配置凸塊電極13之空間時,設為如此之輸入輸出電路單元IOC之配置布局,向輸入輸出電路單元IOC間之空間引繞配線7而配置凸塊連接部15及凸塊電極13。藉此,不再需要確保用於在相對地晶片1之中心方向上配置凸塊電極13之區域,因此可縮小晶片1之面積,實現晶片1之小型化。尤其當如此之區域A4靠近圖1所示之類比系電路區域A6時,可得到有效活用。其理由在於,類比系電路區域A6與形成有其他邏輯系電路之區域相比較,引入信號線或電源線之比例較少,因此輸入輸出電路單元IOC之數量較少即可。

再者,於如區域A3之類之其他區域中,當輸入輸出電路單元IOC之數量較少即可時,亦可於鄰接之2個輸入輸出電路單元IOC間配置凸塊電極13。

又,如圖25所示,為使輸入輸出電路單元IOC間之空間內所配置之凸塊電極13下得到有效活用,亦可於輸入輸出電路單元IOC間之空間內所配置之凸塊電極13下,形成例如通常之邏輯(數位系)電路,或包含靜電放電(Electrostatic Discharge,ESD)應對用二極體之保護電路。藉此,可於晶片1上搭載進一步之電路功能,或者進一步縮小晶片1之面積而使晶片1進一步小型化。

又,於相對靠近晶片1之外週1A且沿著該外週1A之區域A5(參照圖1)中,亦可按與上述之區域A4同樣之布局來配置輸入輸出電路單元IOC,向輸入輸出電路單元IOC間之空間引繞配線7而配置凸塊連接部15及凸塊電極13。

然而,於本實施形態2中,該區域A5係晶片1之外週1A與設計上無法配置凸塊電極13之區域(第3電路區域)A6之間之狹窄區域,進而係必須自晶片1之外週1A隔開特定距離T1以上而配置凸塊電極13之、於配置凸塊電極13時存在制約之區域。再者,該區域A6相對地比區域A5更位於晶片1之內側,例如形成有類比系電路。假設於類比系電路區域A6上形成配線7或凸塊電極13,則有可能會產生來自配線7之雜訊或寄生電容。類比系電路區域A6與其他邏輯電路相比,係對雜訊或寄生電容較敏感之區域,因此成為如上所述之制約特別嚴格之區域。

如圖26所示,當於如此之區域A5中,於與晶片1之外週1A正交之方向上以間距P1排列有配置於相對靠近晶片1之外週1A之位置上之凸塊電極13以及配置於相對靠近區域A6之位置上之凸塊電極13時,即使該間距P1與配置於相對靠近晶片1之外週1A之位置上之凸塊電極13之配置間距P2相同,配置於相對靠近區域A6之位置上之凸塊電極13亦有可能會進入無法配置凸塊電極13之區域A6中。

又,如圖27所示,當配置成,配置於相對靠近晶片1之外週1A之位置上之凸塊電極13之2個(或1個)以及配置於相對靠近區域A6之位置上之凸塊電極13之1個(或2個)成為二等邊三角形之頂點,以使得凸塊電極13不會與區域A6相重疊時,沿著晶片1之外週1A之方向上之凸塊電極13之配置間距P2會變得較寬,若欲配置所需數量之凸塊電極13,則有可能招致晶片1之大型化。再者,圖27中,將配置於相對靠近晶片1之外週1A之位置上之凸塊電極13與鄰接之配置於相對靠近區域A6之位置上之凸塊電極13之間的間距設為P1。

因此,本實施形態2中,如圖28所示配置成,配置於相對靠近晶片1之外週1A之位置上之凸塊電極13之2個(或1個)與配置於相對靠近區域A6之位置上之凸塊電極13之1個(或2個)成為正三角形之頂點。即配置成,以各凸塊電極13之中心為頂點,將各頂點連結而成之形狀成為正三角形。藉此,與圖27所示之成為二等邊三角形之頂點之凸塊電極13之配置方法相比,能夠以較小之區域配置所需數量之凸塊電極13。藉此可防止晶片1之尺寸變大,從而維持或縮小晶片1之尺寸。

以上,根據實施形態對由本發明者所研發之發明進行了具體說明,但本發明並不限定於上述實施形態,於不脫離其主旨之範圍內當可進行各種變更。

[產業上之可利用性]

本發明之半導體裝置之製造方法及半導體裝置可廣泛適用於具有經由接合線或凸塊電極來安裝晶片之構造之半導體裝置。

1...晶片

1A...外週

2...半導體基板

3...半導體元件

4~6...配線(第3配線)

7...配線(第1配線、第2配線)

7A...插塞

8~10、10A...層間絕緣膜

11...絕緣膜(保護膜)

12...表面保護膜(保護膜)

13...凸塊電極

13A...凸塊電極用基底膜

14...接合線

15...凸塊連接部(第2焊墊、第3焊墊)

16...接合墊(第1焊墊)

17...測試用焊墊

18...開口部

18A...開口位置

19...開口部

19A...開口位置

20...開口部

20A...開口位置

21...模組基板

22...RF晶片

23...旁路電容器晶片

24...記憶體晶片

A1...區域

A2...區域(第2電路區域)

A3...區域

A4...區域

A5...區域

A6...區域(第3電路區域)

AIO...輸入輸出電路形成區域(第1電路區域)

IOC...輸入輸出電路單元

LEC...電路單元

圖1係本發明之一實施形態之半導體裝置中所含之晶片之平面圖。

圖2係將圖1之一部分放大後之主要部分平面圖。

圖3係表示沿著圖2中之A-A線之剖面之主要部分剖面圖。

圖4係表示沿著圖2中之A-A線之剖面之主要部分剖面圖。

圖5係表示沿著圖2中之B-B線之剖面之主要部分剖面圖。

圖6係表示沿著圖2中之B-B線之剖面之主要部分剖面圖。

圖7係表示沿著圖2中之C-C線之剖面之主要部分剖面圖。

圖8係表示沿著圖2中之C-C線之剖面之主要部分剖面圖。

圖9係表示沿著圖2中之D-D線之剖面之主要部分剖面圖。

圖10係表示沿著圖2中之D-D線之剖面之主要部分剖面圖。

圖11係對本發明之一實施形態之半導體裝置中所含之晶片上所形成的電源‧GND用配線之圖案進行說明之主要部分平面圖。

圖12係對本發明之一實施形態之半導體裝置之製造步驟進行說明之主要部分剖面圖。

圖13係繼圖12之後的半導體裝置之製造步驟中之主要部分剖面圖。

圖14係繼圖13之後的半導體裝置之製造步驟中之主要部分剖面圖。

圖15係繼圖13之後的半導體裝置之製造步驟中之主要部分剖面圖。

圖16係本發明之一實施形態之半導體裝置中所含之晶片之主要部分平面圖。

圖17係本發明之一實施形態之半導體裝置中所含之晶片之主要部分平面圖。

圖18係本發明之一實施形態之半導體裝置中所含之晶片之主要部分平面圖。

圖19係本發明之一實施形態之半導體裝置中所含之晶片之主要部分平面圖。

圖20係本發明之一實施形態之半導體裝置之平面圖。

圖21係本發明之一實施形態之半導體裝置之側面圖。

圖22係本發明之一實施形態之半導體裝置之平面圖。

圖23係本發明之一實施形態之半導體裝置之側面圖。

圖24係本發明之其他實施形態之半導體裝置中所含之晶片之主要部分平面圖。

圖25係本發明之其他實施形態之半導體裝置中所含之晶片之主要部分平面圖。

圖26係與本發明之其他實施形態之半導體裝置中所含之晶片進行比較之晶片之主要部分平面圖。

圖27係與本發明之其他實施形態之半導體裝置中所含之晶片進行比較之晶片之主要部分平面圖。

圖28係本發明之其他實施形態之半導體裝置中所含之晶片之主要部分平面圖。

1...晶片

7...配線(第1配線、第2配線)

15...凸塊連接部(第2焊墊、第3焊墊)

16...接合墊(第1焊墊)

17...測試用焊墊

Claims (17)

  1. 一種半導體裝置之製造方法,其特徵在於包括以下步驟:(a)於藉由分割區域而劃分成複數個晶片區域之半導體基板上,於上述複數個晶片區域之各區域中形成積體電路;(b)於上述複數個晶片區域之各區域內,於上述積體電路之上層形成第1配線,該第1配線係自第1電路區域延伸至第2電路區域,並與上述積體電路電性連接;(c)將上述第1電路區域之上述第1配線之一部分規定為第1焊墊,且將上述第2電路區域之上述第1配線之一部分規定為第2焊墊;(d)於上述第1配線存在下,於上述半導體基板上形成保護膜;(e)於上述第1焊墊上或上述第2焊墊上之上述保護膜上形成開口部;(f)沿著上述分割區域切斷上述半導體基板而分割成各個半導體晶片;及(g)將上述半導體晶片安裝至安裝基板,並經由接合線或凸塊電極而將上述半導體晶片與上述安裝基板電性連接;且當上述(g)步驟中,經由上述接合線而將上述半導體晶片分別與上述安裝基板電性連接時,於上述(e)步驟中,上述開口部係形成於上述第1焊墊上之上述保護膜,且 上述第2焊墊上係為由上述保護膜所覆蓋之狀態,於上述(g)步驟中,於上述開口部下將上述接合線直接連接於上述第1焊墊;當上述(g)步驟中經由上述凸塊電極而將上述半導體晶片分別與上述安裝基板電性連接時,於上述(e)步驟中,上述開口部係形成於上述第2焊墊上之上述保護膜,且上述第1焊墊上係為由上述保護膜所覆蓋之狀態,進而於上述第2焊墊上直接形成有上述凸塊電極,該凸塊電極係於上述開口部下與上述第2焊墊連接。
  2. 如請求項1之半導體裝置之製造方法,其中上述第1配線係與電源電位或基準電位電性連接;上述半導體晶片係經由上述凸塊電極而與上述安裝基板電性連接;且上述(b)步驟中,於形成有上述第1配線之第1配線層中,係形成複數條第2配線,該複數條第2配線係與上述第1配線電性連接且相互平行地延伸者;於上述(c)步驟中,將上述第2配線之一部分規定為第3焊墊;上述(e)步驟中,於上述第3焊墊上之上述保護膜形成上述開口部,進而於上述第3焊墊上直接形成上述凸塊電極,該凸塊電極係於上述開口部下與上述第3焊墊連接。
  3. 如請求項2之半導體裝置之製造方法,其中上述(a)步驟中,於比上述第1配線層更下層之第2配線層形成複數條 第3配線,該複數條第3配線係與上述第1配線及上述第2配線電性連接且相互平行地延伸者;上述複數條第2配線及上述複數條第3配線,係形成於包含上述半導體晶片之中央之上述第2電路區域。
  4. 如請求項1之半導體裝置之製造方法,其中上述半導體晶片係經由上述凸塊電極而與上述安裝基板電性連接;於上述半導體晶片內,將上述第2電路區域配置於上述第1電路區域與第3電路區域之間,該第1電路區域係相對地靠近上述半導體晶片之外週,該第3電路區域比上述第1電路區域及上述第2電路區域更處於上述半導體晶片之內側。
  5. 如請求項1之半導體裝置之製造方法,其中上述半導體晶片係經由上述凸塊電極而與上述安裝基板電性連接;將包含輸入輸出電路之上述第1電路區域沿著上述半導體晶片之外週而配置複數個;將上述第2電路區域配置於上述第1電路區域間。
  6. 如請求項5之半導體裝置之製造方法,其中於上述凸塊電極下之上述第2電路區域形成第1電路,該第1電路係包含數位系統電路或ESD應對用半導體元件。
  7. 如請求項5之半導體裝置之製造方法,其中將上述第2電路區域配置於上述第1電路區域,與比上述第1電路區域及上述第2電路區域更靠近上述半導體晶片中心之第3電路區域之間;將上述凸塊電極配置成在上述凸塊電極中,上述第1 電路區域間之上述第2電路區域上的1個或相鄰之2個上述凸塊電極,以及上述第1電路區域與上述第3電路區域間之上述第2電路區域上的1個或相鄰之2個上述凸塊電極成為正三角形之各頂點。
  8. 如請求項1之半導體裝置之製造方法,其中上述第1焊墊之數量係比上述第2焊墊之數量多。
  9. 如請求項8之半導體裝置之製造方法,其中於上述(b)步驟中,形成複數條上述第1配線;上述複數條上述第1配線之一部分,係成為與記憶體晶片之間之介面;當於上述安裝基板安裝上述記憶體晶片時,於上述(g)步驟中,係經由上述接合線而將上述半導體晶片與上述安裝基板電性連接,並將上述介面與上述記憶體晶片電性連接;當未於上述安裝基板安裝上述記憶體晶片時,於上述(g)步驟中,經由上述凸塊電極而將上述半導體晶片與上述安裝基板電性連接,於上述(c)步驟中,不對上述介面規定上述第2焊墊,且於上述(e)步驟中不形成與上述介面連接之上述凸塊電極。
  10. 如請求項1之半導體裝置之製造方法,其中於經由上述接合線而將上述半導體晶片與上述安裝基板電性連接時,以及經由上述凸塊電極而將上述半導體晶片與上述安裝基板電性連接時,上述第1電路區域、上述第2電路區域、上述積體電路及上述第1配線係以相同之布局而 形成。
  11. 一種半導體裝置之製造方法,其特徵在於包括以下步驟:(a)於半導體基板上形成第1配線;(b)於上述第1配線上形成第1絕緣膜;及(c)於上述第1絕緣膜上形成開口部,使上述第1配線之一部分露出;其中於上述(a)步驟中,於上述第1配線形成有用以供接合線直接連接之複數個第1區域,以及用以供凸塊電極直接形成之複數個第2區域;於上述(c)步驟中,當對於上述半導體裝置使用上述接合線時,上述開口部係分別形成於上述複數個第1區域,且不形成於上述複數個第2區域;於上述(c)步驟中,當對於上述半導體裝置使用上述凸塊電極時,上述開口部係分別形成於上述複數個第2區域,且不形成於上述複數個第1區域。
  12. 如請求項11之半導體裝置之製造方法,其中上述複數個第1區域之數量係比上述複數個第2區域之數量多。
  13. 如請求項11之半導體裝置之製造方法,其中於上述複數個第1區域之下,係分別形成有輸入輸出電路用單元。
  14. 如請求項13之半導體裝置之製造方法,其中上述複數個第2區域中之一部分,係形成於鄰接之輸入輸出電路用單元之間。
  15. 如請求項14之半導體裝置之製造方法,其中於形成在上 述鄰接之輸入輸出電路用單元間的上述第2區域下之上述半導體基板,係形成有數位系統電路或ESD應對用半導體元件。
  16. 如請求項1至15中任一項之半導體裝置之製造方法,其中上述凸塊電極包括凸塊電極用基底膜、及形成於上述凸塊電極用基底膜上之焊錫膏。
  17. 如請求項16之半導體裝置之製造方法,其中上述凸塊電極用基底膜包括金;上述焊錫膏包括錫、銀及銅。
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