CN101521169B - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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CN101521169B
CN101521169B CN2008101865713A CN200810186571A CN101521169B CN 101521169 B CN101521169 B CN 101521169B CN 2008101865713 A CN2008101865713 A CN 2008101865713A CN 200810186571 A CN200810186571 A CN 200810186571A CN 101521169 B CN101521169 B CN 101521169B
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China
Prior art keywords
circuit region
semiconductor
salient pole
distribution
weld pad
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CN2008101865713A
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English (en)
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CN101521169A (zh
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伊藤仁一
中村哲治
永长贵光
冈村尚
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瑞萨电子株式会社
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Priority to JP2008042695 priority Critical
Priority to JP2008-042695 priority
Priority to JP2008042695A priority patent/JP5342154B2/ja
Application filed by 瑞萨电子株式会社 filed Critical 瑞萨电子株式会社
Publication of CN101521169A publication Critical patent/CN101521169A/zh
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Abstract

本发明提供一种在利用引线接合进行安装的芯片和利用凸块电极进行安装的芯片中能够将制造步骤共用化的技术。不管是在芯片(1)通过凸块电极来进行与外部的电性连接的情况下,还是在芯片(1)通过接合线来进行与外部的电性连接的情况下,均在1条最上层的配线(7)上设置凸块连接部(15)及接合垫(16)这两者。在使用凸块电极的情况下,在凸块连接部(15)上的绝缘膜上设置开口部,并用绝缘膜覆盖接合垫(16)上。另一方面,在使用接合线的情况下,在接合垫(16)上的绝缘膜设置开口部,并用绝缘膜覆盖凸块连接部(15)上。

Description

半导体装置的制造方法及半导体装置

技术领域

[0001] 本发明涉及一种半导体装置的制造技术及半导体装置,尤其涉及一种适用于形成与半导体芯片外部的电性连接构造的有效技术。

背景技术

[0002] 在构筑球栅阵列构造的LSI时,可考虑采用BGA(Ball Grid Array)型、使用再配线构造的CSP、或者凸块电极构造的形态。

[0003] BGA型中,需要作为封装的引线接合,而再配线构造中,需要在半导体芯片的钝化膜上进行再配线。所述的封装、再配线连接于LSI芯片的IO区域中所设的焊垫。

[0004] 与此相对,凸块电极构造是在LSI芯片内的最上层金属配线层中,进行向构成凸块电极的焊锡球的连接,所以电源配线及GND配线不经由IO单元而是直接连接于下层配线层,成为不具有焊垫的构造。

[0005] 因此,如上所述,BGA型及再配线构造与凸块电极构造的布局构造不同,所以当考虑在同一 LSI中使上述两种封装形态混合存在时,必须分别另行制作用于在最上层配线上开口的专用遮罩。

[0006] 在日本专利特开2003-273154号公报(专利文献I)中揭示了一种技术,在半导体芯片区域的主动元件面的四角附近,形成具备引线接合用焊垫区域及再配线用焊垫区域这两者的金属配线层,进而用钝化膜覆盖在该金属配线层上,再对应于半导体芯片的安装形态而选择性地去除引线接合用焊垫区域或再配线用焊垫区域中任一者上的钝化膜而进行开口。由此,不会使成本上升,而且不会使半导体装置的尺寸增大,使得半导体芯片既能对应于带有导线终端的封装,又能对应于CSP (Chip Size Package,芯片尺寸封装)。

[0007]日本专利特开平11-87400号公报(专利文献2)揭示了一种技术,在用于将半导体芯片上所形成的集成电路电性连接于外部的焊垫部中,通过对覆盖焊垫部的保护膜进行选择性开口而形成2个连接部,从而在引线接合及凸块连接中的任一种形态下均能与外部电性连接,通过设为此种构造,米提高半导体装置的开发效率及量产效率。

[0008][专利文献I]

[0009] 日本专利特开2003-273154号公报

[0010][专利文献2]

[0011] 日本专利特开平11-87400号公报

[0012] 然而,所述专利文献I所揭示的技术是以再配线构造作为前提的。并且,通常的再配线构造是连接于与IO单元相连接的焊垫。因此,所述专利文献I的情况下,必须准备与引线接合用焊垫的数量相对应的再配线用焊垫区域。因此,当半导体芯片中所需的引线接合用焊垫的数量增加时,再配线用焊垫区域以及形成于再配线上的凸块电极的数量会相应地增加与此相同的数量。由此会产生半导体芯片(以下简写作芯片)的小型化受到阻碍的问题。

[0013] 而且,在所述专利文献2中揭示的技术的情况下,如果设为利用凸块电极的安装形态,则由于引线接合用连接部被开口而成为一直露出之状态,因而引线接合用连接部有可能会产生腐蚀等。而且,如果设为利用引线接合的安装形态,则因为也形成有凸块电极,因而有可能会导致引线与凸块电极短路。

发明内容

[0014] 而且,本发明的另一目的在于提供一种能将半导体装置小型化的技术。

[0015] 本发明的所述以及其他目的与新颖的特征当应可根据本说明书的叙述及附图而明确。

[0016] 对本案所揭示的发明中的代表性发明的概要进行简单说明如下。

[0017] (I)本发明的半导体装置的制造方法包括以下步骤:

[0018] (a)在通过分割区域而划分成多个芯片区域的半导体基板上,在所述多个芯片区域的各区域中形成集成电路;(b)在所述多个芯片区域的各区域内,在所述集成电路的上层形成第I配线,该第I配线从第I电路区域延伸到第2电路区域,并与所述集成电路电性连接;(c)将所述第I电路区域的所述第I配线的一部分规定为第I焊垫,将所述第2电路区域的所述第I配线的一部分规定为第2焊垫;(d)在所述第I配线的存在下,于所述半导体基板上形成保护膜;(e)在所述第I焊垫上的所述保护膜上或所述第2焊垫上的所述保护膜上形成开口部;(f)沿着所述分割区域切断所述半导体基板,而分割成各个半导体芯片;(g)将所述半导体芯片分别安装到安装基板上,并经由接合线或凸块电极而将所述半导体芯片分别与所述安装基板电性连接;且,

[0019] 当在所述(g)步骤中经由所述接合线而将所述半导体芯片分别与所述安装基板电性连接时,在所述(e)步骤中所述开口部是形成于所述第I焊垫上的所述保护膜上,而在所述(g)步骤中于所述开口部下将所述接合线连接于所述第I焊垫,

[0020] 当在所述(g)步骤中经由所述凸块电极而将所述半导体芯片分别与所述安装基板电性连接时,在所述(e)步骤中所述开口部是形成于所述第2焊垫上的所述保护膜上,进而在所述第2焊垫上形成所述凸块电极,该凸块电极在所述开口部下与所述第2焊垫连接。

[0021] (2)本发明的半导体装置包括:

[0022] 半导体芯片,其主面上形成有集成电路,且被规定有第I电路区域及第2电路区域,所述第I电路区域沿着半导体芯片的外周而配置有多个,且包含输入输出电路,所述第2电路区域配置在所述第I电路区域间;以及

[0023] 凸块电极,其形成在所述第2电路区域上,且与所述集成电路电性连接。

[0024] (3)本发明的半导体装置是在所述(2)的半导体装置中,

[0025] 规定有比所述第I电路区域及所述第2电路区域更靠近所述半导体芯片中心的第3电路区域,

[0026] 所述第2电路区域及所述凸块电极进而配置在所述第I电路区域与所述第3电路区域之间,

[0027] 所述凸块电极配置成,所述凸块电极中,所述第I电路区域间的所述第2电路区域上的I个或相邻的2个所述凸块电极,和所述第I电路区域与所述第3电路区域之间的所述第2电路区域上的I个或相邻的2个所述凸块电极成为正三角形的各顶点。

[0028][发明效果][0029] 对通过本案所揭示的发明中的代表性发明所获得的效果进行简单说明如下。(I)在利用引线接合而安装的芯片与利用凸块电极而安装的芯片中,能够将制造步骤共用化。

(2)能够将半导体装置小型化。

附图说明

[0030] 图1是本发明之一实施形态的半导体装置中所含的芯片的平面图。

[0031] 图2是将图1的一部分放大后的主要部分平面图。

[0032] 图3是表示沿着图2中的A-A线的剖面的主要部分剖面图。

[0033] 图4是表示沿着图2中的A-A线的剖面的主要部分剖面图。

[0034] 图5是表示沿着图2中的B-B线的剖面的主要部分剖面图。

[0035] 图6是表示沿着图2中的B-B线的剖面的主要部分剖面图。

[0036] 图7是表示沿着图2中的C-C线的剖面的主要部分剖面图。

[0037] 图8是表示沿着图2中的C-C线的剖面的主要部分剖面图。

[0038] 图9是表示沿着图2中的D-D线的剖面的主要部分剖面图。

[0039] 图10是表示沿着图2中的D-D线的剖面的主要部分剖面图。

[0040] 图11是对本发明之一实施形态的半导体装置中所含的芯片上所形成的电源*GND用配线的图案进行说明的主要部分平面图。

[0041] 图12是对本发明之一实施形态的半导体装置的制造步骤进行说明的主要部分剖面图。

[0042] 图13是紧跟着图12的半导体装置的制造步骤中的主要部分剖面图。

[0043] 图14是紧跟着图13的半导体装置的制造步骤中的主要部分剖面图。

[0044] 图15是紧跟着图13的半导体装置的制造步骤中的主要部分剖面图。

[0045] 图16是本发明之一实施形态的半导体装置中所含的芯片的主要部分平面图。

[0046] 图17是本发明之一实施形态的半导体装置中所含的芯片的主要部分平面图。

[0047] 图18是本发明之一实施形态的半导体装置中所含的芯片的主要部分平面图。

[0048] 图19是本发明之一实施形态的半导体装置中所含的芯片的主要部分平面图。

[0049] 图20是本发明之一实施形态的半导体装置的平面图。

[0050] 图21是本发明之一实施形态的半导体装置的侧面图。

[0051] 图22是本发明之一实施形态的半导体装置的平面图。

[0052] 图23是本发明之一实施形态的半导体装置的侧面图。

[0053] 图24是本发明的其他实施形态的半导体装置中所含的芯片的主要部分平面图。

[0054] 图25是本发明的其他实施形态的半导体装置中所含的芯片的主要部分平面图。

[0055] 图26是与本发明的其他实施形态的半导体装置中所含的芯片进行比较的芯片的主要部分平面图。

[0056] 图27是与本发明的其他实施形态的半导体装置中所含的芯片进行比较的芯片的主要部分平面图。

[0057] 图28是本发明的其他实施形态的半导体装置中所含的芯片的主要部分平面图。

[0058][符号的说明]

[0059] I 芯片[0060] IA 外周

[0061] 2 半导体基板

[0062] 3 半导体元件

[0063] 4〜6 配线(第3配线)

[0064] 7 配线(第I配线、第2配线)

[0065] 7A 插塞

[0066] 8〜10、IOA层间绝缘膜

[0067] 11 绝缘膜(保护膜)

[0068] 12 表面保护膜(保护膜)

[0069] 13 凸块电极

[0070] 13A 凸块电极用基底膜

[0071] 14 接合线

[0072] 15 凸块连接部(第2焊垫、第3焊垫)

[0073] 16 接合垫(第I焊垫)

[0074] 17 测试用焊垫

[0075] 18 开口部

[0076] 18A 开口位置

[0077] 19 开口部

[0078] 19A 开口位置

[0079] 20 开口部

[0080] 20A 开口位置

[0081] 21 模组基板

[0082] 22 RF 芯片

[0083] 23 旁路电容器芯片

[0084] 24 存储器芯片

[0085] Al 区域

[0086] A2 区域(第2电路区域)

[0087] A3 区域

[0088] A4 区域

[0089] A5 区域

[0090] A6 区域(第3电路区域)

[0091] AIO 输入输出电路形成区域(第I电路区域)

[0092] IOC 输入输出电路单元

[0093] LEC 电路单元

具体实施方式

[0094] 在以下的实施形态中,有时为了方便起见而分成多个部分或实施形态进行说明,但除了特别明示的情况以外,这些部分或实施形态并非彼此无关,而是存在一方是另一方的部分或全部变形例、详细、补充说明等的关系。[0095] 而且,在以下的实施形态中,当言及要素的数等(包括个数、数值、量、范围等)时,除了特别明示的情况以及原理上明确限定于特定数的情况等以外,并不限定于该特定数,既可以是特定数以上也可以是特定数以下。

[0096] 进而,在以下的实施形态中,其构成要素(也包括要素步骤等)当然未必是必需的,除了特别明示的情况以及在原理上明确认为是必须的情况等以外。而且,在实施例等中,对于构成要素等,在说“由A组成”、“由A构成”时,除了特别明示仅该要素的情况等以夕卜,当然并不排除该要素A以外的要素。

[0097] 同样地,在以下的实施形态中,当言及构成要素等的形状、位置关系等时,除了特别明示的情况以及在原理上明确认为并非如此的情况等以外,包括实质上近似或类似于该形状等的要素。这对于所述数值及范围也同样适用。

[0098] 而且,在言及材料等时,除了特别明确记载并非如此时或者在原理上或状况上并非如此时以外,特定的材料是主要的材料,并不排除次要的要素、添加物、附加要素等。例如,就硅构件而言,除了特别明示的情况等以外,不仅表示纯净的硅的情况,还包括以添加杂质、硅为主要要素的二元、三元等的合金(例如SiGe)等。

[0099] 而且,在用于说明本实施形态的所有图中,对于具有相同功能的要素原则上标注相同的符号,并省略其重复说明。

[0100] 而且,在本实施形态中所用的图式中,即使是平面图,有时为了使图式容易观察,也局部地标注了阴影。

[0101] 以下,根据图式来详细说明本发明的实施形态。

[0102](实施形态I)

[0103] 本实施形态I的半导体装置例如是BGA型的半导体装置,图1是对本实施形态I的半导体装置中所含的芯片I的布局进行说明的平面图。而且,图2是将图1中的区域Al放大表示的主要部分平面图,图3及图4表示沿着图2中的A-A线的剖面,图5及图6表示沿着图2中的B-B线的剖面,图7及图8表示沿着图2中的C-C线的剖面,图9及图10表示沿着图2中的D-D线的剖面。而且,图3及图4表示了外部连接用电极(凸块电极或者接合线连接用的接合垫)与信号用配线的连接状态,图5〜图10表示了外部连接用电极与电源*GND(基准电位)用配线的连接状态,图3〜图10中的粗线箭头表示了电流路径。图11表示了在图1中的区域A2上所形成的配线的布局(平向)。

[0104] 如图1至图11所示,在芯片I中,例如在由单晶硅构成的半导体基板2的主面上设有 MISFET (Metal Insulator Semiconductor Field Effect Transistor,金属绝缘体半导体场效应晶体管)等半导体元件3以及与该半导体元件3电性连接的配线4〜7等。配线4〜6是通过在例如由氧化硅等构成的层间绝缘膜8〜10上所形成的配线形成用槽中埋入铜或铜合金而形成。而且,对于形成在配线4的上层的配线5以及形成在配线5的上层的配线6所形成的槽,在底部设有与下层的配线进行连接用的孔,对这些槽及孔一并埋入铜或铜合金,从而成为与下层的配线进行连接用的插塞和配线一体形成的构造。另外,于形成有配线4〜6的槽及孔的侧壁及底面上,为了防止形成配线4〜6的铜向层间绝缘膜8〜10等的扩散,而形成有钛、氮化钛、钽或氮化钽等的单层膜或这些单层膜的层叠膜来作为阻障绝缘膜,但在图3至图10中省略了图示。最上层的配线(第I配线)7例如是将铝膜或铝合金膜作为主导电层的配线,是通过利用蚀刻对成膜于半导体基板2上的铝膜或铝合金膜进行图案化而形成的。在配线7上,例如形成有氧化硅等的绝缘膜(保护膜)11以及由氮化硅膜等的绝缘膜构成的表面保护膜(保护膜)12。而且,本实施形态I中,作为保护膜而例示了氧化硅膜与氮化硅膜的层叠膜,但并不限定于此,例如也可以是仅由氮化硅膜12等单层的绝缘膜而形成。

[0105] 而且,所述绝缘膜11及绝缘膜12的一部分被开口,成为所述的配线7所露出的区域。

[0106] 所述配线7的一部分成为从所述开口部露出的区域。该配线7所露出的区域是用来成为凸块电极13所连接的凸块连接部(第2焊垫)15、接合线14所连接的接合垫(第I焊垫)16及检查用探针所接触的测试用焊垫17的区域,其平面形状与配线7的其他区域相比形成为宽幅。

[0107] 最上层的配线7,在沿着芯片I的外周而配置的输入输出电路形成区域(第I电路区域)AIO中进行与下层的配线4、5、6的电性连接,并从输入输出电路形成区域AIO相对地向芯片I的平面内侧的区域(第2电路区域)延伸。而且,接合垫16及测试用焊垫17在平面上配置于该输入输出电路形成区域AIO中。

[0108] 如图3及图4所示,成为信号用配线的配线7在输入输出电路形成区域AIO中与下层的配线4、5、6电性连接,并经由形成于输入输出电路形成区域AIO中的输入输出电路(包括半导体元件3)及配线4,而与形成于芯片I内部的逻辑(数字)电路电性连接。

[0109] 如图5及图6所示,成为与电源电位或基准电位电性连接的电源*GND用配线的配线7在输入输出电路形成区域AIO中与下层的配线4、5、6电性连接,并经由配线4对形成于芯片I内部的逻辑电路进行供电。成为电源*GND用配线的配线7所电性连接的电源*GND用配线4、5、6如下构造,S卩:在相同的配线层中,多条配线沿着相同的方向延伸,而I个上层或下层的同电位的多条配线沿着在平面上交叉的方向延伸(以下称作网格构造)。图5及图6中,图示了配线7在输入输出电路形成区域AIO中与I个下层的配线6相连接的示例,但是除了输入输出电路形成区域AIO以外,在除此以外的部位也可以是配线7与配线6相连接的构造。

[0110] 如图7至图11所示,在本实施形态I中,成为电源*GND用配线的配线7呈狭缝构造,通过与下层的配线6相连接而形成图11所示的网格配线。另外可以明确的是,例如若将第I配线层作为电源配线,将第2配线层作为GND配线的构成,则即使是单一的配线层也能够构成网格配线。在输入输出电路形成区域AIO以外的区域(例如区域A2)中,也在多个部位连接于下层的配线6。在该区域(第2电路区域)A2中,于配线7的下层的配线层(第2配线层)中所形成的配线(第3配线)4、5、6也呈网格构造。

[0111] 这样,通过将成为电源.GND用配线的配线4、5、6、7设为网格构造,并设为在多个部位与上层及下层的配线相连接的构造,从而能够进行稳定的供电。而且,在区域A2内的呈网格构造的配线7上,也可以设置凸块连接部(第3焊垫)15,进而形成连接的凸块电极13。

[0112] 如图2至图10所示,于本实施形态I中,不管是在芯片I通过凸块电极13来进行与外部的电性连接的情况下,还是在芯片I通过接合线14来进行与外部的电性连接的情况下,均在I条配线7上形成有凸块连接部15及接合垫16这两者。但是,并不是在所有的配线7上都设有凸块连接部15及接合垫16,也存在未设有凸块连接部15的接合垫16。[0113] 当芯片I通过凸块电极13来进行与外部的电性连接时,在形成凸块电极13的位置上的绝缘膜11以及表面保护膜12上形成抵达凸块连接部15的开口部18,使接合垫16及测试用焊垫17为仍由绝缘膜11及表面保护膜12所覆盖的状态。之所以在形成凸块电极13时使接合垫16及测试用焊垫17上为仍由绝缘膜11及表面保护膜12所覆盖的状态,是为了防止因成为凸块电极13的焊锡的回焊热而导致接合垫16及测试用焊垫17熔融。

[0114] 另一方面,当芯片I通过接合线14来进行与外部的电性连接时,在接合垫16及测试用焊垫17上的绝缘膜11以及表面保护膜12上形成分别抵达接合垫16及测试用焊垫17的开口部19、20,使凸块连接部15上为仍由绝缘膜11及表面保护膜12所覆盖的状态。之所以在形成接合线14时使凸块连接部15上为仍由绝缘膜11及表面保护膜12所覆盖的状态,是为了防止从凸块连接部15开始发生腐蚀。

[0115] 另外,图3、图5、图7及图9中,图示了实际上未形成的开口部19、20各自的开口位置19A、20A,图4、图6、图8及图10中也图示了实际上未形成的开口部18的开口位置18A。

[0116] 如上所述,根据本实施形态I,在芯片I通过凸块电极13来进行与外部的电性连接的情况和芯片I通过接合线14来进行与外部的电性连接的情况下,直至形成最上层的配线7为止的芯片I可设为相同的布局。由此,在芯片I通过凸块电极13来进行与外部的电性连接的情况和芯片I通过接合线14来进行与外部的电性连接的情况下,直至形成最上层的配线7为止,可以使用相同的遮罩来进行图案形成,从而可将步骤共用化。其结果,能够提高本实施形态I的半导体装置的量产性,降低制造成本。

[0117] 开口部18、19、20的布局验证可以通过以下方式来实施,即,在开口部18与开口部19,20中设为不同的层(也可以设为数据类型的切换),并制作分别相适合的布局验证规贝U。另外,开口部18、19、20的布局验证也可以通过让使用接合线的情况和使用凸块电极的情况下具有不同的所述开口部的数据类型或者层,从而使设计者在相同的规则文件中分开使用开口部18、19、20的布局验证规则,来选择并使用所述层。

[0118] 而且,开口部18、19、20用的遮罩制作,是使用支持遮罩制作的数据文件即MPD(Mask Pattern Data Specification,遮罩图案数据规范),在使用凸块电极13的情况下指定开口部18的层,在使用接合线14的情况下指定开口部19、20的层,从而分别制作专用的遮罩。通过设为这样的晶片等级下的处理方式,从而在使用凸块电极13的情况和使用接合线14的情况下能够分开制作芯片I。

[0119] 另外,关于开口部18、19、20的图案转印步骤,也可以不制作遮罩,而是采用电子束直描方式。由此,可以削减遮罩制造所耗的成本。而且,对于比配线7更下层的配线图案,也可以采用电子束直描方式。

[0120] 其次,对于本实施形态I的芯片I的制造步骤,使用图12至图15进行说明。如前所述,在使用凸块电极13的情况和使用接合线14的情况下,形成配线7为止的步骤均相同。

[0121] 首先,如图12所示,在形成有形成集成电路的半导体元件3及配线4〜6的半导体基板2上,堆积例如氧化硅膜而形成层间绝缘膜10A。

[0122] 继而,将通过光刻技术进行了图案化的光阻剂膜作为遮罩来对层间绝缘膜IOA进行蚀刻,形成抵达配线6的接触孔。

[0123] 继而,在包含该接触孔内的层间绝缘膜IOA上,堆积较薄的钛膜或氮化钛膜的单层膜,或者堆积这些单层膜的层叠膜而形成阻障导电膜之后,在层间绝缘膜IOA上堆积钨膜,利用该钨膜埋入接触孔。继而,将接触孔外的阻障导电膜及钨膜去除,由此形成与配线6相连接的插塞7A。

[0124] 其次,如图13所示,在半导体基板2上依次堆积钛膜、铝膜(或铝合金膜)及氮化钛膜之后,通过将光阻剂膜作为遮罩的干式蚀刻来对这些钛膜、铝膜(或铝合金膜)及氮化钛膜进行图案化,形成配线7。如前所述,在该步骤中,形成以及规定凸块连接部15、接合垫16及测试用焊垫17。

[0125] 继而,在半导体基板I上依次堆积氧化硅膜及氮化硅膜,形成绝缘膜11及表面保护膜12。

[0126] 以后的步骤在使用凸块电极13的情况和使用接合线14的情况下不同。

[0127] 在使用凸块电极13的情况下,如图14所示,将通过光刻技术进行了图案化的光阻剂膜作为遮罩来对表面保护膜12及绝缘膜11进行蚀刻,形成抵达配线7的开口部18。继而,例如通过非电解镀敷法而在开口部18下的配线7上使金膜等导电性膜成膜,形成凸块电极用基底膜13A。

[0128] 其次,形成凸块电极13。作为凸块电极13的制造步骤,例如,通过焊锡印刷技术将焊锡膏印刷到半导体基板2上之后,通过回焊处理使焊锡膏熔融及再结晶化,在凸块电极用基底膜13A上形成凸块电极13 (参照图3、图5、图7及图9)。作为该焊锡膏,例如可使用由锡、银及铜所形成的无铅焊锡。而且,取代焊锡膏的使用,而将预先成形为球状的焊锡球供给到开口部18上之后,对半导体基板2实施回焊处理,以此也可以形成凸块电极13。

[0129] 随后,沿着划分好的芯片区域间的划线(切割)区域切断晶片状态的半导体基板2,分割成各个芯片I。所分割的芯片I可以经由凸块电极13而安装到安装基板上。在将芯片I配置到安装基板上之后,对凸块电极13进行回焊,继而在芯片I与安装基板之间填充底部填充树脂,从而制造本实施形态I的半导体装置。

[0130] 在使用接合线14的情况下,如图15所示,将通过光刻技术进行了图案化的光阻剂膜作为遮罩来对表面保护膜12及绝缘膜11进行蚀刻,在输入输出电路形成区域AIO中形成抵达配线7的开口部19、20。

[0131] 继而,在测试用焊垫17处通过探头进行晶片测试。通过探头进行测试时,可以通过使探头的针直接接触到测试用焊垫17而进行。如果利用实际用于形成接合线14的接合垫16来进行测试,则有可能会因探头针的应力而导致在接合垫16下的层间绝缘膜上发生裂纹等问题的产生。因此,本实施形态I中,分别形成有探头测试用的测试用焊垫17的区域与实际用于形成接合线14的接合垫16的区域。

[0132] 其次,沿着划分好的芯片区域间的划线(切割)区域(分割区域)切断晶片状态的半导体基板2,分割成各个芯片I。所分割的芯片I使用DAF(Die Attached Film,芯片附加薄膜)等搭载到安装基板(例如多层配线基板)上。继而,利用接合线14将开口部19A下的接合垫16与安装基板的电极连接之后(参照图4、图6、图8及图10),利用铸模树脂将芯片I及接合线14密封。随后,在特定位置切断铸模树脂及安装基板,从而制造本实施形态I的半导体装置。

[0133] 此处,图16及图17是芯片I中的凸块连接部15 (或凸块电极13)、接合垫16及测试用焊垫17附近的主要部分平面图,图16表示了使用接合线14的情况时的平面,图17表示了使用凸块电极13的情况。如前所述,接合垫16及测试用焊垫17配置在输入输出电路形成区域AIO中,在接合垫16及测试用焊垫17下形成有包含输入输出电路的输入输出电路单元10C。

[0134] 这样,在至此为止的本实施形态I中,对分别配置接合垫16及测试用焊垫17的情况进行了说明,但是也可以如图18及图19所示般,设为使接合垫16与测试用焊垫17—体形成的平面尺寸较大的构造,或者设为省略了测试用焊垫17自身的构造。

[0135] 而且,关于最上层的配线7,是以将铝作为主成分的构成进行了说明,但应明确的是,即使是铜等其他材质也可以获得同样的效果。而且,也可以仅最上层的配线7是由铝形成,而比其更下层的配线层是由以铜为主体的配线层形成。如果对在层间绝缘膜10上形成配线6的情况进行例示,则在形成层间绝缘膜10之后,形成连接于下层的配线5的孔,随后形成构成配线6的配线槽。其次,在孔及槽内,形成由钽或氮化钽等的导电性膜构成的阻障金属膜,在该阻障金属膜上形成以铜为主成分的导电性膜(铜膜)。继而,将槽外部的阻障金属膜及铜膜通过CMP法等而除去,由此可以在孔及槽内埋入阻障金属膜及铜膜,从而形成配线6以及将配线6与配线5连接的连接部。

[0136] 然而,在本实施形态I中,当将芯片I与外部的例如存储器电路等其他芯片电性连接时,设为使用接合线14的构造,例如设为配置在区域A3 (参照图1)中的接合垫16(配线7)成为用于与存储器电路电性连接的接口的构成。另一方面,当无须使芯片I与外部的存储器电路电性连接时,设为使用凸块电极13的构造,例如通过将在区域A3中为了与外部的存储器电路电性连接而设置的配线7上的凸块电极13的形成予以省略,从而能够将芯片I的尺寸缩小化。因此,在成为用于与外部的存储器电路电性连接的接口的区域A3中,例如接合垫16为51个,凸块电极13为10个。即,在本实施形态I中,形成于芯片I上的接合垫16的数量比凸块连接部15的数量多。

[0137] 另外,当成为使用凸块电极13的构成时,成为用于与存储器电路电性连接的接口的区域A3的配线7成为开放端,但对于这样的配线7必须实施提升(pull up)或压低(pulldown)等处理,从而有必要将其设计成,即使成为开放端也不会妨碍形成于芯片I内的逻辑电路的动作。

[0138] 图20至图23表示了将本实施形态I的芯片I作为无线系统的控制器而安装到模组基板21上时的示例,图20及图21分别是使用了所述接合线14时的平面图及侧面图,图22及图23分别是使用了所述凸块电极13时的平面图及侧面图。在模组基板21上,除了芯片I以外,还安装着形成有进行高频动作的RF(Radi0 Frequency,射频)电路的RF芯片22以及旁路电容器芯片23等。旁路电容器芯片23为了电源稳定化而电性插入在电源线中。而且,图20至图23中的箭头表示各芯片间的信号的流动。

[0139] 如前所述,当将使用了接合线14的芯片I安装到模组基板21上时,形成有存储器电路的存储器芯片24也可以安装到模组基板21上(参照图20及图21)。由此,可以搭载大量的固件等程序,因而能够提高整个无线系统的功能。

[0140] 另一方面,当安装有使用了凸块电极13的芯片I时,由于成为不安装存储器芯片24的构成,因而能够以最小构成来构筑无线系统(参照图22及图23)。由此,能够将构筑有该无线系统的模组的尺寸最小化,因此即使对于例如手机之类的模组安装区域受到限定的设备,也能够适用无线系统。[0141](实施形态2)

[0142] 图24是本实施形态2的芯片I的主要部分平面图,图示了相当于所述实施形态I中所示图1中的区域A4的区域。

[0143] 如图24所示,在相对靠近芯片I的外周IA且沿着该外周IA的区域A4中,形成有输入输出电路单元10C,在该输入输出电路单元IOC上,形成有所述实施形态I中也有说明的接合垫16及测试用焊垫17。

[0144] 如图2所示,如所述实施形态I中也有说明般,在I条配线7上也形成有凸块连接部15、接合垫16及测试用焊垫17。由于在输入输出电路单元IOC上形成有接合垫16及测试用焊垫17,因而将配线7引绕至凸块电极13在平面上不会与输入输出电路单元IOC相重叠的区域,例如引绕至相对地芯片I的中心方向而配置凸块连接部15。

[0145] 此处,如图24所示,在区域A4中,当可将输入输出电路单元IOC的配置布局设计成能够确保可在邻接的2个输入输出电路单元IOC间配置凸块电极13的空间时,设为这样的输入输出电路单元IOC的配置布局,向输入输出电路单元IOC间的空间引绕配线7而配置凸块连接部15及凸块电极13。由此,不再需要确保用于在相对地芯片I的中心方向上配置凸块电极13的区域,所以能够缩小芯片I的面积,实现芯片I的小型化。尤其当这样的区域A4靠近图1所示的模拟系电路区域A6时,能够得到有效活用。其理由在于,模拟系电路区域A6与形成有其他逻辑系统电路的区域相比较,引入信号线或电源线的比例较少,所以输入输出电路单兀IOC的数量较少即可。

[0146] 另外,在如区域A3之类的其他区域中,当输入输出电路单元IOC的数量较少即可时,也可以在邻接的2个输入输出电路单元IOC间配置凸块电极13。

[0147] 而且,如图25所示,为了使输入输出电路单元IOC间的空间内所配置的凸块电极13下得到有效活用,也可以在输入输出电路单元IOC间的空间内所配置的凸块电极13下,形成例如通常的逻辑(数字)电路,或包含静电放电(Electrostatic Discharge, ESD)应对用二极管的保护电路。由此,能够在芯片I上搭载进一步的电路功能,或者进一步缩小芯片I的面积而使芯片I进一步小型化。

[0148] 而且,在相对靠近芯片I的外周IA且沿着该外周IA的区域A5(参照图1)中,也可以按与所述的区域A4同样的布局来配置输入输出电路单兀10C,向输入输出电路单兀IOC间的空间引绕配线7而配置凸块连接部15及凸块电极13。

[0149] 然而,在本实施形态2中,该区域A5是芯片I的外周IA与设计上无法配置凸块电极13的区域(第3电路区域)A6之间的狭窄区域,进而是必须从芯片I的外周IA隔开特定距离Tl以上而配置凸块电极13的、在配置凸块电极13时存在制约的区域。另外,该区域A6相对地比区域A5更位于芯片I的内侧,例如形成有模拟系电路。假设在模拟系电路区域A6上形成配线7或凸块电极13,则有可能会产生来自配线7的噪声或寄生电容。模拟系电路区域A6与其他逻辑电路相比,是对噪声或寄生电容较敏感的区域,所以成为如上所述的制约特别严格的区域。

[0150] 如图26所示,当在这样的区域A5中,在与芯片I的外周IA正交的方向上以间距Pl排列有配置在相对靠近芯片I的外周IA的位置上的凸块电极13和配置在相对靠近区域A6的位置上的凸块电极13时,即使该间距Pl与配置在相对靠近芯片I的外周IA的位置上的凸块电极13的配置间距P2相同,配置在相对靠近区域A6的位置上的凸块电极13也有可能会进入无法配置凸块电极13的区域A6中。

[0151] 而且,如图27所示,当配置成,配置在相对靠近芯片I的外周IA的位置上的凸块电极13的2个(或I个)和配置在相对靠近区域A6的位置上的凸块电极13的I个(或2个)成为二等边三角形的顶点,以使得凸块电极13不会与区域A6相重叠时,沿着芯片I的外周IA的方向上的凸块电极13的配置间距P2会变得较宽,如果想要配置所需数量的凸块电极13,则有可能招致芯片I的大型化。另外,图27中,将配置在相对靠近芯片I的外周IA的位置上的凸块电极13与邻接的配置在相对靠近区域A6的位置上的凸块电极13之间的间距设为P1。

[0152] 因此,本实施形态2中,如图28所示配置成,配置在相对靠近芯片I的外周IA的位置上的凸块电极13的2个(或I个)与配置在相对靠近区域A6的位置上的凸块电极13的I个(或2个)成为正三角形的顶点。即配置成,以各凸块电极13的中心为顶点,将各顶点连结而成的形状成为正三角形。由此,与图27所示的成为二等边三角形的顶点的凸块电极13的配置方法相比,能够以较小的区域配置所需数量的凸块电极13。以此可以防止芯片I的尺寸变大,从而维持或缩小芯片I的尺寸。

[0153] 以上,根据实施形态对由本发明者所研发的发明进行了具体说明,但本发明并不限定于所述实施形态,在不脱离其主旨的范围内当可进行各种变更。

[0154][产业适用性]

[0155] 本发明的半导体装置的制造方法及半导体装置可广泛适用于具有经由接合线或凸块电极来安装芯片的构造的半导体装置。

Claims (18)

1.一种半导体装置的制造方法,其特征在于包括以下步骤: (a)在通过分割区域而划分成多个芯片区域的半导体基板上,在所述多个芯片区域的各区域中形成集成电路;(b)在所述多个芯片区域的各区域内,在所述集成电路的上层形成第I配线,该第I配线从第I电路区域延伸到第2电路区域,并与所述集成电路电性连接;(c)将所述第I电路区域的所述第I配线的一部分规定为第I焊垫,将所述第2电路区域的所述第I配线的一部分规定为第2焊垫;(d)在所述第I配线的存在下,于所述半导体基板上形成保护膜;(e)在所述第I焊垫上的所述保护膜上或所述第2焊垫上的所述保护膜上形成开口部;(f)沿着所述分割区域切断所述半导体基板,分割成各个半导体芯片;(g)将所述半导体芯片分别安装到安装基板上,并经由接合线或凸块电极而将所述半导体芯片分别与所述安装基板电性连接,所述第I焊垫用于与接合线连接,所述第2焊垫用于与凸块电极连接;且, 当在所述(g)步骤中经由所述接合线而将所述半导体芯片分别与所述安装基板电性连接时,在所述(e)步骤中所述开口部是形成于所述第I焊垫上的所述保护膜上,而在所述(g)步骤中于所述开口部下将所述接合线连接于所述第I焊垫, 当在所述(g)步骤中经由所述凸块电极而将所述半导体芯片分别与所述安装基板电性连接时,在所述(e)步骤 中所述开口部形成于所述第2焊垫上的所述保护膜上,进而在所述第2焊垫上形成所述凸块电极,该凸块电极在所述开口部下与所述第2焊垫连接。
2.根据权利要求1所述的半导体装置的制造方法,其特征在于, 所述第I配线与电源电位或基准电位电性连接, 所述半导体芯片各自经由所述凸块电极而与所述安装基板电性连接, 所述(b)步骤中,在形成有所述第I配线的第I配线层中,形成多条第2配线,所述多条第2配线与所述第I配线电性连接,且相互平行地延伸, 所述(c)步骤中,将所述第2配线的一部分规定为第3焊垫, 所述(e)步骤中,在所述第3焊垫上的所述保护膜上形成所述开口部,进而在所述第3焊垫上形成所述凸块电极,该凸块电极在所述开口部下与所述第3焊垫连接。
3.根据权利要求2所述的半导体装置的制造方法,其特征在于, 所述(a)步骤中,在比所述第I配线层更下层的第2配线层中形成多条第3配线,所述多条第3配线与所述第I配线及所述第2配线电性连接,且相互平行地延伸, 所述多条第2配线及所述多条第3配线形成于包含所述半导体芯片的中央的所述第2电路区域中。
4.根据权利要求1所述的半导体装置的制造方法,其特征在于, 所述半导体芯片各自经由所述凸块电极而与所述安装基板电性连接, 在所述半导体芯片内,将所述第2电路区域配置在所述第I电路区域与第3电路区域之间,所述第I电路区域相对靠近所述半导体芯片的外周,所述第3电路区域比所述第I电路区域及所述第2电路区域更处在所述半导体芯片的内侧。
5.根据权利要求1所述的半导体装置的制造方法,其特征在于, 所述半导体芯片各自经由所述凸块电极而与所述安装基板电性连接, 将包含输入输出电路的所述第I电路区域沿着所述半导体芯片的外周而配置多个, 将所述第2电路区域配置在所述第I电路区域间。
6.根据权利要求5所述的半导体装置的制造方法,其特征在于, 在所述凸块电极下的所述第2电路区域上形成第I电路,所述第I电路包含数字电路或ESD应对用半导体元件。
7.根据权利要求5所述的半导体装置的制造方法,其特征在于, 将所述第2电路区域配置在所述第I电路区域与比所述第I电路区域及所述第2电路区域更靠近所述半导体芯片中心的第3电路区域之间, 以所述凸块电极中,所述第I电路区域间的所述第2电路区域上的I个或相邻的2个所述凸块电极,和所述第I电路区域与所述第3电路区域之间的所述第2电路区域上的I个或相邻的2个所述凸块电极成为正三角形的各顶点的方式配置所述凸块电极。
8.根据权利要求1所述的半导体装置的制造方法,其特征在于, 所述第I焊垫的数量比所述第2焊垫的数量多。
9.根据权利要求8所述的半导体装置的制造方法,其特征在于, 在所述(b)步骤中,形成多条所述第I配线, 所述多条所述第I配线的 一部分成为与存储器芯片之间的接口, 当在所述安装基板上安装所述存储器芯片时,在所述(g)步骤中,经由所述接合线而将所述半导体芯片分别与所述安装基板电性连接,并将所述接口与所述存储器芯片电性连接, 当不在所述安装基板上安装所述存储器芯片时,在所述(g)步骤中,经由所述凸块电极而将所述半导体芯片分别与所述安装基板电性连接,在所述(c)步骤中,不对所述接口规定所述第2焊垫,且在所述(e)步骤中不形成与所述接口连接的所述凸块电极。
10.根据权利要求1所述的半导体装置的制造方法,其特征在于, 在经由所述接合线而将所述半导体芯片分别与所述安装基板电性连接的情况、和经由所述凸块电极而将所述半导体芯片分别与所述安装基板电性连接的情况下,所述第I电路区域、所述第2电路区域、所述集成电路及所述第I配线以相同的布局而形成。
11.一种半导体装置,其特征在于包括: 半导体芯片,其主面上形成有集成电路,且被规定有第I电路区域及第2电路区域,所述第I电路区域沿着半导体芯片的外周而配置有多个,且包含用于与接合线连接的第I焊垫的输入输出电路,所述第2电路区域配置在所述第I电路区域间; 凸块电极,其形成在所述第2电路区域上,且与所述集成电路电性连接;以及形成在所述第2电路区域上,用于与所述凸块电极连接的第2焊垫;且 所述第I焊垫以及所述第2焊垫形成于所述集成电路的上层的同一配线上。
12.根据权利要求11所述的半导体装置,其特征在于, 在所述凸块电极下的所述第2电路区域中形成有包含数字电路或ESD应对用半导体元件的第I电路。
13.根据权利要求11所述的半导体装置,其特征在于, 规定有比所述第I电路区域及所述第2电路区域更靠近所述半导体芯片中心的第3电路区域, 所述第2电路区域及所述凸块电极进而配置在所述第I电路区域与所述第3电路区域之间,所述凸块电极配置成,所述凸块电极中,所述第I电路区域间的所述第2电路区域上的I个或相邻的2个所述凸块电极,和所述第I电路区域与所述第3电路区域之间的所述第2电路区域上的I个或相邻的2个所述凸块电极成为正三角形的各顶点。
14.一种半导体装置的制造方法,其特征在于包括以下步骤: (a)在半导体基板上形成第I配线;(b)在所述第I配线上形成第I绝缘膜; (c)在所述第I绝缘膜上形成开口部,使所述第I配线的一部分露出, 在所述(a)步骤中,在所述第I配线上形成有用于供接合线形成,且具有用于与接合线连接的第I焊垫的多个第I区域以及用于供凸块电极形成,且具有用于与凸块电极连接的第2焊垫的多个第2区域, 在所述(c)步骤中,当对于所述半导体装置使用所述接合线时,所述开口部是分别形成于所述多个第I区域的所述第I焊垫,且不形成于所述多个第2区域中, 在所述(c)步骤中,当对于所述半导体装置使用所述凸块电极时,所述开口部是分别形成于所述多个第2区域的所述第2焊垫,且不形成于所述多个第I区域中。
15.根据权利要求14所述的半导体装置的制造方法,其特征在于, 所述多个第I区域的数量比 所述多个第2区域的数量多。
16.根据权利要求14所述的半导体装置的制造方法,其特征在于, 在所述多个第I区域之下分别形成有输入输出电路用单元。
17.根据权利要求16所述的半导体装置的制造方法,其特征在于, 所述多个第2区域中的一部分是形成在邻接的输入输出电路用单元之间。
18.根据权利要求17所述的半导体装置的制造方法,其特征在于, 在形成于所述邻接的输入输出电路用单元之间的所述第2区域之下的所述半导体基板上,形成有数字电路或ESD应对用半导体元件。
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