EP1897138B1 - Semiconductor device and mounting structure thereof - Google Patents

Semiconductor device and mounting structure thereof Download PDF

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Publication number
EP1897138B1
EP1897138B1 EP06747146A EP06747146A EP1897138B1 EP 1897138 B1 EP1897138 B1 EP 1897138B1 EP 06747146 A EP06747146 A EP 06747146A EP 06747146 A EP06747146 A EP 06747146A EP 1897138 B1 EP1897138 B1 EP 1897138B1
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EP
European Patent Office
Prior art keywords
wiring line
semiconductor device
insulating film
openings
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP06747146A
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German (de)
French (fr)
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EP1897138A1 (en
Inventor
Takeshi c/o I.P.D. Casio Computer Co . WAKABAYASHI
Ichiro c/oI.P.D. Casio Computer Co. MIHARA
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Publication of EP1897138B1 publication Critical patent/EP1897138B1/en
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Definitions

  • This invention relates to a semiconductor device and a mounting structure thereof.
  • a semiconductor device is flip-chip-mounted on a substrate.
  • a method is employed, wherein a bare semiconductor substrate having an integrated circuit formed therein is directly provided with external electrode pads connected to the integrated circuit, and solder balls are formed on the external electrode pads, and then the solder balls are bonded to connection terminals of an external circuit board, thereby minimizing a mounting area (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2001-196374 ).
  • a silicon oxide film is formed on a silicon substrate, and a plurality of through-holes are formed in the silicon oxide film and metal layers are provided in the through-holes. Then, a thin silicon layer is formed on the silicon oxide film, and an integrated circuit including P-type and/or N-type MOS transistors is formed in the silicon layer, and then an upper surface of the integrated circuit is covered with an interlayer insulating film. Subsequently, the silicon substrate is polished in its thickness direction from its lower side so that it completely removed to expose a lower surface of the silicon oxide film. Then, external electrode pad portions are formed at places corresponding to the through-holes provided in the silicon oxide film before solder balls are provided on the external electrode pad portions. In this manner, the external electrode pad portions and the solder balls are provided to correspond to one another in the metal layers connected to the integrated circuit via the through-holes.
  • the size of the semiconductor device is significantly increased, which requires a large mounting area.
  • a short-circuit occurs in a bonding step, and there is a great variation in the size of the solder balls, making it impossible to obtain reliability in connection.
  • WO-A-2005/024912 discloses an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level, wherein each thick metal layer may be coupled to a row of C4 bumps.
  • C4 Controlled Collapse Chip Connection
  • US-A-2004/0079966 discloses a chip structure comprising cross laminations of dielectric-multi layers and interconnected metal layers, which connects with external circuits through nodes for applying ground voltage or power voltage.
  • this invention is directed to provide a semiconductor device and a mounting structure thereof in which the number of external electrode pad portions can be reduced to achieve a size reduction and an improvement of reliability in connection.
  • this invention provides a semiconductor device according to appended claim 1 and a mounting structure comprising the semiconductor device according to appended claim 16.
  • the wiring line for external connection is connected to the internal wiring line through a plurality of openings formed in the second insulating film.
  • the number of the wiring line may be decreased in comparison with the prior art, to allow the semiconductor device to become smaller and higher reliability in connection.
  • FIG. 1 shows a sectional view of a semiconductor device as a first embodiment of this invention.
  • This semiconductor device includes a silicon substrate (semiconductor substrate) 1.
  • An integrated circuit (not shown) having a predetermined function is provided in the center of an upper side of the silicon substrate 1, and a plurality of internal connection pads 2 made of a metal such as an aluminum-based metal are provided in peripheral parts of the upper surface in such a manner as to be electrically connected to the integrated circuit.
  • a first insulating film 3 made of silicon oxide, silicon nitride or the like is provided on the upper surfaces of the internal connection pads 2 and the silicon substrate 1.
  • a plurality of openings 4 are formed, for example, in matrix-form arrangement, in the first insulating film 3 in parts corresponding to the centers of the upper surfaces of the internal connection pads 2.
  • An internal wiring line 5 of about 1 ⁇ m in thickness made of copper or a copper alloy is provided on an upper surface of the first insulating film 3 in such a manner as to be electrically connected to the internal connection pads 2 via the openings 4 of the first insulating film 3.
  • the internal wiring line 5 shown in FIG. 1 is an internal wiring line for grounding or for V DD (generically called “for power source"), and several to several ten internal wiring lines are provided in parallel and vertically spaced with each other to the surface of the drawing of FIG. 1 .
  • internal wiring lines for control signals and for data are omitted.
  • a second insulating film 6 made of silicon oxide, silicon nitride or the like is provided on the upper surfaces of the first insulating film 3 and the internal wiring lines 5. Openings 7 are formed in the second insulating film 6 in parts corresponding to a plurality (e.g., six) of connection pad portions of each of the internal wiring lines 5.
  • Connection pads 8 made of copper, a copper alloy or the like are provided in the openings 7 of the second insulating film 6 and on an upper surface of the second insulating film 6 in the vicinity or periphery of the openings 7 in such a manner as to be electrically connected to the connection pad portions of the internal wiring line 5.
  • a third insulating film 9 made of silicon oxide, silicon nitride or the like is provided on the upper surfaces of the second insulating film 6 and the connection pads 8. Openings 10 are formed in the third insulating film 9 in parts corresponding to the centers of upper surfaces of the connection pads 8.
  • a protective film (insulating film) 11 made of a polyimide-based resin or the like is provided on an upper surface of the third insulating film 9. Openings 12 are formed in the protective film 11 in parts corresponding to the openings 10 of the third insulating film 9. Foundation metal or lower layers 13 made of copper or the like are provided on an upper surface of the protective film 11. A wiring line or upper layer 14 made of copper is provided on an entire upper surface of the foundation metal layer 13. In this case, the thickness of the wiring line 14 is larger than the thickness of the internal wiring line 5, and is preferably 2 to 10 ⁇ m.
  • Each of the foundation metal layers 13 and each of the wiring lines 14 are connected to the plurality (e.g., three) of internal connection pads 2 via the plurality (e.g., three) of openings 12, 10 of the protective film 11 and the third insulating film 9.
  • part of the foundation metal layer 13 is only provided within the openings 10 formed in the third insulating film 9 and within the openings 12 formed in the protective film 11, but this is for figure convenience, and in practice, part of the wiring line 14 is also provided therein.
  • each of the foundation metal layers 13 and each of the wiring lines 14 are provided across the three respective openings 10 and 12, but this is also for figure convenience, and in practice, they are formed across several to several ten respective openings 10 and 12.
  • the width of each of the wiring lines 14 is decided in accordance with a later-described current from an external power source supplied to the solder balls.
  • An overcoat film 15 made of a solder resist or the like is provided on upper surfaces of the wiring lines 14 and the protective film 11.
  • a substantially central part in longitudinal and width directions thereof serves as an external electrode pad portion, and openings 16 are formed in the overcoat film 15 in parts corresponding to the external electrode pad portions.
  • a solder ball 17 is provided within and above the opening 16 in such a manner as to be electrically connected to the external electrode pad portion of the wiring line 14.
  • each of the internal wiring lines 5 is electrically connected to the plurality of internal connection pads 2.
  • connection pads 8 are provided in each of the internal wiring lines 5.
  • One wiring line 14 is connected to several to several ten connection pads 8.
  • Each of the solder balls 17 is formed in one external electrode pad portion provided in each of the wiring lines 14.
  • the number of solder balls 17 for grounding or for power source corresponds to a few percent to several ten percent of the number of connection pads 8 for power source, so that the total number of solder balls 17 can be smaller than the total number of connection pads 8, thus making it possible to achieve a size reduction of the semiconductor device and an improvement of reliability in connection.
  • a plurality of second wiring lines 14 are arranged to extend in the longitudinal direction of the internal or first wiring lines 5, and if both lines 5 and 14 have the same width, no space is wasted in terms of layout, allowing a reduction in the size of the semiconductor device.
  • Ni / To / Ti ⁇ No ⁇ Ni ⁇ To / Ti - 1 be satisfied, wherein Ni is the number of openings 10 or 12 corresponding to one second wiring line, No is the number of external electrode pad portions provided in one second wiring line (or the number of openings 16), Ti is the thickness of the first wiring line 5, and To is the thickness of the second wiring line 14 including the foundation metal layer 13.
  • FIG. 2 shows a sectional view of a semiconductor device as a second embodiment of this invention.
  • This semiconductor device is different from the semiconductor device shown in FIG. 1 in that a columnar electrode 18 made of copper is provided on an upper surface of an external electrode pad portion of a second wiring line 14, and a sealing film 19 made of an epoxy-based resin or the like is provided on an upper surface of a protective film 11 including the wiring line 14 so that an upper surface of the sealing film 19 may form one surface with upper surfaces of the columnar electrodes 18, and then a solder ball 17 is provided on the upper surface of the columnar electrode 18.
  • first and second insulating films (interlayer insulating films) 3 and 6 when so-called low-k is used as a material for first and second insulating films (interlayer insulating films) 3 and 6, the specific inductive capacity and elasticity modulus of the first and second insulating films 3 and 6 are in a trade-off relation. If the specific inductive capacity is reduced, a very fragile material having a young's elasticity modulus of 5 Gpa or less is used. In this case, in general, when the semiconductor device comprising the columnar electrodes 18 is mounted on a circuit board (not shown), cracks may be easily caused in the first and second insulating films 3 and 6 by stress due to a difference of thermal expansion coefficients between a silicon substrate 1 and the circuit board.
  • the total number of solder balls 17 can be smaller than the total number of connection pads 8 to increase the size of the solder balls 17, it is possible to reduce the stress due to the difference of thermal expansion coefficients between the silicon substrate 1 and the circuit board. Therefore, even if the so-called low-k which has a young's elasticity modulus of 5 Gpa or less and is thus very fragile is used as the material for first and second insulating films 3 and 6, it is possible to prevent the cracks from being easily caused in the first and second insulating films 3 and 6.
  • one external electrode pad portion is provided in each of the second wiring lines 14 provided for several to several ten connection pads 8, but the number of external electrode pad portions provided in each of the wiring lines 14 is not necessarily limited to one, and a plurality of external electrode pad portions may be provided as long as the number thereof is smaller than the number of connection pads.
  • One solder ball 17 is formed under the wiring line 14.
  • FIG. 3 is a plan view of an external circuit board 20 to which the aforementioned semiconductor device is to be mounted face down.
  • a power source wiring line pattern 22 is provided on one surface of the circuit board 20.
  • the power source wiring line pattern 22 is a pattern which interconnects a plurality of feeder lines 21 arranged in parallel to correspond to the internal wiring lines 5, and each of the feeder lines 21 is provided with connection terminal portions 23 corresponding to the external electrode pad portions of the wiring line 14 of the semiconductor device.
  • the solder balls 17 provided on the external electrode pad portions are aligned with the connection terminal portions 23 of the circuit board 20 to mount the semiconductor device face down by bonding.
  • the power source wiring line pattern 22 of the circuit board 20 is desirably covered with a resist except for the connection terminal portions.

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Description

    Technical Field
  • This invention relates to a semiconductor device and a mounting structure thereof.
    • Background Art
  • Recently, in equipment such as personal computers and mobile devices, it has often been the case that, in order to reduce equipment size, a semiconductor device is flip-chip-mounted on a substrate. In this case, a method is employed, wherein a bare semiconductor substrate having an integrated circuit formed therein is directly provided with external electrode pads connected to the integrated circuit, and solder balls are formed on the external electrode pads, and then the solder balls are bonded to connection terminals of an external circuit board, thereby minimizing a mounting area (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2001-196374 ).
  • In the above-mentioned semiconductor device, a silicon oxide film is formed on a silicon substrate, and a plurality of through-holes are formed in the silicon oxide film and metal layers are provided in the through-holes. Then, a thin silicon layer is formed on the silicon oxide film, and an integrated circuit including P-type and/or N-type MOS transistors is formed in the silicon layer, and then an upper surface of the integrated circuit is covered with an interlayer insulating film. Subsequently, the silicon substrate is polished in its thickness direction from its lower side so that it completely removed to expose a lower surface of the silicon oxide film. Then, external electrode pad portions are formed at places corresponding to the through-holes provided in the silicon oxide film before solder balls are provided on the external electrode pad portions. In this manner, the external electrode pad portions and the solder balls are provided to correspond to one another in the metal layers connected to the integrated circuit via the through-holes.
  • Recently, semiconductor devices for control use driven at a high-speed clock of several gigahertz have emerged. It is necessary to supply a current of several tens of A from an external power source to such a semiconductor device. In this case, if the diameter of the solder balls provided on the external electrode pad portions is about 100 µm, a current of about 30 mA can only be passed to one solder ball in order to prevent the breakdown of the solder balls due to heat generation. Therefore, when a power source of a large current of several tens of A is required, a current passed to several thousand external electrode pad portions via several thousand solder balls converges inside.
  • For the purpose of, for example, face-down mounting to connection terminal portions of the external circuit board via the solder balls thus provided on a large number of external electrode pad portions, the size of the semiconductor device is significantly increased, which requires a large mounting area. Moreover, due to the large number of solder balls, a short-circuit occurs in a bonding step, and there is a great variation in the size of the solder balls, making it impossible to obtain reliability in connection.
  • WO-A-2005/024912 discloses an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level, wherein each thick metal layer may be coupled to a row of C4 bumps. US-A-2004/0079966 discloses a chip structure comprising cross laminations of dielectric-multi layers and interconnected metal layers, which connects with external circuits through nodes for applying ground voltage or power voltage.
    • Disclosure of Invention
  • Therefore, this invention is directed to provide a semiconductor device and a mounting structure thereof in which the number of external electrode pad portions can be reduced to achieve a size reduction and an improvement of reliability in connection.
  • In order to achieve the above object, this invention provides a semiconductor device according to appended claim 1 and a mounting structure comprising the semiconductor device according to appended claim 16.
  • Other embodiments are defined by the dependent claims. According to this invention, the wiring line for external connection is connected to the internal wiring line through a plurality of openings formed in the second insulating film. Thus, the number of the wiring line may be decreased in comparison with the prior art, to allow the semiconductor device to become smaller and higher reliability in connection.
  • Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
    • Brief Description of Drawings
  • The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.
    • FIG. 1 is a sectional view of a semiconductor device as a first embodiment of this invention;
    • FIG. 2 is a sectional view of a semiconductor device as a second embodiment of this invention; and
    • FIG. 3 is a plan view showing one embodiment of a circuit board to which the semiconductor device of this invention is connected.
    Best Mode for Carrying Out the Invention (First Embodiment)
  • FIG. 1 shows a sectional view of a semiconductor device as a first embodiment of this invention. This semiconductor device includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) having a predetermined function is provided in the center of an upper side of the silicon substrate 1, and a plurality of internal connection pads 2 made of a metal such as an aluminum-based metal are provided in peripheral parts of the upper surface in such a manner as to be electrically connected to the integrated circuit.
  • A first insulating film 3 made of silicon oxide, silicon nitride or the like is provided on the upper surfaces of the internal connection pads 2 and the silicon substrate 1. A plurality of openings 4 are formed, for example, in matrix-form arrangement, in the first insulating film 3 in parts corresponding to the centers of the upper surfaces of the internal connection pads 2. An internal wiring line 5 of about 1 µm in thickness made of copper or a copper alloy is provided on an upper surface of the first insulating film 3 in such a manner as to be electrically connected to the internal connection pads 2 via the openings 4 of the first insulating film 3.
  • Here, the internal wiring line 5 shown in FIG. 1 is an internal wiring line for grounding or for VDD (generically called "for power source"), and several to several ten internal wiring lines are provided in parallel and vertically spaced with each other to the surface of the drawing of FIG. 1. In FIG. 1, internal wiring lines for control signals and for data are omitted.
  • A second insulating film 6 made of silicon oxide, silicon nitride or the like is provided on the upper surfaces of the first insulating film 3 and the internal wiring lines 5. Openings 7 are formed in the second insulating film 6 in parts corresponding to a plurality (e.g., six) of connection pad portions of each of the internal wiring lines 5.
  • Connection pads 8 made of copper, a copper alloy or the like are provided in the openings 7 of the second insulating film 6 and on an upper surface of the second insulating film 6 in the vicinity or periphery of the openings 7 in such a manner as to be electrically connected to the connection pad portions of the internal wiring line 5. A third insulating film 9 made of silicon oxide, silicon nitride or the like is provided on the upper surfaces of the second insulating film 6 and the connection pads 8. Openings 10 are formed in the third insulating film 9 in parts corresponding to the centers of upper surfaces of the connection pads 8.
  • A protective film (insulating film) 11 made of a polyimide-based resin or the like is provided on an upper surface of the third insulating film 9. Openings 12 are formed in the protective film 11 in parts corresponding to the openings 10 of the third insulating film 9. Foundation metal or lower layers 13 made of copper or the like are provided on an upper surface of the protective film 11. A wiring line or upper layer 14 made of copper is provided on an entire upper surface of the foundation metal layer 13. In this case, the thickness of the wiring line 14 is larger than the thickness of the internal wiring line 5, and is preferably 2 to 10 µm. Each of the foundation metal layers 13 and each of the wiring lines 14 are connected to the plurality (e.g., three) of internal connection pads 2 via the plurality (e.g., three) of openings 12, 10 of the protective film 11 and the third insulating film 9. Here, in FIG. 1, part of the foundation metal layer 13 is only provided within the openings 10 formed in the third insulating film 9 and within the openings 12 formed in the protective film 11, but this is for figure convenience, and in practice, part of the wiring line 14 is also provided therein. Moreover, each of the foundation metal layers 13 and each of the wiring lines 14 are provided across the three respective openings 10 and 12, but this is also for figure convenience, and in practice, they are formed across several to several ten respective openings 10 and 12. The width of each of the wiring lines 14 is decided in accordance with a later-described current from an external power source supplied to the solder balls.
  • An overcoat film 15 made of a solder resist or the like is provided on upper surfaces of the wiring lines 14 and the protective film 11. In each of the wiring lines 14, a substantially central part in longitudinal and width directions thereof serves as an external electrode pad portion, and openings 16 are formed in the overcoat film 15 in parts corresponding to the external electrode pad portions. A solder ball 17 is provided within and above the opening 16 in such a manner as to be electrically connected to the external electrode pad portion of the wiring line 14.
  • As described above, in this semiconductor device, there are provided several to several ten internal wiring lines 5, and each of them is electrically connected to the plurality of internal connection pads 2. There are provided a number of connection pads 8 in each of the internal wiring lines 5. One wiring line 14 is connected to several to several ten connection pads 8. Each of the solder balls 17 is formed in one external electrode pad portion provided in each of the wiring lines 14.
  • Therefore, in this semiconductor device, the number of solder balls 17 for grounding or for power source corresponds to a few percent to several ten percent of the number of connection pads 8 for power source, so that the total number of solder balls 17 can be smaller than the total number of connection pads 8, thus making it possible to achieve a size reduction of the semiconductor device and an improvement of reliability in connection.
  • Here, a plurality of second wiring lines 14 are arranged to extend in the longitudinal direction of the internal or first wiring lines 5, and if both lines 5 and 14 have the same width, no space is wasted in terms of layout, allowing a reduction in the size of the semiconductor device. Here, since the sums of power source currents supplied to the first wiring lines 5 and the wiring second lines 14 via the electrode pad portions are equal, it is recommended that Ni / To / Ti ≤ No ≤ Ni ⁢ To / Ti - 1
    Figure imgb0001
    be satisfied, wherein Ni is the number of openings 10 or 12 corresponding to one second wiring line, No is the number of external electrode pad portions provided in one second wiring line (or the number of openings 16), Ti is the thickness of the first wiring line 5, and To is the thickness of the second wiring line 14 including the foundation metal layer 13.
    • (Second Embodiment)
  • FIG. 2 shows a sectional view of a semiconductor device as a second embodiment of this invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that a columnar electrode 18 made of copper is provided on an upper surface of an external electrode pad portion of a second wiring line 14, and a sealing film 19 made of an epoxy-based resin or the like is provided on an upper surface of a protective film 11 including the wiring line 14 so that an upper surface of the sealing film 19 may form one surface with upper surfaces of the columnar electrodes 18, and then a solder ball 17 is provided on the upper surface of the columnar electrode 18.
  • In this semiconductor device, when so-called low-k is used as a material for first and second insulating films (interlayer insulating films) 3 and 6, the specific inductive capacity and elasticity modulus of the first and second insulating films 3 and 6 are in a trade-off relation. If the specific inductive capacity is reduced, a very fragile material having a young's elasticity modulus of 5 Gpa or less is used. In this case, in general, when the semiconductor device comprising the columnar electrodes 18 is mounted on a circuit board (not shown), cracks may be easily caused in the first and second insulating films 3 and 6 by stress due to a difference of thermal expansion coefficients between a silicon substrate 1 and the circuit board.
  • However, in the second embodiment, since the total number of solder balls 17 can be smaller than the total number of connection pads 8 to increase the size of the solder balls 17, it is possible to reduce the stress due to the difference of thermal expansion coefficients between the silicon substrate 1 and the circuit board. Therefore, even if the so-called low-k which has a young's elasticity modulus of 5 Gpa or less and is thus very fragile is used as the material for first and second insulating films 3 and 6, it is possible to prevent the cracks from being easily caused in the first and second insulating films 3 and 6.
  • In the embodiments described above, one external electrode pad portion is provided in each of the second wiring lines 14 provided for several to several ten connection pads 8, but the number of external electrode pad portions provided in each of the wiring lines 14 is not necessarily limited to one, and a plurality of external electrode pad portions may be provided as long as the number thereof is smaller than the number of connection pads. One solder ball 17 is formed under the wiring line 14.
  • FIG. 3 is a plan view of an external circuit board 20 to which the aforementioned semiconductor device is to be mounted face down. A power source wiring line pattern 22 is provided on one surface of the circuit board 20. The power source wiring line pattern 22 is a pattern which interconnects a plurality of feeder lines 21 arranged in parallel to correspond to the internal wiring lines 5, and each of the feeder lines 21 is provided with connection terminal portions 23 corresponding to the external electrode pad portions of the wiring line 14 of the semiconductor device. The solder balls 17 provided on the external electrode pad portions are aligned with the connection terminal portions 23 of the circuit board 20 to mount the semiconductor device face down by bonding. Although not shown in the figure, the power source wiring line pattern 22 of the circuit board 20 is desirably covered with a resist except for the connection terminal portions.

Claims (16)

  1. A semiconductor device comprising:
    a semiconductor substrate (1) having an integrated circuit that includes a plurality of internal connection pads (2);
    a first insulating film (3) having a plurality of first openings (4) corresponding to the internal connection pads (2), respectively formed on the semiconductor substrate (1);
    at least one power source internal wiring line (5) formed on the first insulating film (3) and connected to the internal connection pads (2) via the first openings (4);
    a second insulating film (6) formed on the first insulating film (3) and on the internal wiring line (5) and having a plurality of second openings (7) exposing parts of the internal wiring line (5); and
    at least one wiring line (13, 14) formed on an upper side of the second insulating film (6) to correspond to the internal wiring line (5) and electrically connected to the internal wiring line (5) via the plurality of the second openings (7) of the second insulating film (6),
    wherein said at least one wiring line (14) has at least one external electrode pad portion whose number is smaller than the number of the second openings (7) in the second insulating film (6),
    characterized in that
    the at least one wiring line (13, 14) has a thickness thicker than the internal wiring line (5) and a length shorter than the internal wiring line (5), and
    the number of the second openings (7) of the second insulating film (6) is larger than the number of the first openings (4) of the first insulating film (3).
  2. The semiconductor device according to claim 1, wherein a solder ball (17) is provided on the external electrode pad portion of said wiring line (14).
  3. The semiconductor device according to claim 1, wherein a columnar electrode (18) is provided on the external electrode pad portion of said wiring line (14).
  4. The semiconductor device according to claim 3, wherein a solder ball (17) is provided on the columnar electrode (18).
  5. The semiconductor device according to claim 1, which further comprises connection pads (8) provided in the second openings (7) of the second insulating film (6) covering an upper surface of the power source internal wiring line (5).
  6. The semiconductor device according to claim 5, wherein the second insulating film (6, 9) includes a first layer (6) formed between the connection pads (8), and a second layer (9) provided on the first layer (6) and both layers (6, 9) having first openings (10) formed at positions corresponding to the connection pads (8).
  7. The semiconductor device according to claim 1, wherein the second layer has a layer structure constituted of a plurality of layers (6, 9).
  8. The semiconductor device according to claim 1, wherein said wiring line (14) and the internal wiring line (5) are made of copper or a copper alloy.
  9. The semiconductor device according to claim 1, wherein the Young's elasticity modulus of at least one of the first (3) and second (6) insulating films is 5 Gpa or less.
  10. The semiconductor device according to claim 1, wherein said wiring line (14) and the internal wiring line (5) have the same width.
  11. The semiconductor device according to claim 1, wherein the plurality of said wiring lines (14) are arranged along the internal wiring line (5).
  12. The semiconductor device according to claim 1, wherein Ni / To / Ti ≤ No ≤ Ni ⁢ To / Ti - 1
    Figure imgb0002
    is satisfied, where Ni is the number of the second openings (7) corresponding to said wiring line (14), No is the number of external electrode pad portions provided in said wiring line (14), Ti is the thickness of the internal wiring line (5), and To is the thickness of said wiring line (14).
  13. The semiconductor device according to claim 1, wherein the first insulating film (3) is made of low-k.
  14. The semiconductor device according to claim 1, wherein the second insulating film (6) is made of low-k.
  15. The semiconductor device according to claim 13 or 14, wherein the device further includes a columnar electrode on said wiring line.
  16. A semiconductor device and a mounting structure therefore, comprising;
    the semiconductor device according to any of claims 1 to 15, and
    the mounting structure which includes:
    a substrate (20) having a power source pattern (22) with at least one power source terminal portion (23) corresponding to the external electrode pad portion of the semiconductor device; and
    a solder layer bonding the external electrode pad portion to the power source terminal portion (23) of the power source pattern (22).
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US7719116B2 (en) 2010-05-18
US20060273463A1 (en) 2006-12-07
KR100877018B1 (en) 2009-01-07
EP1897138A1 (en) 2008-03-12
DE602006012674D1 (en) 2010-04-15
KR20070088688A (en) 2007-08-29
CN101091250A (en) 2007-12-19
CN100514627C (en) 2009-07-15
JP2006339331A (en) 2006-12-14
JP4449824B2 (en) 2010-04-14
WO2006129832A1 (en) 2006-12-07

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