TW201640628A - 具有較佳散熱效能的半導體晶片封裝構件 - Google Patents

具有較佳散熱效能的半導體晶片封裝構件 Download PDF

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TW201640628A
TW201640628A TW105111955A TW105111955A TW201640628A TW 201640628 A TW201640628 A TW 201640628A TW 105111955 A TW105111955 A TW 105111955A TW 105111955 A TW105111955 A TW 105111955A TW 201640628 A TW201640628 A TW 201640628A
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chip package
pad
package
solder
wafer
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TW105111955A
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TWI624916B (zh
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蕭景文
林子閎
彭逸軒
謝東憲
張聖明
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聯發科技股份有限公司
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Abstract

一種半導體晶片封裝構件，包含一基板，具有一晶片安裝面；複數焊接墊，設於晶片安裝面上；第一虛設接墊及與第一虛設接墊間隔開的第二虛設接墊，設於晶片安裝面上；一防焊遮罩，設於晶片安裝面上，且部分覆蓋該焊接墊、第一虛設接墊及第二虛設接墊；一晶片封裝，安裝在晶片安裝面上，透過設於複數焊接墊上的複數個錫球電連接基板；一分立元件，設於晶片封裝與基板之間，該分立元件具有第一連接端與第二連接端；一第一焊錫，將第一連接端、第一虛設接墊與晶片封裝連接起來；及一第二焊錫，將第二連接端、第二虛設接墊與晶片封裝連接起來。

Description

具有較佳散熱效能的半導體晶片封裝構件
本發明係有關於一種晶片封裝構件。更具體而言，本發明係有關於一種半導體晶片封裝構件，具有較佳的散熱效能。
過去形成半導體晶片封裝構件的方法中，晶片（或晶片封裝）係透過焊料接合電連接到封裝基板。晶片放置在封裝基板上並對準放置位點，使得焊球對準基板上的接墊或預焊料。基板通常由有機材料或層壓材料組成。後續再利用加熱回焊，形成晶片與封裝基板之間的電連接。
對於晶片封裝，有電氣性能和散熱控制兩大挑戰。在電氣性能方面，晶片封裝必須維持信號完整性和半導體元件的操作頻率。在散熱控制的方面，則要求晶片封裝有效消散由半導體晶片產生的熱。
通常，會利用導熱膠將散熱器或散熱蓋黏貼在基板和晶片上。上述散熱器或散熱蓋通常由高導熱性材料製成，並且具有基本上與封裝基板相同的尺寸。散熱器的目的是分散操作期間所產生的熱，以降低封裝構件內的應力。
隨著半導體技術的飛速發展，晶片上的輸入/輸出（I/O）墊的數量急劇增加，且晶片消耗的功率也增加了。僅靠安裝在覆晶晶片的非主動面上的散熱器已無法有效地消散來自晶片（或晶片封裝的基板側）主動面的熱。因此，有必要在該技術領域中提供一種具有較佳散熱效能的晶片封裝構件。
本發明的主要目的在提供一種改良的半導體晶片封裝構件，具有較佳散熱效能，而能解決先前技藝的不足與缺點。
根據本發明一實施例，提供一種半導體晶片封裝構件，包含有一基板，具有一晶片安裝面；複數個焊接墊，設於該晶片安裝面上；一第一虛設接墊以及一與該第一需設接墊間隔開的第二虛設接墊，設於該晶片安裝面上；一防焊遮罩，設於該晶片安裝面上，並部分覆蓋該焊接墊、該第一虛設接墊與該第二虛設接墊；一晶片封裝，安裝在該晶片安裝面上，並透過設於該複數個焊接墊上的複數個錫球電連接該基板；一分立元件，設於該晶片封裝與該基板之間，該分立元件具有一第一連接端與一第二連接端；一第一焊錫，將該第一連接端、該第一虛設接墊與該晶片封裝連接起來；以及一第二焊錫，將該第二連接端、該第二虛設接墊與該晶片封裝連接起來。其中該分立元件包含一基板側電容、一去耦電容、一電阻或一電感。
以上的半導體晶片封裝構件，晶片封裝產生的熱，可以經由焊錫及分立元件有效的傳導至封裝基板，以達到散熱目的。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。
下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
請參閱第1圖，其為依據本發明例示的實施例所繪示的半導體晶片封裝構件的剖面示意圖。如第1圖所示，半導體晶片封裝構件1可以包含一晶片封裝100，透過一呈陣列狀排列的錫球250，直接安裝在一封裝基板200的晶片安裝面200a上。
根據本發明例示的實施例，晶片封裝100可以包含一被成型模料12所包覆環繞的半導體晶片10。半導體晶片10的主動面10a上分佈有複數個輸入/輸出（I/O）墊102，該等輸入/輸出（I/O）墊102未被成型模料12所覆蓋。根據本發明例示的實施例，所述主動面10a係朝下面向封裝基板200。半導體晶片10的非主動面10b可以被成型模料12所覆蓋，但不限於此。
根據本發明例示的實施例，圍繞在半導體晶片10周圍的成型模料12的一表面係大致上與主動面10a齊平。在周圍的成型模料12與主動面10a上，形成有一重佈線層（RDL）結構20，藉此扇出I/O墊102。重佈線層結構20包含有至少一介電層120、至少一金屬層110以及位於晶片封裝100的基板側（land side）的重佈接墊112。
設置於封裝基板200的焊接墊212上的錫球250建立起晶片封裝100與封裝基板200之間的電連接。上述組態也就是習知的扇出晶圓級封裝（fan-out wafer level package，FOWLP）組態。
需理解的是，第1圖中顯示的晶片封裝100的結構僅為例示說明。在某些其它實施例中，晶片封裝100可以被未封裝的矽晶片或晶粒（die）所取代。在某些其它實施例中，晶片封裝100可以由多晶粒的晶片封裝取代，例如，由扇出晶圓級封裝或其它類型的晶片封裝所取代。
在某些實施例中，錫球250之間還可以施以一環氧樹脂或樹脂類底膠（圖未示）。在某些實施例中，錫球250可以由銅柱（copper pillar）等連接結構所取代。在某些實施例中，封裝基板200可以由印刷電路板（PCB）所取代。
根據本發明例示的實施例，半導體晶片封裝構件1另包含有至少一分立元件（discrete device）150，安裝在晶片封裝100的基板側。例如， 分立元件150包含但不限於：一基板側電容（land side capacitor）、一去耦合電容（de-coupling capacitor）、一電阻（resistor）或一電感（inductor）。
根據本發明例示的實施例，分立元件150，例如基板側電容，具有一第一連接端151與一第二連接端152，經由重佈線層結構20分別電耦合至VSS 與VDD 電壓。根據本發明例示的實施例，第一連接端151與第二連接端152可藉由焊錫（solder）154分別連結至重佈線層結構20中的對應接墊111。
根據本發明例示的實施例，透過焊錫154，分立元件150的第一連接端151與第二連接端152還被電連結至封裝基板200的對應接墊211。所述接墊211係用於散熱，且可以是虛設接墊（dummy pad）或稱為無功能接墊，此處的虛設接墊可以係指該接墊不與封裝基板上的線路電連接。例如，虛設接墊211可以是完全與封裝基板200上的金屬繞線電性隔離，但不限於此。
根據本發明例示的實施例，虛設接墊211及焊接墊212可以部分被一防焊遮罩202所覆蓋。例如，防焊遮罩202可以覆蓋各個虛設接墊211及各個焊接墊212的一週邊區域，而顯露出各個虛設接墊211及各個焊接墊212的一中央區域。
藉由提供這樣的組態，晶片封裝100產生的熱，可以經由焊錫154及分立元件150有效的傳導至封裝基板200，以達到散熱目的。
第2圖至第4圖例示封裝基板200上的散熱（虛設）接墊211與基板側電容的其它不同態樣。為簡化說明，圖中僅顯示出半導體晶片封裝構件的一些部件，例如，重佈線層結構20、封裝基板200的上半部，以及分立元件150。
如第2圖所示，晶片封裝100上的重佈線層結構20的接墊111係對準封裝基板200上的虛設接墊211。為了避免焊錫154的溢流，在兩個焊接墊211之間的防焊遮罩202上，可以另提供有一凹陷處或溝槽202a。若有施加一底膠，溝槽202a即被底膠所填滿。
如第3圖所示，晶片封裝100上的重佈線層結構20的接墊111同樣對準封裝基板200上的虛設接墊211。為了避免焊錫154的溢流，在兩個接墊111之間的介電層120上，可以另提供有一凹陷處或溝槽120a。若有施加一底膠，溝槽120a即被底膠所填滿。
如第4圖所示，晶片封裝100上的重佈線層結構20的接墊111未對準封裝基板200上的虛設接墊211，而有一些錯位。藉由增加虛設接墊211之間的距離，可以避免焊錫154的溢流。
第5圖繪示的是本發明另一例示性實施例，其中相同的區域、層或元件仍沿用相同的符號來表示。如第5圖所示，根據本發明另一例示的實施例，提供的是一半導體晶片封裝構件1a，其包含一多晶片封裝100a，具有至少兩個半導體晶片30、40並列設置在重佈線層結構20上。半導體晶片30、40分別在其主動面上設置有複數個I/O墊302及I/O墊402。
同樣的，在成型模料12的表面與半導體晶片30、40的主動面上，形成有一重佈線層結構20，藉此扇出I/O墊302及402。重佈線層結構20包含有至少一介電層120、至少一金屬層110以及位於多晶片封裝100a的基板側的重佈接墊112。
半導體晶片封裝構件1a另包含有至少一分立元件150，安裝在多晶片封裝100a的基板側。例如，分立元件150包含但不限於：一基板側電容、一去耦合電容、一電阻或一電感。
根據本發明另一例示的實施例，分立元件150，例如基板側電容，同樣具有一第一連接端151與一第二連接端152，經由重佈線層結構20分別電耦合至VSS 與VDD 電壓。根據本發明另一例示的實施例，第一連接端151與第二連接端152可藉由焊錫154分別連結至重佈線層結構20中的對應接墊111。
根據本發明另一例示的實施例，透過焊錫154，分立元件150的第一連接端151與第二連接端152還電連結至封裝基板200的對應接墊211。所述接墊211係用於散熱，且可以是虛設的接墊。例如，虛設接墊211可以是完全與封裝基板200上的其它金屬繞線電性隔離，但不限於此。
根據本發明另一例示的實施例，虛設接墊211及焊接墊212可以部分被一防焊遮罩202所覆蓋。例如，防焊遮罩202可以覆蓋各個虛設接墊211及各個焊接墊212的一週邊區域，而顯露出各個虛設接墊211及各個焊接墊212的一中央區域。
藉由提供這樣的組態，多晶片封裝100a產生的熱，可以經由焊錫154及分立元件150有效的傳導至封裝基板200達到散熱目的。
第6圖繪示的是本發明又另一例示性實施例，其中相同的區域、層或元件仍沿用相同的符號來表示。如第6圖所示，根據本發明又另一例示的實施例，提供的是一半導體晶片封裝構件1b，其包含一下晶片封裝（lower chip package）100b，具有至少一半導體晶片50，設置在一下重佈線層結構20a上。半導體晶片50在其主動面上設置有複數個I/O墊502。下重佈線層結構20a可以形成在半導體晶片50的主動面上以及周圍的成型模料12上，以扇出I/O墊502。下重佈線層結構20a可以包含至少一介電層120、至少一金屬層110以及位於下晶片封裝100b的基板側的重佈接墊112。
在下晶片封裝100b的上方，堆疊有一上晶片封裝100c，其中下晶片封裝100b與上晶片封裝100c共同構成一封裝上封裝（package-on-package；PoP）500。上晶片封裝100c可以包含至少一半導體晶片60，其被成型模料13所包覆。舉例來說，半導體晶片60可以是一記憶體晶片，例如一動態隨機存取記憶體晶片（DRAM chip），但不限於此。上晶片封裝100c可以透過複數個錫球350以及複數個穿模導孔（through mold vias，TMV）420與下晶片封裝100b電連接。另外，還可選擇在上晶片封裝100c與下晶片封裝100b之間另形成一上重佈線層結構20b。
半導體晶片封裝構件1b同樣包含有至少一分立元件150，安裝在封裝上封裝500的基板側。例如，分立元件150包含但不限於：一基板側電容、一去耦合電容、一電阻或一電感。
根據本發明另一例示的實施例，分立元件150，例如基板側電容，同樣具有一第一連接端151與一第二連接端152，經由下重佈線層結構20a分別電耦合至VSS 與VDD 電壓。根據本發明另一例示的實施例，第一連接端151與第二連接端152可藉由焊錫154分別連結至下重佈線層結構20a中的對應接墊111。
根據本發明另一例示的實施例，透過焊錫154，分立元件150的第一連接端151與第二連接端152還電連結至封裝基板200的對應接墊211。所述接墊211係用於散熱，且可以是虛設的接墊。例如，虛設接墊211可以是完全與封裝基板200上的其它金屬繞線電性隔離，但不限於此。
虛設接墊211及焊接墊212可以部分被一防焊遮罩202所覆蓋。例如，防焊遮罩202可以覆蓋各個虛設接墊211及各個焊接墊212的一週邊區域，而顯露出各個虛設接墊211及各個焊接墊212的一中央區域。
藉由提供這樣的組態，封裝上封裝500產生的熱，可以經由焊錫154及分立元件150有效的傳導至封裝基板200達到散熱目的。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧半導體晶片封裝構件 1a‧‧‧半導體晶片封裝構件 1b‧‧‧半導體晶片封裝構件 10‧‧‧半導體晶片 10a‧‧‧主動面 10b‧‧‧非主動面 12‧‧‧成型模料 13‧‧‧成型模料 20‧‧‧重佈線層結構 20a‧‧‧下重佈線層結構 20b‧‧‧上重佈線層結構 30‧‧‧半導體晶片 40‧‧‧半導體晶片 50‧‧‧半導體晶片 60‧‧‧半導體晶片 100‧‧‧晶片封裝 100a‧‧‧多晶片封裝 100b‧‧‧下晶片封裝 100c‧‧‧上晶片封裝 102‧‧‧輸出/輸入（I/O）墊 110‧‧‧金屬層 111‧‧‧接墊（虛設接墊） 112‧‧‧重佈接墊 120‧‧‧介電層 120a‧‧‧溝槽 150‧‧‧分立元件 151‧‧‧第一連接端 152‧‧‧第二連接端 154‧‧‧焊錫 200‧‧‧封裝基板 200a‧‧‧晶片安裝面 202‧‧‧防焊遮罩 202a‧‧‧溝槽 211‧‧‧接墊 212‧‧‧焊接墊 250‧‧‧錫球 302‧‧‧I/O墊 350‧‧‧錫球 402‧‧‧I/O墊 420‧‧‧穿模導孔 500‧‧‧封裝上封裝 502‧‧‧I/O墊
所附圖式係提供用以方便對本發明更進一步的了解，其構成本說明書的一部分。所附圖式與說明書內容一同闡述之本發明實施例，有助於解釋本發明的原理原則。在圖式中： 第1圖為依據本發明例示的實施例所繪示的半導體晶片封裝構件的剖面示意圖； 第2圖至第4圖例示封裝基板上的散熱（虛設）接墊與基板側（land side）電容的其它不同態樣； 第5圖是依據本發明另一例示性實施例所繪示的半導體晶片封裝構件的剖面示意圖；及 第6圖是依據本發明又另一例示性實施例所繪示的半導體晶片封裝構件的剖面示意圖。
1‧‧‧半導體晶片封裝構件
10‧‧‧半導體晶片
10a‧‧‧主動面
10b‧‧‧非主動面
12‧‧‧成型模料
20‧‧‧重佈線層結構
100‧‧‧晶片封裝
102‧‧‧輸出/輸入(I/O)墊
110‧‧‧金屬層
111‧‧‧接墊
112‧‧‧重佈接墊
120‧‧‧介電層
150‧‧‧分立元件
151‧‧‧第一連接端
152‧‧‧第二連接端
154‧‧‧焊錫
200‧‧‧封裝基板
200a‧‧‧晶片安裝面
202‧‧‧防焊遮罩
211‧‧‧接墊(虛設接墊)
212‧‧‧焊接墊
250‧‧‧錫球

Claims (14)

  1. 一種半導體晶片封裝構件，包含有： 一基板，具有一晶片安裝面； 複數個焊接墊，設於該晶片安裝面上； 一第一虛設接墊，設於該晶片安裝面上； 一第二虛設接墊，與該第一虛設接墊間隔開，並且設於該晶片安裝面上； 一防焊遮罩，設於該晶片安裝面上，並部分覆蓋該等焊接墊、該第一虛設接墊與該第二虛設接墊； 一晶片封裝，安裝在該晶片安裝面上，並透過設於該等焊接墊上的複數個錫球電連接該基板； 一分立元件，設於該晶片封裝與該基板之間，該分立元件具有一第一連接端與一第二連接端； 一第一焊錫，將該第一連接端、該第一虛設接墊與該晶片封裝連接起來；以及 一第二焊錫，將該第二連接端、該第二虛設接墊與該晶片封裝連接起來。
  2. 如申請專利範圍第1項所述的半導體晶片封裝構件，其中該基板包含一封裝基板或一印刷電路板。
  3. 如申請專利範圍第1項所述的半導體晶片封裝構件，其中該第一連接端係經由該第一焊錫電連接至該晶片封裝上的一第一接墊。
  4. 如申請專利範圍第3項所述的半導體晶片封裝構件，其中該第二連接端係經由該第二焊錫電連接至該晶片封裝上的一第二接墊。
  5. 如申請專利範圍第4項所述的半導體晶片封裝構件，其中該第一接墊係對準該第一虛設接墊，該第二接墊係對準該第二虛設接墊。
  6. 如申請專利範圍第4項所述的半導體晶片封裝構件，其中該第一接墊未對準該第一虛設接墊，該第二接墊未對準該第二虛設接墊。
  7. 如申請專利範圍第1項所述的半導體晶片封裝構件，其中該分立元件包含一基板側電容、一去耦合電容、一電阻或一電感。
  8. 如申請專利範圍第1項所述的半導體晶片封裝構件，其中在該防焊遮罩中另設有一溝槽，介於該第一虛設接墊與該第二虛設接墊之間。
  9. 如申請專利範圍第4項所述的半導體晶片封裝構件，其中該晶片封裝包含有一半導體晶片，其具有一主動面、一成型模料圍繞該半導體晶片、一重佈線層結構，設於該主動面上以及該成型模料上。
  10. 如申請專利範圍第9項所述的半導體晶片封裝構件，其中該重佈線層結構包含有至少一介電層、至少一金屬層、重佈接墊、該第一接墊與該第二接墊。
  11. 如申請專利範圍第10項所述的半導體晶片封裝構件，其中該介電層中另設有一溝槽，介於該第一接墊與該第二接墊之間。
  12. 如申請專利範圍第1項所述的半導體晶片封裝構件，其中該晶片封裝為一多晶片封裝，該多晶片封裝包含有一重佈線層結構、至少兩個並列設置在該重佈線層結構上的半導體晶片、以及一成型模料，該成型模料覆蓋該至少兩個半導體晶片以及該重佈線層結構。
  13. 如申請專利範圍第1項所述的半導體晶片封裝構件，其中該晶片封裝為一封裝上封裝，該封裝上封裝包含有一下晶片封裝以及一上晶片封裝，該上晶片封裝堆疊在該下晶片封裝上。
  14. 如申請專利範圍第13項所述的半導體晶片封裝構件，其中該封裝上封裝包含有一下重佈線層結構以及一成型模料，該第一焊錫與該第二焊錫係電連接至該下重佈線層結構，該成型模料覆蓋該下晶片封裝內的一晶片以及該下重佈線層結構的一表面。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10096552B2 (en) 2017-01-03 2018-10-09 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
TWI658553B (zh) * 2017-01-03 2019-05-01 Samsung Electronics Co., Ltd. 扇出型半導體封裝
TWI709211B (zh) * 2018-03-13 2020-11-01 南韓商三星電子股份有限公司 扇出型組件封裝
TWI795059B (zh) * 2020-12-22 2023-03-01 聯發科技股份有限公司 半導體裝置

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
KR20170085833A (ko) * 2016-01-15 2017-07-25 삼성전기주식회사 전자 부품 패키지 및 그 제조방법
JP6716967B2 (ja) * 2016-03-04 2020-07-01 富士ゼロックス株式会社 半導体パッケージ及び半導体パッケージの製造方法
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10541226B2 (en) * 2016-07-29 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US10229859B2 (en) * 2016-08-17 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10756042B2 (en) * 2016-12-26 2020-08-25 Intel IP Corporation Multi-layer redistribution layer for wafer-level packaging
US10283474B2 (en) * 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10157862B1 (en) * 2017-07-27 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10566261B2 (en) 2017-11-15 2020-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages with embedded heat dissipation structure
WO2019133008A1 (en) * 2017-12-30 2019-07-04 Intel Corporation Ultra-thin, hyper-density semiconductor packages
JP7271094B2 (ja) * 2018-06-19 2023-05-11 キオクシア株式会社 半導体記憶装置
KR20200007509A (ko) 2018-07-13 2020-01-22 삼성전자주식회사 반도체 패키지
US11114400B2 (en) * 2018-09-06 2021-09-07 Amkor Technology Singapore Holding Pte.Ltd. Semiconductor device with improved thermal dissipation and manufacturing methods
US11728238B2 (en) * 2019-07-29 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with heat dissipation films and manufacturing method thereof
JP2021044477A (ja) * 2019-09-13 2021-03-18 キオクシア株式会社 半導体記憶装置
CN113555351B (zh) * 2020-04-23 2024-02-06 瑞昱半导体股份有限公司 半导体封装

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW523857B (en) * 2001-12-06 2003-03-11 Siliconware Precision Industries Co Ltd Chip carrier configurable with passive components
DE10317018A1 (de) 2003-04-11 2004-11-18 Infineon Technologies Ag Multichipmodul mit mehreren Halbleiterchips sowie Leiterplatte mit mehreren Komponenten
US6884939B2 (en) * 2003-06-18 2005-04-26 Intel Corporation Constructing of an electronic assembly having a decoupling capacitor
US8174116B2 (en) * 2007-08-24 2012-05-08 Nec Corporation Spacer, and its manufacturing method
US9607935B2 (en) * 2009-04-21 2017-03-28 Ati Technologies Ulc Semiconductor chip package with undermount passive devices
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US8736065B2 (en) 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
WO2013052320A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US9263186B2 (en) 2013-03-05 2016-02-16 Qualcomm Incorporated DC/ AC dual function Power Delivery Network (PDN) decoupling capacitor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10096552B2 (en) 2017-01-03 2018-10-09 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
TWI658553B (zh) * 2017-01-03 2019-05-01 Samsung Electronics Co., Ltd. 扇出型半導體封裝
TWI709211B (zh) * 2018-03-13 2020-11-01 南韓商三星電子股份有限公司 扇出型組件封裝
TWI795059B (zh) * 2020-12-22 2023-03-01 聯發科技股份有限公司 半導體裝置

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