TWI702703B - 半導體封裝元件 - Google Patents

半導體封裝元件 Download PDF

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Publication number
TWI702703B
TWI702703B TW106106100A TW106106100A TWI702703B TW I702703 B TWI702703 B TW I702703B TW 106106100 A TW106106100 A TW 106106100A TW 106106100 A TW106106100 A TW 106106100A TW I702703 B TWI702703 B TW I702703B
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pad
memory chip
coupled
redistribution layer
semiconductor package
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TW106106100A
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TW201806111A (zh
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林聖謀
何敦逸
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聯發科技股份有限公司
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Publication of TW201806111A publication Critical patent/TW201806111A/zh
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Abstract

本發明提供半導體封裝元件。該半導體封裝元件包括：基板；位於該基板上的第一襯墊和第二襯墊；安裝在該基板上的邏輯晶片，該邏輯晶片包括耦接於該第二襯墊的第一邏輯晶片襯墊；安裝在該基板上的記憶體晶片，該記憶體晶片包括第一記憶體晶片襯墊和第一再分配層走線；其中，該第一再分配層走線包括第一端和第二端，該第一端通過該第一記憶體晶片襯墊耦接於該第一襯墊，該第二端耦接於該第二襯墊而非該第一襯墊。

Description

半導體封裝元件
本發明係有關於半導體技術領域，特別係有關於半導體封裝元件結構。
為了確保電子產品和通信設備的小型化和多功能，期望半導體封裝具有小的尺寸，以支持多針(mluti-pin)連接、高速率以及高功能。多功能系統級封裝(System In Package，SIP)通常要求集成離散的邏輯晶片(logic die)和記憶體晶片(memory die)。該記憶體晶片通常使用較長的再分配層(Redistribution Layer，RDL)接地走線作為該記憶體晶片和該邏輯晶片的連接。但是，在用於無線頻率應用的系統級封裝設計時，該較長的再分配層接地走線帶來不期望的信號完整性問題和雜訊耦合問題。
因此，需要一種新型的半導體封裝元件。
本發明提供半導體封裝元件結構，可在記憶體晶片的再分配層走線長度較長時，改善信號的完整性和減少耦合雜訊。
本發明實施例提供的一種半導體封裝元件，可包括：基板；位於該基板上的第一襯墊和第二襯墊；安裝在該基 板上的邏輯晶片，該邏輯晶片包括耦接於該第二襯墊的第一邏輯晶片襯墊；安裝在該基板上的記憶體晶片，該記憶體晶片包括第一記憶體晶片襯墊和第一再分配層走線；其中，該第一再分配層走線包括第一端和第二端，該第一端通過該第一記憶體晶片襯墊耦接於該第一襯墊，該第二端耦接於該第二襯墊而非該第一襯墊；其中，該第一襯墊和該第二襯墊為接地襯墊。在該種半導體封裝元件中，記憶體晶片的第一再分配層走線的第一端和第二端分別耦接於基板的第一接地襯墊(第一襯墊)和第二接地襯墊(第二襯墊)，由此，當該記憶體晶片的再分配層走線長度較長時，該設計可通過降低串音缺陷來改善信號的完整性。而當該半導體封裝元件的邏輯晶片中包括射頻電路用於射頻應用，該記憶體晶片的再分配層走線同樣可以通過減少該記憶體晶片的電路和該邏輯晶片的射頻電路之間的耦合雜訊來改善射頻靈敏度問題。
本發明實施例提供的另一種半導體封裝元件，可包括：基板；位於該基板上的第一襯墊和第二襯墊；安裝在該基板上的記憶體晶片；以及安裝在該基板上的邏輯晶片；其中，該記憶體晶片包括第一側、第二側、記憶體晶片襯墊以及再分配層走線；其中，該記憶體晶片襯墊靠近該第一側且與該第一襯墊耦接；其中，該再分配層走線包括靠近該第一側的第一端和靠近該第二側的第二端，該第一端通過該記憶體晶片襯墊耦接於該第一襯墊，該第二端通過第一單導電路徑耦接於靠近該第二側的該第二襯墊；其中，該邏輯晶片包括邏輯晶片襯墊，該邏輯晶片襯墊靠近該第二側，且與該第二襯墊耦接；其中， 該第一襯墊和該第二襯墊為接地襯墊。類似第一種半導體封裝元件，在該種半導體封裝元件中，記憶體晶片的再分配層走線的第一端和第二端分別耦接於基板的第一接地襯墊(第一襯墊)和第二接地襯墊(第二襯墊)，由此，當該記憶體晶片的再分配層走線長度較長時，該設計可通過降低串音缺陷來改善信號的完整性。而當該半導體封裝元件的邏輯晶片中包括射頻電路用於射頻應用，該記憶體晶片的再分配層走線同樣可以通過減少該記憶體晶片的電路和該邏輯晶片的射頻電路之間的耦合雜訊來改善射頻靈敏度問題。
本發明實施例提供的再一種半導體封裝元件，可包括：基板；位於該基板上的第一接地襯墊和第二接地襯墊；安裝在該基板上的記憶體晶片；以及安裝在該基板上的邏輯晶片；其中，該記憶體晶片包括記憶體接地襯墊以及再分配層接地走線；其中，該記憶體接地襯墊耦接於該第一接地襯墊；其中，該再分配層走線包括第一端和第二端，該第一端通過包括該記憶體接地襯墊的第一導電路徑耦接於該第一接地襯墊，該第二端通過不與該記憶體接地走線耦接的第二導電路徑耦接於該第二接地襯墊；其中，該邏輯晶片包括邏輯接地襯墊，該邏輯接地襯墊通過該第二接地襯墊耦接於該第二端。類似第一種半導體封裝元件，在該種半導體封裝元件中，記憶體晶片的再分配層接地走線的第一端和第二端分別耦接於基板的第一接地襯墊和第二接地襯墊，由此，當該記憶體晶片的再分配層走線長度較長時，該設計可通過降低串音缺陷來改善信號的完整性。而當該半導體封裝元件的邏輯晶片中包括射頻電路用於 射頻應用，該記憶體晶片的再分配層走線同樣可以通過減少該記憶體晶片的電路和該邏輯晶片的射頻電路之間的耦合雜訊來改善射頻靈敏度問題。
100a，100b‧‧‧半導體晶片(邏輯晶片)
500a，500b，500c，500d，500e‧‧‧半導體封裝元件
360‧‧‧射頻單元
701‧‧‧晶片粘接表面
700‧‧‧基板
260‧‧‧第二再分配層信號走線
262‧‧‧第二再分配層信號走線260的第三端
264‧‧‧第二再分配層信號走線260的第四端
102，104，150a，150b，152，250a，250b，252a‧‧‧襯墊
300a，310a，320a，320b，330，340‧‧‧導電路徑
200a，200b‧‧‧半導體晶片(記憶體晶片)
240‧‧‧再分配層接地走線
242‧‧‧再分配層接地走線240的第一端
244‧‧‧再分配層接地走線240的第二端
220‧‧‧記憶體晶片200a的第一側
222‧‧‧記憶體晶片200a的第二側
110，210‧‧‧輸入/輸出襯墊範圍
160，266，268，710，720‧‧‧導電結構
750‧‧‧成型材料
112，212‧‧‧糊狀物
270a‧‧‧再分配層結構
800‧‧‧基礎
通過閱讀後續的詳細描述和實施例可以更全面地理解本發明，該實施例參照附圖給出，其中：
第1圖為依據本發明的一些實施例的半導體封裝元件500a和500b的俯視圖。
第2圖為依據本發明的一些實施例的半導體封裝結構500c的俯視圖。
第3圖~第4圖為第1圖的剖面圖，示出第1圖中的半導體封裝元件的基板、邏輯晶片、記憶體晶片以及該記憶體晶片的再分配層接地走線的佈局。
第5圖為依據本發明的一些實施例的半導體封裝元件500d和500e的俯視圖。
第6圖~第7圖為第5圖的截面圖，示出第5圖中的半導體封裝元件的基板、邏輯晶片、記憶體晶片以及該記憶體晶片的再分配層接地走線的佈局。
以下描述為本發明實施的較佳實施例。以下實施例僅用來例舉闡釋本發明的技術特徵，並非用來限制本發明的範疇。在通篇說明書及申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域技術人員應可理解，製造商可能會用不 同的名詞來稱呼同樣的元件。本說明書及申請專利範圍並不以名稱的差異來作為區別元件的方式，而是以元件在功能上的差異來作為區別的基準。本發明的範圍應當參考後附的申請專利範圍來確定。本發明中使用的術語“元件”、“系統”和“裝置”可以是與電腦相關的實體，其中，該電腦可以是硬體、軟體、或硬體和軟體的結合。在以下描述和申請專利範圍當中所提及的術語“包含”和“包括”為開放式用語，故應解釋成“包含，但不限定於...”的意思。此外，術語“耦接”意指間接或直接的電氣連接。因此，若文中描述一個裝置耦接至另一裝置，則代表該裝置可直接電氣連接於該另一裝置，或者透過其它裝置或連接手段間接地電氣連接至該另一裝置。
本發明實施例提供了半導體封裝元件。該半導體封裝元件為系統級封裝。該半導體封裝元件包括至少一個邏輯晶片和至少一個記憶體晶片。該記憶體晶片包括再分配層接地走線，該再分配層接地走線包括朝向相反的兩個端子。該兩個端子中的其中一個設計為靠近該記憶體晶片的接地襯墊(pad)並耦接於該接地襯墊。該兩個端子中的另一個耦接於基板接地襯墊。該半導體封裝組件設計為增加該再分配層接地走線的兩個端子的接地點，以避免具有較長的長度的該再分配層接地走線的兩個端子之間的電勢差(potential different)。此外，該再分配層接地走線的額外的接地點可減少該較長的再分配層接地走線造成的射頻干擾(interference)。
第1圖為依據本發明的一些實施例的半導體封裝元件500a和500b的俯視圖(plan view)。第3圖-第4圖為 第1圖的剖面圖，示出第1圖中的半導體封裝元件的基板、邏輯晶片、記憶體晶片以及該記憶體晶片的再分配層接地走線的佈局。為了清楚地展示半導體封裝元件500a和500b的基板、邏輯晶片、記憶體晶片以及該記憶體晶片的再分配層接地走線的佈局，第1圖中省略了成型材料。
如第1圖及第3圖所示，半導體封裝元件500a通過多個導電結構710安裝在基礎800上。在一些實施例中，半導體封裝元件500a為系統級封裝。在一些實施例中，該基礎800可包括印刷電路板(Printed Circuit Board，PCB)。導電結構710可包括導電凸塊(bump)結構，例如，銅凸塊、焊錫球結構、焊錫凸塊結構、導電柱結構、導線結構或者導電膏中任一種。半導體封裝元件500a包括基板700、半導體晶片(邏輯晶片)100a、半導體晶片(記憶體晶片)200a以及記憶體晶片200a的再分配層接地走線240。需要注意的是，基板700、邏輯晶片100a以及記憶體晶片200a為半導體封裝元件500a的離散的，獨立的組件。
第1圖和第3圖提供了基板700。基板700包括晶片粘接表面701用於安裝邏輯晶片100a和記憶體晶片200a。基板700包括靠近晶片粘接表面701設置的多個離散的接地襯墊102和104。在一些實施例中，接地襯墊102和104用於將輸入/輸出連接至地。因此，接地襯墊102和104同時作為基板700的接地襯墊。基板700還包括形成在其內部且耦接於接地襯墊102和104的互連(未圖示)。在一些實施例中，基板700可包括半導體基板，例如，矽基板。在其他一些實施例中， 基板700可包括介電材料，例如，有機材料。在一些實施例中，該有機材料包括帶有玻璃纖維的聚丙烯、環氧樹脂、聚醯亞胺、氰酸酯、其他合適的材料中任一種或者它們的組合。
如第1圖和第3圖所示，半導體晶片100a設置在基板700上。半導體晶片100a可通過半導體晶片100a和基板700之間的粘合劑112(例如，糊狀物)安裝到基板700的晶片粘接表面701。在一些實施例中，半導體晶片100a通過引線接合技術(bonding technology)耦接至基板700。在一些實施例中，如第3圖所示，半導體晶片100a通過包括導線(例如，導線320a)的導體結構耦接至基板700。在一些實施例中，半導體晶片100a可為邏輯晶片100a，該邏輯晶片100a包括中央處理單元、影像處理單元、動態隨機記憶體控制器中任一種，或者它們的組合。
如第1圖和第3圖所示，半導體晶片200a通過半導體晶片100a和200a之間的粘合劑212(例如，糊狀物)直接堆疊安裝在半導體晶片100a上。在一些實施例中，半導體晶片200a可作用為記憶體晶片200a，例如，動態隨機訪問記憶體晶片。在一些實施例中，半導體晶片200a通過引線接合技術耦接至基板700。如第3圖所示，半導體晶片200a通過包括導線(例如，導線300a和310a)的導體結構耦接至基板700。
如第1圖和第3圖所示，記憶體晶片200a可包括記憶體輸入/輸出晶片襯墊202且在記憶體晶片200a的輸入/輸出晶片襯墊202上包括再分配層結構270a。在一些實施例中，記憶體晶片200a可為一個或多個動態隨機記憶體晶片。 再分配層結構270a可包括至少一個再分配層走線240和至少一個襯墊250a。再分配層走線240和襯墊250a用於輸入/輸出連接至地。如第3圖所示，在一些實施例中，再分配層走線240作用為再分配層接地走線240。再分配層走線240設計為位於單層的(single layered-level)再分配層結構270a
Figure 106106100-A0101-12-0008-8
如第3圖所示，在一些實施例中，襯墊250a位於再分配層結構270a的頂部且位於輸入/輸出襯墊區域210內部。襯墊250a作用為記憶體晶片200a的接地襯墊。
再分配層走線240用於將記憶體輸入/輸出晶片襯墊202的接地路徑從襯墊250a處以扇形方式散開至或重新路由至特定的位置(例如，該特定的位置靠近邏輯晶片100a的輸入/輸出襯墊區域110)。記憶體晶片200a的再分配層接地走線240可具有長的長度。如第1圖和第3圖所示，記憶體晶片200a的再分配層接地走線240設計為從記憶體晶片200a的第一側220延伸至記憶體晶片200a的第二側222，以用於連接記憶體晶片200a和邏輯晶片100a。再分配層接地走線240包括第一端242和遠離第一端242的第二端244。第一端242耦接於鄰近的襯墊250a。記憶體晶片200a的襯墊250a耦接於其鄰近的屬於基板700的接地襯墊102。在一些實施例中，再分配層接地走線240的第一端242和記憶體晶片200a的襯墊250a均設置為鄰近記憶體晶片200a的第一側220。基板700的接地襯墊102靠近記憶體晶片200a的第一側220設置。此外，基板700的接地襯墊102靠近記憶體晶片200a的襯墊250a設置，以減小記憶體晶片200a到基板700的接地路徑。
如第1圖和第3圖所示，記憶體晶片200a的襯墊250a通過導電路徑300a(例如，接合線)耦接於接地襯墊102。需要注意的是，導電路徑300a為包括兩端的單接合線，該兩端分別與襯墊250a和接地襯墊102接觸。導電路徑300a不與接地襯墊104接觸。
如第1圖和第3圖所示，再分配層接地走線240的第二端244耦接於基板700的接地襯墊，例如，接地襯墊104而非接地襯墊102。再分配層接地走線240的第二端244耦接於接地襯墊104，而不使用襯墊250a和接地襯墊102。在一些實施例中，再分配層接地走線240的第二端244和接地襯墊104均靠近記憶體晶片200a的第二側222設置。第一側220和第二側222為記憶體晶片200a的不同側。再分配層接地走線240的第二端244通過導電路徑310a(例如，接合線)耦接於接地襯墊104。需要注意的是，導電路徑310a為包括兩端的單接合線，該兩端分別與第二端244和接地襯墊104接觸。導電路徑310a不與接地走線102和接地路徑300a接觸。
如第1圖和第3圖所示，邏輯晶片100a可包括邏輯裝置(未圖示)以及位於該邏輯裝置上的再分配層結構(未圖示)。邏輯晶片100a的再分配層結構可包括至少一個再分配層走線和至少一個襯墊150a，該再分配層結構用於傳輸邏輯裝置的接地信號。如第3圖所示，在一些實施例中，襯墊150a設置在該再分配層結構的頂部。襯墊150a設置在邏輯晶片100a的輸入/輸出襯墊區域110中，且作用為邏輯晶片100a的接地襯墊。
如第1圖和第3圖所示，邏輯晶片100a的襯墊150a僅通過導電路徑320a(例如，接合線)耦接於基板700的接地襯墊104。在一些實施例中，邏輯晶片100a的襯墊150a不與基板700的接地襯墊102耦接。導電路徑300a、310a以及320a為不同的導電路徑。也即，導電路徑320a不與導電路徑300a和310a接觸。
如第1圖所示，第3圖中的半導體晶片200a的再分配層結構270a可包括走線第二再分配層信號走線260和耦接於走線第二再分配層信號走線260的至少一個襯墊252a。在一些實施例中，如第1圖所示，走線第二再分配層信號走線260設計為靠近再分配層接地走線240並與240平行。類似於再分配層接地走線240，記憶體晶片200a的走線第二再分配層信號走線260具有長的長度。記憶體晶片200a的走線第二再分配層信號走線260設計為從記憶體晶片200a的第一側220延伸至第二側222。
走線第二再分配層信號走線260和襯墊252a用於輸入/輸出連接至記憶體輸入/輸出晶片襯墊202的信號。走線第二再分配層信號走線260可作用為再分配層信號走線。走線第二再分配層信號走線260不與基板700的接地襯墊102和104耦接。在一些實施例中，襯墊252a也設置在再分配層結構(例如，第3圖所示的再分配層結構270a)的頂部。襯墊252a作用為記憶體晶片200a的信號襯墊。襯墊252a位於輸入/輸出襯墊範圍210內。此外，襯墊252a靠近襯墊250a但與襯墊250a絕緣。
如第1圖所示，第二再分配層信號走線260包括第三端262和遠離第三端262的第四端264。第二再分配層信號走線260的第三端262位於再分配層接地走線240的第一端242旁邊。此外，第二再分配層信號走線260的第四端264位於再分配層接地走線240的第二端244旁邊。第三端262耦接於其附近的襯墊252a。記憶體晶片200a的襯墊252a耦接於基板700的相應的信號襯墊(未圖示)。第二再分配層信號走線260通過基板700的導電路徑330、340和導電結構720耦接於邏輯晶片100a的襯墊152。在一些實施例中，導電路徑330和340可包括接合線。基板700的導電結構720可包括電路和襯墊。
如第1圖所示，在一些實施例中，邏輯晶片100a的襯墊152靠近襯墊150a但是與150a電隔離。襯墊152可作用為邏輯晶片100a的信號襯墊。
如第3圖所示，半導體封裝元件500a進一步包括圍繞邏輯晶片100a、記憶體晶片200a以及導電路徑(包括導電路徑300a、310a以及320a)的成型材料(molding compound)750。成型材料750與邏輯晶片100a、記憶體晶片200a以及導電路徑300a、310a以及320a接觸。成型材料750還覆蓋基板700的晶片附著表面701。在一些實施例中，成型材料750可由非導電材料形成，例如，環氧樹脂、樹脂、可塑造的聚合物，以及它們的類似物。成型材料750剛提供時可為流體的，然後通過化學反應處理，例如環氧樹脂、樹脂。在另一些實施例中，成型材料750可為紫外線或熱處理後的聚合物用作為可設置在 邏輯晶片100a和記憶體晶片200a周圍的膠體或可伸縮的固體，並隨時可被紫外線或熱處理流程處理。成型材料750可使用模具進行處理。
第4圖為第1圖的截面圖，示出半導體封裝元件500b的基板、邏輯晶片、記憶體晶片以及該記憶體晶片的再分配層接地走線的佈局。此實施例與前面描述的實施例中相同或者相近的元件請參考第1圖和第3圖，為簡化起見在此將不再重複。半導體封裝元件500b與半導體封裝元件500a的區別為半導體封裝元件500b包括通過倒裝技術設置在基板700上的半導體晶片(邏輯晶片)100b。在一些實施例中，半導體晶片100b可作用為邏輯晶片100b。邏輯晶片100b可包括至少一個襯墊150b，用於輸入/輸出連接至地。襯墊150b作用為邏輯晶片100b的接地襯墊。如第1圖所示，襯墊150b設置在輸入/輸出襯墊區域110內。
如第4圖所示，邏輯晶片100b是倒裝的，並通過導電結構160耦接於基板700。導電結構160設置在襯墊150b上。導電結構160可包括耦接於相應的襯墊150b的至少一個凸塊結構。導電凸塊結構可包括銅凸塊、焊錫球結構、焊錫凸塊結構、導電柱結構、導線結構或者導電膏結構中任一種。邏輯晶片100b的襯墊150b通過互連320b(例如，基板700中嵌入的電路)耦接於基板700的接地襯墊104。
第2圖為依據本發明的一些實施例的半導體封裝結構500c的俯視圖。此實施例與前面描述的實施例中相同或者相近的元件請參考第1圖、第3圖以及第4圖，為簡化起見 在此將不再重複。半導體封裝元件500c與半導體封裝元件500a/500b的區別為半導體封裝元件500c的半導體晶片(邏輯晶片)100a/100b還包括集成在該半導體晶片(邏輯晶片)100a/100b中的至少一個射頻單元360，用於射頻應用。
第5圖為依據本發明的一些實施例的半導體封裝元件500d和500e的俯視圖。第6圖-第7圖為第5圖的截面圖，示出第5圖中的半導體封裝元件的基板、邏輯晶片、記憶體晶片以及該記憶體晶片的再分配層接地走線的佈局。為簡潔地示出半導體封裝元件500d和500e的基板、邏輯晶片、記憶體晶片以及該記憶體晶片的再分配層接地走線的佈局，在第5圖中未示出成型材料。此實施例與前面描述的實施例中相同或者相近的元件請參考第1圖-第4圖，為簡化起見在此將不再重複。
如第5圖和第6圖所示，半導體封裝元件500d和第1圖-第3圖中的半導體封裝元件500a/500b的區別為記憶體晶片200a設置在邏輯晶片100a旁邊。因此，記憶體晶片200a和邏輯晶片100a分別通過糊狀物212和112安裝在晶片附著表面701上。
如第6圖所示，在一些實施例中，邏輯晶片100a通過引線結合技術耦接於邏輯晶片100a。半導體晶片100a可通過半導體晶片100a和基板700之間的粘合劑112(例如，糊狀物)安裝在基板700的晶片附著表面701上。
如第5圖和第6圖所示，在一些實施例中，再分配層接地走線240的第一端242、記憶體晶片200a的襯墊250a 以及基板700的接地襯墊102靠近記憶體晶片200a的第一側220設置。再分配層接地走線240的第二端244、邏輯晶片100a的襯墊150a和接地走線104均靠近記憶體晶片200a的第二側222設置。此外，如第6圖所示，接地襯墊104設置在邏輯晶片100a和記憶體晶片200a之間。
第7圖為第5圖的截面圖，示出第5圖中的半導體封裝元件500e的基板、邏輯晶片、記憶體晶片以及該記憶體晶片的再分配層接地走線的佈局。此實施例與前面描述的實施例中相同或者相近的元件請參考第5圖-第6圖，為簡化起見在此將不再重複。半導體封裝元件500e與半導體封裝元件500d的區別為半導體封裝元件500e包括通過倒裝晶片技術設置在基板700上的半導體晶片100b和半導體晶片200b。在一些實施例中，半導體晶片100b作用為邏輯晶片100b、半導體晶片200b作用為記憶體晶片200b。
如第7圖所示，邏輯晶片100b可包括至少一個襯墊150b，用於輸入/輸出連接至地。襯墊150b作用為邏輯晶片100b的接地襯墊。
記憶體晶片200b可包括記憶體輸入/輸出晶片襯墊202和位於記憶體輸入/輸出晶片襯墊202上的再分配層結構270b。再分配層結構270b可包括至少一個再分配層走線240和至少兩個襯墊250b和250c。再分配層走線240和襯墊250b和250c用於輸入/輸出連接至地。如第7圖所示，在一些實施例中，再分配層結構240作用為再分配層接地走線240。再分配層走線240設計為位於再分配層結構270b的單一水平面 上。再分配層走線240的兩端242和244分別耦接於襯墊250b和250c。襯墊250b和250c作用為記憶體晶片200a的接地襯墊。如第5圖所示，襯墊250b設置在輸入/輸出襯墊區域210內。襯墊250c設置在輸入/輸出襯墊區域210外。例如，襯墊250c靠近再分配層走線240的端244設置。此外，襯墊250b不與襯墊250c接觸。
如第7圖所示，記憶體晶片200b上下倒裝，且通過導電結構266和268耦接於基板700。導電結構266和268分別設置在襯墊250b和250c上。導電結構266和268可包括耦接於襯墊250b和250c的相應的導電凸塊。此外，導電結構266不與導電結構268接觸。記憶體晶片200b的接地襯墊250b通過導電結構266和互連300b耦接於基板700的接地襯墊102。記憶體晶片200b的襯墊250c通過導電結構268和嵌入在基板700中的互連320b耦接於基板700的接地襯墊104。在一些實施例中，互連300b和320b嵌入在基板700中。互連300b和320b可包括多個電路。
如第7圖所示，邏輯晶片100b上下倒裝，且通過導電結構160耦接於基板700。導電結構160設置在襯墊150b上。導電結構160可包括耦接於襯墊150b的相應的導電凸塊結構。邏輯晶片100b的襯墊150b通過導電結構160和基板700的互連320b耦接於基板700的接地襯墊104。也即，互連320b與記憶體晶片200b的襯墊250c、邏輯晶片100b的襯墊150b以及基板700的接地襯墊104電連接。此外，互連300b和320b為離散的電路。互連300b不與互連320b接觸。
實施例提供了半導體封裝元件。該半導體封裝元件包括基板、位於基板上的記憶體晶片和邏輯晶片。該記憶體晶片包括再分配層接地走線，該再分配層接地走線包括第一端和遠離該第一端的第二端。該第一端和第二端分別靠近該記憶體晶片的不同側。該再分配層接地走線的該第一端通過包含該記憶體晶片的一個襯墊的第一導電路徑耦接於該基板的第一接地襯墊，該第一接地襯墊設置在一個輸入/輸出襯墊範圍內。該再分配層接地走線的第二端通過與該第一導電路徑不同的第二導電路徑耦接於該基板的第二接地襯墊。該第二導電路徑不與該記憶體的該襯墊耦接。該邏輯晶片包括通過該基板的該第二接地襯墊耦接於該再分配層的第二端的襯墊。
本發明的半導體封裝元件設計為在該記憶體晶片的再分配層走線的兩端包括接地路徑。如果該記憶體晶片的再分配層接地走線長度較長，再分配層接地走線的設計可通過降低串音缺陷來改善信號的完整性。如果該半導體封裝元件的邏輯晶片中包括射頻電路用於射頻應用，該記憶體晶片的再分配層接地走線同樣可以通過減少該記憶體晶片的電路和該邏輯晶片的射頻電路之間的耦合雜訊來改善射頻靈敏度問題。
申請專利範圍書中用以修飾元件的“第一”、“第二”等序數詞的使用本身未暗示任何優先權、優先次序、各元件之間的先後次序、或所執行方法的時間次序，而僅用作標識來區分具有相同名稱(具有不同序數詞)的不同元件。
儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的是，在不脫離本發明的精神以及申請專利範 圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。
100a，100b‧‧‧半導體晶片(邏輯晶片)
500a，500b‧‧‧半導體封裝元件
701‧‧‧晶片粘接表面
700‧‧‧基板
260‧‧‧第二再分配層信號走線
262‧‧‧第二再分配層信號走線260的第三端
264‧‧‧第二再分配層信號走線260的第四端
102，104，150a，150b，152，250a，252a‧‧‧襯墊
300a，310a，320a，320b，330，340‧‧‧導電路徑
200a‧‧‧半導體晶片(記憶體晶片)
240‧‧‧再分配層接地走線
242‧‧‧再分配層接地走線240的第一端
244‧‧‧再分配層接地走線240的第二端
220‧‧‧記憶體晶片200a的第一側
222‧‧‧記憶體晶片200a的第二側
110，210‧‧‧輸入/輸出襯墊範圍
720‧‧‧導電結構

Claims (18)

  1. 一種半導體封裝元件，包括：基板；位於該基板上的第一襯墊和第二襯墊；安裝在該基板上的邏輯晶片，該邏輯晶片包括耦接於該第二襯墊的第一邏輯晶片襯墊；安裝在該基板上的記憶體晶片，該記憶體晶片包括第一記憶體晶片襯墊和第一再分配層走線；其中，該第一再分配層走線包括第一端和第二端，該第一端通過該第一記憶體晶片襯墊耦接於該第一襯墊，該第二端耦接於該第二襯墊而非該第一襯墊；該記憶體晶片進一步包括：第二再分配層信號走線，包括第三端和第四端，其中，該第三端耦接於該記憶體晶片的第二記憶體晶片襯墊，該第四端耦接於該邏輯晶片的第二邏輯晶片襯墊；其中，該第一襯墊和該第二襯墊為接地襯墊。
  2. 如申請專利範圍1的半導體封裝元件，該第一記憶體晶片襯墊和該第一襯墊均靠近該記憶體晶片的第一側設置。
  3. 如申請專利範圍2的半導體封裝元件，該第一邏輯晶片襯墊和該第二襯墊靠近該記憶體晶片的第二側設置，其中，該第二側與該第一側不同。
  4. 如申請專利範圍1的半導體封裝元件，該第一記憶體晶片襯墊通過第一導電路徑耦接於該第一襯墊。
  5. 如申請專利範圍4的半導體封裝元件，該第二端通過第二 導電路徑耦接於該第二端。
  6. 如申請專利範圍5的半導體封裝元件，該第一邏輯晶片通過第三導電路徑耦接於該第一邏輯晶片襯墊，其中，該第三導電路徑不同於該第一導電路徑和該第二導電路徑。
  7. 如申請專利範圍1的半導體封裝元件，該第一再分配層走線為接地走線。
  8. 如申請專利範圍1的半導體封裝元件，該第一再分配層走線設置在單層結構上。
  9. 如申請專利範圍1的半導體封裝元件，該記憶體晶片直接位於該邏輯晶片上；或者該記憶體晶片設置在該邏輯晶片旁邊。
  10. 如申請專利範圍1的半導體封裝元件，該第二記憶體晶片襯墊與該第一記憶體晶片襯墊隔離，該第二邏輯晶片襯墊與該第一邏輯晶片襯墊隔離。
  11. 如申請專利範圍1的半導體封裝元件，該走線第二再分配層信號走線不與該第一襯墊或該第二襯墊耦接。
  12. 如申請專利範圍1的半導體封裝元件，該第四端通過該基板的導電結構耦接於該第二邏輯晶片襯墊。
  13. 如申請專利範圍1的半導體封裝元件，該走線第二再分配層信號走線為單走線。
  14. 一種半導體封裝元件，包括：基板；位於該基板上的第一襯墊和第二襯墊；安裝在該基板上的記憶體晶片；以及 安裝在該基板上的邏輯晶片；其中，該記憶體晶片包括第一側、第二側、記憶體晶片襯墊以及再分配層走線；其中，該記憶體晶片襯墊靠近該第一側且與該第一襯墊耦接；其中，該再分配層走線包括靠近該第一側的第一端和靠近該第二側的第二端，該第一端通過該記憶體晶片襯墊耦接於該第一襯墊，該第二端通過第一單導電路徑耦接於靠近該第二側的該第二襯墊；該記憶體晶片進一步包括：第二再分配層信號走線，包括第三端和第四端，其中，該第三端耦接於該記憶體晶片的第二記憶體晶片襯墊，該第四端耦接於該邏輯晶片的第二邏輯晶片襯墊；其中，該邏輯晶片包括邏輯晶片襯墊，該邏輯晶片襯墊靠近該第二側，且與該第二襯墊耦接；其中，該第一襯墊和該第二襯墊為接地襯墊。
  15. 如申請專利範圍14的半導體封裝元件，該第一單導電路徑不與該第一襯墊接觸。
  16. 如申請專利範圍15的半導體封裝元件，該記憶體晶片襯墊通過不與該第一單導電路徑接觸的第二單導電路徑耦接於該第一襯墊。
  17. 如申請專利範圍16的半導體封裝元件，該邏輯晶片襯墊耦接於該第二襯墊而非該第一襯墊。
  18. 如申請專利範圍17的半導體封裝元件，該邏輯晶片襯墊通 過第三單導電路徑耦接於該第二襯墊，其中，該第三單導電路徑不與該第一單導電路徑和該第二單導電路徑接觸。
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