TWI724510B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI724510B
TWI724510B TW108130442A TW108130442A TWI724510B TW I724510 B TWI724510 B TW I724510B TW 108130442 A TW108130442 A TW 108130442A TW 108130442 A TW108130442 A TW 108130442A TW I724510 B TWI724510 B TW I724510B
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conductor layer
semiconductor
substrate
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TW202034490A (zh
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大塚靖夫
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日商東芝記憶體股份有限公司
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Abstract

根據一個實施形態，實施形態之半導體裝置1具備：配線基板2；間隔基板3，其搭載於配線基板2上，內設有電源導體層7與接地導體層8；至少一個第1半導體晶片4，其等安裝於間隔基板3上，具有與電源導體層7電性連接之電源層及與接地導體層8電性連接之接地層；及第2半導體晶片5，其安裝於配線基板2上。

Description

半導體裝置
此處說明之複數個實施形態全體係關於半導體裝置。
於內置有NAND型快閃記憶體等記憶體晶片之半導體記憶裝置中，小型化與高容量化快速發展。於如半導體記憶裝置般之半導體裝置中應用如下構成，即，為了兼顧小型化與高容量化，例如將複數個記憶體晶片等半導體晶片之積層體隔著間隔件安裝於配線基板上，並且將記憶體晶片之控制器晶片等半導體晶片安裝於配線基板上，且以樹脂層密封該等複數個半導體晶片。該半導體裝置中，隨著記憶體晶片之高速化，要求進一步抑制電源-接地間之電壓變動雜訊。
例如，提出如下方案，即，於安裝於配線基板上之複數個半導體晶片間配置導體塗層晶片，並且將導體塗層晶片與半導體晶片之接地、導體塗層晶片與配線基板之接地分別以較短之導線連接，由此降低接地之電阻及電感。進而，藉由導體塗層晶片之接地導體層與半導體晶片之電源導體層來增加電源-接地間之電容，由此使電源-接地間之阻抗降低。
於抑制半導體裝置之電源-接地間之電壓變動雜訊時，隨著半導體裝置之高速化，需要變小之電源-接地間之阻抗之頻率範圍向高頻區域擴大。為了降低高頻之電源-接地間之阻抗，需要增加電源-接地間之電容。然而，上述之先前構造中，為了於導體塗層晶片之接地導體層與半導體晶片之電源導體層增加電容，電源層與接地層之間之距離受晶片之厚度限制，難以進一步增加電容。因此，存在無法充分獲得所期待之電源-接地間之電壓變動雜訊之抑制效果之問題。
本發明之實施形態，提供藉由降低高頻之電源-接地間之阻抗而可抑制電源-接地間之電壓變動雜訊之半導體裝置。
根據實施形態之半導體裝置，具備：配線基板；間隔基板，其搭載於上述配線基板上，內設有電源導體層與接地導體層；至少一個第1半導體晶片，其等安裝於上述間隔基板上，具有與上述電源導體層電性連接之電源層及與上述接地導體層電性連接之接地層；及第2半導體晶片，其安裝於上述配線基板上。
根據上述構成，可提供藉由降低高頻之電源-接地間之阻抗而能夠抑制電源-接地間之電壓變動雜訊之半導體裝置。
以下，參照圖式對實施形態之半導體裝置進行說明。再者，各實施形態中，存在對實質上相同之構成部位附上相同符號，並省略其一部分說明之情形。圖式為模式性之圖，厚度與平面尺寸之關係、各部之厚度之比率等存在與實物不同之情形。說明中之表示上下等方向之用語，於未特別明示之情形時，均表示以後述之配線基板之半導體晶片之搭載面為上之情形時之相對性之方向，存在與以重力加速度方向為基準之現實方向不同之情形。
(第1實施形態) 圖1係表示第1實施形態之半導體裝置之構成之剖面圖。圖1所示之半導體裝置1具備：配線基板2；間隔基板3，其搭載於配線基板2上；複數個第1半導體晶片4(4A、4B)，其等安裝於間隔基板3上；第2半導體晶片5，其安裝於藉由間隔基板3確保安裝空間之配線基板2上；及密封樹脂層6，其密封第1及第2半導體晶片4、5。間隔基板3如下文詳述般，內設有電源導體層7與接地導體層8。
作為配線基板2，使用例如於絕緣樹脂基板之表面或內部設置有配線網(未圖示)之配線基板，具體而言使用印刷配線板(多層印刷基板等)，該印刷配線板使用玻璃-環氧樹脂或BT樹脂(雙馬來醯亞胺三嗪樹脂)等。印刷配線板等配線基板2，通常具有作為配線網之Cu層(未圖示)。配線基板2具有成為外部端子之形成面之第1表面2a、及成為第1及第2半導體晶片4、5之安裝面之第2表面2b。
於配線基板2之第1面2a設置有複數個外部電極9。於配線基板2之第2面2b設置有複數個內部電極10，該等複數個內部電極10成為間隔基板3之電源導體層7與接地導體層8或第1及第2半導體晶片4、5之電性連接部，並且利用省略圖示之內部配線與外部電極9電性連接。於配線基板2之外部電極9上形成有外部端子11。於以BGA(Ball Grid Array，球柵陣列)封裝之形式使用半導體裝置1之情形時，外部端子11由使用焊料球或焊料鍍覆等之連接端子(球電極)構成。於以LGA(Land Grid Array，柵格陣列)封裝之形式使用半導體裝置1之情形時，作為外部端子11，應用使用鍍Au等之金屬焊盤。
於搭載於配線基板2之第2面2b之間隔基板3上，配置有複數個第1半導體晶片4A、4B。第1半導體晶片4A、4B分別具有複數個電極焊墊12(12A、12B)。第1半導體晶片4A、4B以各自之電極焊墊12A、12B露出之方式積層為階梯狀。作為第1半導體晶片4之具體例，可列舉NAND型快閃記憶體等記憶體晶片，但並不限定於該等。圖1表示將2個第1半導體晶片4A、4B積層為階梯狀之構造，第1半導體晶片4之相對於配線基板2之安裝數或安裝構造並不限定於此。第1半導體晶片4之安裝數並不限定於2個，亦可為1個或3個以上之複數個之任一者。第1半導體晶片4之複數個電極焊墊12中，信號焊墊於它們之間以導線13連接，進而以導線14與配線基板2之內部電極10連接。
於配線基板2之第2面2b上，進而搭載有第2半導體晶片5。第2半導體晶片5之至少一部分，配置於包含有於間隔基板3上升高、且階梯狀積層之複數個半導體晶片4A、4B之從間隔基板3突出之部分之下側之空間。第2半導體晶片5具有複數個電極焊墊15，該等電極焊墊15經由導線16與配線基板2之內部電極10電性連接。作為第2半導體晶片5，可列舉於作為第1半導體晶片4之記憶體晶片與外部設備之間接收發送數位信號之控制器晶片或介面晶片、邏輯晶片、RF(radio frequency，射頻)晶片等系統LSI(large scale integration，大規模積體電路)晶片。藉由將第2半導體晶片5搭載於配線基板2之第2面2b上，可縮短從控制器晶片或系統LSI晶片等第2半導體晶片5至配線基板2為止之配線長度，從而可應對半導體裝置1之高速化。
作為間隔基板3，使用例如矽酮間隔件，但並不限定於此，亦可使用通常之配線基板作為間隔基板3。間隔基板3為了如上述般確保第2半導體晶片5之安裝空間，將第1半導體晶片4之位置升高來使之向上方移動。實施形態之半導體裝置1中，於該間隔基板3之內部設置有電源導體層7與接地導體層8。進而，間隔基板3具有複數個電極焊墊17，於其內部設置有複數個導通孔18。電源導體層7經由至少一個導通孔18而與至少一個電極焊墊17連接，進而電極焊墊17以導線19與配線基板2之內部電極10之電源電極連接。接地導體層8經由其他導通孔18而與其他電極焊墊17連接，進而電極焊墊17以導線19與配線基板2之內部電極10之接地電極連接。電源導體層7及接地導體層8分別於間隔基板3內設置有複數個。
第1半導體晶片4A、4B之複數個電極焊墊12A、12B中，電源焊墊於它們之間以導線13連接，進而以導線20與和間隔基板3之電源導體層7連接之電極焊墊17連接。第1半導體晶片4A、4B之複數個電極焊墊12A、12B中，接地焊墊於它們之間以導線13連接，進而以導線20與和間隔基板3之接地導體層8連接之電極焊墊17連接。即，設置於第1半導體晶片4內之電源層，與間隔基板3之電源導體層7連接，進而與配線基板2之電源電極連接。設置於第1半導體晶片4內之接地層，與間隔基板3之接地導體層8連接，進而與配線基板2之接地電極連接。
如此，藉由將第1半導體晶片4之電源層(未圖示)與間隔基板3之電源導體層7電性連接，並且將第1半導體晶片4之接地層(未圖示)與間隔基板3之接地導體層8電性連接，可於間隔基板3之電源導體層7與接地導體層8之間增加電容。電源導體層7與接地導體層8之間之距離，雖受間隔基板3之厚度之限制，但可設定為所需之距離，可增加電源-接地間之電容。進而，可縮短第1半導體晶片4之電源層及接地層與電源導體層7及接地導體層8之距離。因此，即便於第1半導體晶片4A、4B高頻化之情形時，仍可降低高頻之電源-接地間之阻抗。
阻抗Z相對於頻率f、電感L及容量C以下式表示。  [數1]
Figure 02_image001
如上所述，即便於頻率f高頻化之情形時，仍可使容量C增加，並且可使電感L減少，由此可使阻抗Z變小。電感L於其他條件相同之情形時，一般係配線距離越長則變得越大，因此需要儘量縮短配線。藉由使阻抗Z變小，可抑制電源-接地間之電壓變動雜訊。由此，隨著半導體裝置1之高速化，即便於電源-接地間之阻抗高頻化之情形時，仍可增加電源-接地間之電容而降低阻抗，由此可抑制電源-接地間之電壓變動雜訊。因此，可提高具備高速化及高頻化之第1半導體晶片(記憶體晶片)4之半導體裝置1之動作特性或可靠性等，並且可抑制對外部設備之不良影響等。進而，藉由增加電源-接地間之電容，可省去搭載晶片電容器，從而可實現半導體裝置1之小型化或低成本化等。
(第2實施形態) 圖2係表示第2實施形態之半導體裝置之構成之剖面圖。圖2所示之半導體裝置1具有搭載於配線基板2上之2個間隔基板3A、3B。於2個間隔基板3A、3B上，分別安裝有2個第1半導體晶片4A(4A1、4A2)、4B(4B1、4B2)。間隔基板3A及安裝於其上之第1半導體晶片4A1、4B1、與間隔基板3B及安裝於其上之第1半導體晶片4A2，4B2，除於配線基板2上左右反轉之外，具有相同構造，又除它們之間之連接構造及與配線基板2之連接構造亦左右反轉之外，具有相同構造。
進而，間隔基板3A、3B、第1半導體晶片4A1、4B1、4A2、4B2及配線基板2之連接構造，除間隔基板3B及第1半導體晶片4A2、4B2之左右反轉狀態以外，與第1實施形態之連接構造相同，分別使用導線13、14、19、20連接。第2實施形態之半導體裝置1，於配線基板2之2個間隔基板3A、3B間安裝有第2半導體晶片5。即，於包含有階梯狀積層之第1半導體晶片4A1、4B1之從間隔基板3A突出之部分之下側、及階梯狀積層之第1半導體晶片4A2、4B2之從間隔基板3B突出之部分之下側之空間，配置第2半導體晶片5。2個間隔基板3A、3B分別具有電源導體層7A、7B及接地導體層8A、8B。
將上述間隔基板3A之電源導體層7A及接地導體層8A與設置於第1半導體晶片4A1、4B1之電源層及接地層連接，並且將間隔基板3B之電源導體層7B及接地導體層8B與設置於第1半導體晶片4A2、4B2內之電源層及接地層連接，由此可增加各個電源-接地間之電容，進而可縮短第1半導體晶片4A1、4B1、4A2、4B2之電源層及接地層與電源導體層7A、7B及接地導體層8A、8B之距離。因此，即便於第1半導體晶片4A1、4B1、4A2、4B2高頻化之情形時，仍可降低高頻之電源-接地間之阻抗。由此，可抑制電源-接地間之電壓變動雜訊。因此，可提高具備高速化及高頻化之第1半導體晶片(記憶體晶片)4之半導體裝置1之動作特性或可靠性等，並且可抑制對外部設備之不良影響等。
(第3實施形態) 圖3係表示第3實施形態之半導體裝置之構成之剖面圖。圖3所示之半導體裝置1，於將間隔基板3搭載於配線基板2上之接著層21內配置第2半導體晶片5。即，第3實施形態之半導體裝置1應用薄膜上晶片構造，將間隔基板3隔著接著層21搭載於配線基板2上，並且將第2半導體晶片5埋入於接著層21內。第3實施形態之半導體裝置1，除將第2半導體晶片5埋入於接著層21內之構造以外，具有與第1實施形態之半導體裝置1相同之構成及連接構造等。
即，藉由將間隔基板3之電源導體層7及接地導體層8與設置於第1半導體晶片4A、4B內之電源層及接地層連接，而增加電源-接地間之電容。進而，縮短第1半導體晶片4A、4B之電源層及接地層與電源導體層7及接地導體層8之距離。因此，即便於第1半導體晶片4A、4B高頻化之情形時，仍可降低高頻之電源-接地間之阻抗。由此，可抑制電源-接地間之電壓變動雜訊。因此，可提高具備高速化及高頻化之第1半導體晶片(記憶體晶片)4之半導體裝置1之動作特性或可靠性等，並且可抑制對外部設備之不良影響等。
再者，上述各實施形態之構成可分別組合應用，又亦可置換一部分。此處，對本發明之幾個實施形態進行了說明，但該等實施形態係作為例子提示者，並未意圖限定發明之範圍。該等新之實施形態能以其他各種方式實施，可於不脫離發明之要旨之範圍，進行各種省略、替換、變更等。該等實施形態或其變化包含於發明之範圍或要旨中，同時亦包含於權利要求書中所記載之發明及其均等之範圍。關聯申 請 案 之引用
本申請案係基於2019年3月14申請之先前之日本專利申請案第2019-046938號之優先權之利益，且請求其利益，並將其內容全體藉由引用而包含於此。
1:半導體裝置 2:配線基板 2a:第1表面 2b:第2表面 3:間隔基板 3A:間隔基板 3B:間隔基板 4A:第1半導體晶片 4A1:第1半導體晶片 4A2:第1半導體晶片 4B:第1半導體晶片 4B1:第1半導體晶片 4B2:第1半導體晶片 5:第2半導體晶片 6:密封樹脂層 7:電源導體層 7A:電源導體層 7B:電源導體層 8:接地導體層 8A:接地導體層 8B:接地導體層 9:外部電極 10:內部電極 11:外部端子 12A:電極焊墊 12B:電極焊墊 13:導線 14:導線 15:電極焊墊 16:導線 17:電極焊墊 18:導通孔 19:導線 20:導線 21:接著層
圖1係表示第1實施形態之半導體裝置之剖面圖。  圖2係表示第2實施形態之半導體裝置之剖面圖。  圖3係表示第3實施形態之半導體裝置之剖面圖。
1:半導體裝置
2:配線基板
2a:第1表面
2b:第2表面
3:間隔基板
4A:第1半導體晶片
4B:第1半導體晶片
5:第2半導體晶片
6:密封樹脂層
7:電源導體層
8:接地導體層
9:外部電極
10:內部電極
11:外部端子
12A:電極焊墊
12B:電極焊墊
13:導線
14:導線
15:電極焊墊
16:導線
17:電極焊墊
18:通孔
19:導線
20:導線

Claims (6)

  1. 一種半導體裝置，具備：配線基板；間隔基板，其搭載於上述配線基板上，且內設有電源導體層與接地導體層；至少一個第1半導體晶片，其等安裝於上述間隔基板上，具有與上述電源導體層電性連接之電源層及與上述接地導體層電性連接之接地層；及第2半導體晶片，其安裝於上述配線基板上。
  2. 如請求項1之半導體裝置，其中於上述間隔基板上，積層安裝有複數個上述第1半導體晶片。
  3. 如請求項1之半導體裝置，其中上述間隔基板具有與上述電源導體層電性連接之電源焊墊、及與上述接地導體層電性連接之接地焊墊，上述第1半導體晶片具有經由導線與上述間隔基板之上述電源焊墊電性連接之電極焊墊、及經由導線與上述間隔基板之上述接地焊墊電性連接之電極焊墊。
  4. 如請求項2之半導體裝置，其中上述間隔基板具有與上述電源導體層電性連接之電源焊墊、及與上述接地導體層電性連接之接地焊墊，上述第1半導體晶片具有經由導線與上述間隔基板之上述電源焊墊電性連接之電極焊墊、及經由導線與上述間隔基板之上述接地焊墊電性連接之電極焊墊。
  5. 如請求項1至4中任一項之半導體裝置，其中上述第2半導體晶片之至少一部分，位於從上述間隔基板突出之上述第1半導體晶片之一部分之下方。
  6. 如請求項1至4中任一項之半導體裝置，其中上述第2半導體晶片埋入於將上述間隔基板搭載於上述配線基板上之接著層內。
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