JP2008016519A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2008016519A JP2008016519A JP2006183993A JP2006183993A JP2008016519A JP 2008016519 A JP2008016519 A JP 2008016519A JP 2006183993 A JP2006183993 A JP 2006183993A JP 2006183993 A JP2006183993 A JP 2006183993A JP 2008016519 A JP2008016519 A JP 2008016519A
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- wiring board
- semiconductor device
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- main surface
- memory chip
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
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- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
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Abstract
【解決手段】第1配線基板4と、第1配線基板4上に搭載されたマイコンチップ3と、マイコンチップ3上に配置された第2配線基板5と、第1配線基板4と第2配線基板5とを接続する複数の第1はんだバンプ34と、第1配線基板4の裏面4bに設けられた外部端子である複数の第2はんだバンプ35とからなり、第2配線基板5には高速の第1メモリチップ2と第2メモリチップ6が積層して内蔵され、第2配線基板5内で第1メモリチップ2の配線と第2メモリチップ6の配線が等長化されており、第1配線基板4を有するパッケージ完結構造上に第2配線基板5を有するパッケージ完結構造が搭載されている。
【選択図】図1
Description
図1は本発明の実施の形態1の半導体装置の構造の一例を模式的に示す断面図、図2は図1に示す半導体装置の等長配線構造を模式的に示す部分構造図、図3は図1に示す半導体装置を基板ごとに展開して構造を示す平面図、図4は本発明の実施の形態1の変形例の半導体装置の構造を模式的に示す断面図である。また、図5は図1に示す半導体装置の上段側パッケージの構造を示す断面図、図6は図1に示す半導体装置の下段側パッケージの構造を示す断面図、図7は図4に示す半導体装置の下段側パッケージの構造を示す断面図、図8は本発明の実施の形態1の変形例の半導体装置の構造を模式的に示す断面図、図9は本発明の実施の形態1の変形例の半導体装置の構造を模式的に示す断面図である。さらに、図10は図8に示す半導体装置を基板ごとに展開して構造を示す平面図、図11は本発明の実施の形態1の変形例の半導体装置の構造を模式的に示す断面図、図12は本発明の実施の形態1の変形例の半導体装置の構造を模式的に示す断面図である。
図40は本発明の実施の形態2の半導体装置の構造の一例を模式的に示す断面図、図41は図40に示す半導体装置の上段側パッケージの構造を示す断面図、図42は図41に示す上段側パッケージの基板の内部構造の一例を示す部分断面図である。
図43は本発明の実施の形態3の半導体装置の構造の一例を模式的に透過して示す平面図、図44は図43に示す半導体装置の断面図、図45乃至図48はそれぞれ本発明の実施の形態3の変形例の半導体装置の構造を模式的に透過して示す平面図と断面図である。
2 第1メモリチップ
2a 主面
2b 裏面
2c 第1電極パッド
2d 貫通孔
3 マイコンチップ
3a 主面
3b 裏面
4 第1配線基板
4a 主面
4b 裏面
4c 第1ボンディングリード
4d 端子
4e 第1内部配線
4f 第2内部配線
5 第2配線基板
5a 主面
5b 裏面
5c 第2ボンディングリード
5d 内部配線
5e 第1距離
5f 第2距離
5g 端子
5h 他の内部配線
6 第2メモリチップ
6a 主面
6b 裏面
6c 第2電極パッド
6d 貫通孔
7 Siベース
8 デバイス層
9 ヒューズ
10 パッシベーション膜
11 絶縁層
12 シード層
13 レジスト膜
14 Cu電極
15 第1ベース基板
16 キャビティ
17 樹脂層
18 ダイボンド材
19 絶縁材
20 導体パターン
21 第2ベース基板
22 充填材
23 スルーホール配線
24 ビアパッド
25 中継パターン
26 パッド
27 レジスト膜
28 スペーサ基板
28a 段差部
29 導体
30 第3メモリチップ
30a 主面
30b 裏面
30c 貫通孔
31,32 SIP(半導体装置)
33 薄膜化デバイス
34 第1はんだバンプ(第1バンプ電極)
35 第2はんだバンプ(第2バンプ電極)
36 金バンプ
37 アンダーフィル
38 ワイヤ
39 封止体
40 メモリチップ
41 放熱板
42 接着剤
43 第3配線基板
44 第3はんだバンプ
45 マイコンチップ
46 はんだペースト
Claims (17)
- 第1主面と前記第1主面に対向する第1裏面を有する第1配線基板と、
前記第1配線基板の第1主面上に搭載されたマイコンチップと、
第2主面と前記第2主面に対向する第2裏面を有し、かつ前記マイコンチップ上に配置された第2配線基板と、
前記第1配線基板と前記第2配線基板を電気的に接続する複数の第1バンプ電極と、
前記第1配線基板の第1裏面に配置された複数の第2バンプ電極とを有し、
前記第2配線基板は、第1メモリチップと第2メモリチップを内蔵し、
前記第2メモリチップは、前記第1メモリチップ上に配置され、
前記第1及び第2メモリチップは、外部クロック信号の立ち上がりと立ち下がりの両方に同期してデータを転送することを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記第1配線基板の主面と前記第2配線基板の主面のうち、何れか一方もしくは両方に放熱板が設けられていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記マイコンチップは、前記第1配線基板上にフリップチップ接続されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記マイコンチップは、前記第1配線基板上に複数搭載されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数の第1バンプ電極は、前記第1配線基板の第1主面上に設けられた複数の第1ボンディングリードと前記第2配線基板の第2裏面上に設けられた複数の第2ボンディングリードとの間にそれぞれ配置されていることを特徴とする半導体装置。
- 請求項5記載の半導体装置において、前記マイコンチップと前記第1及び第2メモリチップのそれぞれは、前記複数の第1ボンディングリード、前記複数の第1バンプ電極、及び前記複数の第2ボンディングリードを介して電気的に接続されていることを特徴とする半導体装置。
- 請求項6記載の半導体装置において、前記第1メモリチップの第1電極パッドから前記第1電極パッドに対応する前記第2配線基板の第2ボンディングリードまでの第1距離と、前記第2メモリチップの第2電極パッドから前記第2電極パッドに対応する前記第2ボンディングリードまでの第2距離は等しいことを特徴とする半導体装置。
- 請求項7記載の半導体装置において、前記第1距離と前記第2距離の差の許容範囲は、±2mm以内好ましくは±1mm以内であることを特徴とする半導体装置。
- 主面と前記主面に対向する裏面を有する第1配線基板と、
前記第1配線基板の主面上に搭載されたマイコンチップと、
主面と前記主面に対向する裏面を有し、かつ前記マイコンチップ上に配置された第2配線基板と、
前記第1配線基板と前記第2配線基板を電気的に接続する複数の第1バンプ電極と、
前記第1配線基板の裏面に配置された複数の第2バンプ電極とを有し、
前記第2配線基板は、第1メモリチップと第2メモリチップを内蔵し、
前記第1及び第2メモリチップは、各々の主面と裏面に開口する貫通孔をそれぞれ有し、かつそれぞれの貫通孔に埋め込まれた導体を介して電気的に接続し、
前記第1及び第2メモリチップは、外部クロック信号の立ち上がりと立ち下がりの両方に同期してデータを転送することを特徴とする半導体装置。 - 請求項9記載の半導体装置において、前記第1配線基板の主面と前記第2配線基板の主面のうち、何れか一方もしくは両方に放熱板が設けられていることを特徴とする半導体装置。
- 請求項9記載の半導体装置において、前記マイコンチップは、前記第1配線基板上にフリップチップ接続されていることを特徴とする半導体装置。
- 請求項9記載の半導体装置において、前記複数の第1バンプ電極は、前記第1配線基板の第1主面上に設けられた複数の第1ボンディングリードと前記第2配線基板の第2裏面上に設けられた複数の第2ボンディングリードとの間にそれぞれ配置されていることを特徴とする半導体装置。
- 請求項12記載の半導体装置において、前記マイコンチップと前記第1及び第2メモリチップのそれぞれは、前記複数の第1ボンディングリード、前記複数の第1バンプ電極、及び前記複数の第2ボンディングリードを介して電気的に接続されていることを特徴とする半導体装置。
- 請求項13記載の半導体装置において、前記第1メモリチップの第1電極パッドから前記第1電極パッドに対応する前記第2配線基板の第2ボンディングリードまでの第1距離と、前記第2メモリチップの第2電極パッドから前記第2電極パッドに対応する前記第2ボンディングリードまでの第2距離は等しいことを特徴とする半導体装置。
- 主面と前記主面に対向する裏面を有し、かつ前記主面上に複数の第1ボンディングリードが設けられた第1配線基板を準備する工程と、
主面と前記主面に対向する裏面を有し、かつ外部クロック信号の立ち上がりと立ち下がりの両方に同期してそれぞれデータを転送する第1メモリチップと第2メモリチップを内蔵し、さらに前記第2メモリチップが前記第1メモリチップ上に配置され、かつ前記裏面上に複数の第2ボンディングリードが設けられた第2配線基板を準備する工程と、
前記第1配線基板の主面上にマイコンチップを搭載する工程と、
前記第1配線基板の主面の前記複数の第1ボンディングリード上にはんだペーストを塗布する工程と、
前記第2配線基板の裏面の前記複数の第2ボンディングリードに第1バンプ電極を接続する工程と、
前記第1バンプ電極と前記はんだペーストを接続して前記第1配線基板上に前記第2配線基板を実装する工程とを有することを特徴とする半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、前記第2配線基板を、熱及び荷重を掛けた状態で前記第1配線基板上に実装することを特徴とする半導体装置の製造方法。
- 請求項15記載の半導体装置の製造方法において、前記第1メモリチップの第1電極パッドから前記第1電極パッドに対応する前記第2配線基板の第2ボンディングリードまでの第1距離と、前記第2メモリチップの第2電極パッドから前記第2電極パッドに対応する前記第2ボンディングリードまでの第2距離は等しいことを特徴とする半導体装置の製造方法。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011028070A (ja) * | 2009-07-28 | 2011-02-10 | Seiko Epson Corp | 集積回路装置、電子機器及び電子機器の製造方法 |
CN102157394A (zh) * | 2011-03-22 | 2011-08-17 | 南通富士通微电子股份有限公司 | 高密度系统级封装方法 |
US8436462B2 (en) | 2010-03-26 | 2013-05-07 | Samsung Electronics Co., Ltd. | Semiconductor housing package, semiconductor package structure including the semiconductor housing package, and processor-based system including the semiconductor package structure |
WO2014004527A1 (en) * | 2012-06-29 | 2014-01-03 | Intel Corporation | Package substrates with multiple dice |
US8928132B2 (en) | 2011-02-17 | 2015-01-06 | Samsung Electronics Co., Ltd. | Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package |
JP2015056494A (ja) * | 2013-09-11 | 2015-03-23 | 株式会社東芝 | 半導体装置および記憶装置 |
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Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4185499B2 (ja) * | 2005-02-18 | 2008-11-26 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
SG166773A1 (en) * | 2007-04-24 | 2010-12-29 | United Test & Assembly Ct Lt | Bump on via-packaging and methodologies |
US7759212B2 (en) * | 2007-12-26 | 2010-07-20 | Stats Chippac, Ltd. | System-in-package having integrated passive devices and method therefor |
US8258015B2 (en) * | 2008-02-22 | 2012-09-04 | Stats Chippac Ltd. | Integrated circuit package system with penetrable film adhesive |
US8304869B2 (en) * | 2008-08-01 | 2012-11-06 | Stats Chippac Ltd. | Fan-in interposer on lead frame for an integrated circuit package on package system |
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US8097956B2 (en) * | 2009-03-12 | 2012-01-17 | Apple Inc. | Flexible packaging for chip-on-chip and package-on-package technologies |
JP2010238995A (ja) * | 2009-03-31 | 2010-10-21 | Sanyo Electric Co Ltd | 半導体モジュールおよびこれを搭載したカメラモジュール |
US8064202B2 (en) * | 2010-02-24 | 2011-11-22 | Monolithic Power Systems, Inc. | Sandwich structure with double-sided cooling and EMI shielding |
US8674516B2 (en) * | 2011-06-22 | 2014-03-18 | Stats Chippac Ltd. | Integrated circuit packaging system with vertical interconnects and method of manufacture thereof |
KR20130007049A (ko) * | 2011-06-28 | 2013-01-18 | 삼성전자주식회사 | 쓰루 실리콘 비아를 이용한 패키지 온 패키지 |
US8816404B2 (en) | 2011-09-16 | 2014-08-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant |
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US9368477B2 (en) * | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
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US9281284B2 (en) * | 2014-06-20 | 2016-03-08 | Freescale Semiconductor Inc. | System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof |
JP6543129B2 (ja) * | 2015-07-29 | 2019-07-10 | ルネサスエレクトロニクス株式会社 | 電子装置 |
KR102438753B1 (ko) * | 2015-10-01 | 2022-09-01 | 에스케이하이닉스 주식회사 | 반도체 장치 |
WO2017122449A1 (ja) * | 2016-01-15 | 2017-07-20 | ソニー株式会社 | 半導体装置および撮像装置 |
US11487445B2 (en) * | 2016-11-22 | 2022-11-01 | Intel Corporation | Programmable integrated circuit with stacked memory die for storing configuration data |
CN108400117A (zh) * | 2017-02-06 | 2018-08-14 | 钰桥半导体股份有限公司 | 三维整合的散热增益型半导体组件及其制作方法 |
US10475770B2 (en) * | 2017-02-28 | 2019-11-12 | Amkor Technology, Inc. | Semiconductor device having stacked dies and stacked pillars and method of manufacturing thereof |
JP6679528B2 (ja) * | 2017-03-22 | 2020-04-15 | キオクシア株式会社 | 半導体装置 |
TWI678747B (zh) * | 2018-10-01 | 2019-12-01 | 點序科技股份有限公司 | 測試裝置及其晶片承載板 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001068617A (ja) * | 1999-08-27 | 2001-03-16 | Toshiba Corp | 半導体装置 |
JP2003218282A (ja) * | 2002-01-18 | 2003-07-31 | Ibiden Co Ltd | 半導体素子内蔵基板および多層回路基板 |
JP2004281820A (ja) * | 2003-03-17 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004281920A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004327474A (ja) * | 2003-04-21 | 2004-11-18 | Elpida Memory Inc | メモリモジュール及びメモリシステム |
JP2005039020A (ja) * | 2003-07-18 | 2005-02-10 | Renesas Technology Corp | 半導体装置 |
JP2006032379A (ja) * | 2004-07-12 | 2006-02-02 | Akita Denshi Systems:Kk | 積層半導体装置及びその製造方法 |
JP2006165077A (ja) * | 2004-12-03 | 2006-06-22 | Elpida Memory Inc | 積層型半導体パッケージ |
JP2006245104A (ja) * | 2005-03-01 | 2006-09-14 | Matsushita Electric Ind Co Ltd | 部品内蔵モジュールの製造方法および部品内蔵モジュール |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3858854B2 (ja) | 2003-06-24 | 2006-12-20 | 富士通株式会社 | 積層型半導体装置 |
TWI267967B (en) * | 2005-07-14 | 2006-12-01 | Chipmos Technologies Inc | Chip package without a core and stacked chip package structure using the same |
US7550680B2 (en) * | 2006-06-14 | 2009-06-23 | Stats Chippac Ltd. | Package-on-package system |
US7667338B2 (en) * | 2006-08-08 | 2010-02-23 | Lin Paul T | Package with solder-filled via holes in molding layers |
-
2006
- 2006-07-04 JP JP2006183993A patent/JP5259059B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-16 US US11/798,737 patent/US7847413B2/en not_active Expired - Fee Related
- 2007-05-22 TW TW096118100A patent/TW200816435A/zh unknown
- 2007-06-18 CN CNA2007101101300A patent/CN101101909A/zh active Pending
- 2007-06-29 KR KR1020070065074A patent/KR20080004356A/ko not_active Application Discontinuation
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001068617A (ja) * | 1999-08-27 | 2001-03-16 | Toshiba Corp | 半導体装置 |
JP2003218282A (ja) * | 2002-01-18 | 2003-07-31 | Ibiden Co Ltd | 半導体素子内蔵基板および多層回路基板 |
JP2004281820A (ja) * | 2003-03-17 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004281920A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004327474A (ja) * | 2003-04-21 | 2004-11-18 | Elpida Memory Inc | メモリモジュール及びメモリシステム |
JP2005039020A (ja) * | 2003-07-18 | 2005-02-10 | Renesas Technology Corp | 半導体装置 |
JP2006032379A (ja) * | 2004-07-12 | 2006-02-02 | Akita Denshi Systems:Kk | 積層半導体装置及びその製造方法 |
JP2006165077A (ja) * | 2004-12-03 | 2006-06-22 | Elpida Memory Inc | 積層型半導体パッケージ |
JP2006245104A (ja) * | 2005-03-01 | 2006-09-14 | Matsushita Electric Ind Co Ltd | 部品内蔵モジュールの製造方法および部品内蔵モジュール |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011028070A (ja) * | 2009-07-28 | 2011-02-10 | Seiko Epson Corp | 集積回路装置、電子機器及び電子機器の製造方法 |
US8436462B2 (en) | 2010-03-26 | 2013-05-07 | Samsung Electronics Co., Ltd. | Semiconductor housing package, semiconductor package structure including the semiconductor housing package, and processor-based system including the semiconductor package structure |
US8928132B2 (en) | 2011-02-17 | 2015-01-06 | Samsung Electronics Co., Ltd. | Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package |
CN102157394A (zh) * | 2011-03-22 | 2011-08-17 | 南通富士通微电子股份有限公司 | 高密度系统级封装方法 |
WO2014004527A1 (en) * | 2012-06-29 | 2014-01-03 | Intel Corporation | Package substrates with multiple dice |
US8742597B2 (en) | 2012-06-29 | 2014-06-03 | Intel Corporation | Package substrates with multiple dice |
US9177911B2 (en) | 2012-06-29 | 2015-11-03 | Intel Corporation | Package substrates with multiple dice |
JP2015056494A (ja) * | 2013-09-11 | 2015-03-23 | 株式会社東芝 | 半導体装置および記憶装置 |
TWI724510B (zh) * | 2019-03-14 | 2021-04-11 | 日商東芝記憶體股份有限公司 | 半導體裝置 |
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TW200816435A (en) | 2008-04-01 |
JP5259059B2 (ja) | 2013-08-07 |
KR20080004356A (ko) | 2008-01-09 |
CN101101909A (zh) | 2008-01-09 |
US7847413B2 (en) | 2010-12-07 |
US20080006947A1 (en) | 2008-01-10 |
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