TW201513291A - 晶片封裝及其製備方法 - Google Patents

晶片封裝及其製備方法 Download PDF

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TW201513291A
TW201513291A TW103129800A TW103129800A TW201513291A TW 201513291 A TW201513291 A TW 201513291A TW 103129800 A TW103129800 A TW 103129800A TW 103129800 A TW103129800 A TW 103129800A TW 201513291 A TW201513291 A TW 201513291A
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lower vertical
connecting member
connector
vertical
wafer
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TW103129800A
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TWI532140B (zh
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Po-Chun Lin
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Nanya Technology Corp
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Abstract

一種半導體裝置包含複數導體。各導體經由一上垂直連接件連接一晶片選擇接點。上垂直連接件穿過在基材上的絕緣層或連接穿過基材和絕緣層的直的垂直連接件。半導體裝置包含複數下垂直連接件，下垂直連接件穿過基材並對應地電性連接晶片選擇接點及晶片選擇電極。晶片選擇電極電性連接半導體裝置的晶粒電路，而晶片選擇接點電性絕緣於晶粒電路。下垂直連接件與直的垂直連接件呈二維排列。

Description

晶片封裝及其製備方法
本發明係關於一種晶片封裝及其製備方法。
三維積體電路是堆疊晶粒並將其互連而製成，藉此使它們可運作如單一裝置一般。堆疊的晶粒可使用直通矽通道(through silicon via；TSV)技術相連，如此三維積體電路可具有小的底面積。
通常TSVs是非常大；它們有閘極和記憶元(memory cells)的數倍大。再者，當TSVs製作時，TSVs周圍會產生拉伸應力，拉伸應力會導致載子遷移率的差異(carrier mobility variation)。在TSVs周圍設置禁用區(keep out zones)，以避免裝置或單元被由TSV所產生的應力所影響。
傳統的三維積體電路具有一晶片選擇機制，其中該晶片選擇機制使用TSVs為垂直連接件。通常TSVs是沿一方向設置。由於TSVs及其所產生的禁用區等的尺寸大，成直線排列的TSVs消耗大的晶粒面積，造成大尺寸的晶粒或限制三維積體電路中晶粒堆疊的數目。
根據上述問題，本發明對應地實現成不同實施例的晶片封裝及其製備方法。
本發明一實施例之晶片封裝包含至少一半導體裝置。至少一半導體裝置包含一晶粒、一晶片選擇電極、複數晶片選擇接點、一第一下垂直連接件、複數第二下垂直連接件、一絕緣層、複數上垂直連接件、一垂直連接件及複數導體。晶粒包含一晶粒電路和一基材。晶片選擇電極形成於基材，並電性連接晶粒電路。複數晶片選擇接點形成於基材，並電性隔離於晶粒電路。第一下垂直連接件貫穿基材，並連接晶片選擇電極。複 數第二下垂直連接件貫穿基材，並對應連接該些晶片選擇接點。絕緣層形成於基材上。複數上垂直連接件穿過絕緣層，並對應連接該些晶片選擇接點。垂直連接件垂直地穿過基材與絕緣層。複數導體形成於絕緣層上。各導體連接至該些上垂直連接件與垂直連接件中之一對應者，並延伸至該第一下垂直連接件與該些第二下垂直連接件中一對應者之上方。第一下垂直連接件、該些第二下垂直連接件和該垂直連接件呈二維排列。
本發明一實施例之晶片封裝之製備方法包含：形成一第一下垂直連接件、複數第二下垂直連接件和一第三下垂直連接件於一半導體裝置之一基材；形成一晶片選擇電極和複數晶片選擇接點於基材，其中晶片選擇電極連接第一下垂直連接件，而該些晶片選擇接點對應地連接該些第二下垂直連接件；形成一絕緣層於基材上；形成複數上垂直連接件於絕緣層內，其中該些上垂直連接件對應地連接該些晶片選擇接點和第三下垂直連接件，而且第三下垂直連接件和與其連接的上垂直連接件形成一直的垂直連接件；以及形成複數導體於絕緣層上，其中該些導體對應地連接該些上垂直連接件和直的垂直連接件；其中第一下垂直連接件、該些第二下垂直連接件和第三下垂直連接件呈二維排列。
在至少一些實施例中，上述實施例之優點：由於垂直連接件呈二維排列，故可使用較少的面積。
1、1a、1b、1c‧‧‧晶片封裝
11、11a、11b、11c‧‧‧半導體裝置
12‧‧‧晶粒
31‧‧‧禁用區
32‧‧‧垂直連接件
51‧‧‧基材、底層
52‧‧‧孔洞
53‧‧‧金屬層
55‧‧‧孔洞
121‧‧‧基材
122‧‧‧晶片選擇電極
123‧‧‧晶片選擇接點
124‧‧‧第一下垂直連接件
125‧‧‧第二下垂直連接件
126‧‧‧絕緣層
127‧‧‧上垂直連接件
128‧‧‧垂直連接件
129‧‧‧導體
130‧‧‧絕緣墊
131‧‧‧導電墊
710‧‧‧晶粒
716‧‧‧凸塊(含複合結構凸塊)
圖1為本發明一實施例之晶片封裝之半導體裝置之示意圖。
圖2A為本發明另一實施例之晶片封裝之半導體裝置之示意圖。
圖2B為本發明另一實施例之晶片封裝之半導體裝置之示意圖。
圖3為本發明一實施例之示意圖，其例示複數垂直件的排列。
圖4為本發明另一實施例之示意圖，其例示複數垂直件的排列。
圖5A至5D為示意圖，其例示本發明一實施例之晶片封裝之製備方法。
圖6本發明一實施例之晶片封裝之堆疊的半導體裝置。
圖1為本發明一實施例之晶片封裝1之半導體裝置11之示意圖。如圖1所示，晶片封裝1包含至少一半導體裝置11。在一實施例中，晶片封裝1包含複數半導體裝置11。複數半導體裝置11堆疊在晶片封裝1內，並且彼此電性連接。
半導體裝置11可包含一晶粒12。晶粒12可從包含複數晶粒的晶圓分離出。各晶粒12包含具有預定功能的複製晶粒電路。晶粒12可包含基材121，其中晶粒電路形成於基材121上。
基材121包含半導體材料，例如：矽材料或類似者。
參照圖1所示，半導體裝置11可包含一晶片選擇電極(chip select(CS)terminal)122。晶片選擇電極122可形成於基材121上，並連接著晶粒12上整個晶粒電路。晶片選擇電極122是一個存取啟動開關(access-enable switch)。當晶片選擇電極122在啟動狀態(active state)時，半導體裝置11會對其輸入端(input terminals)的改變(例如：給動態隨機存取記憶體裝置的資料或位置資訊)而有所反應，並驅動一些輸出端。當晶片選擇電極122在非啟動狀態(inactive state)時，半導體裝置11會忽略其輸入端上的任何狀態變化，且其輸出會在高阻抗狀態(high impedance state)。
在一實施例中，晶片選擇電極122包含金屬，例如(但不限於)是銅(copper)或鎢(tungsten)。
半導體裝置11可包含至少一晶片選擇接點(chip select pad)123。晶片選擇接點123可形成於基材121上，且不連接(或電性隔離於)晶粒12之晶粒電路。
半導體裝置11可包含一第一下垂直連接件124。第一下垂直連接件124可貫穿基材121，並連接晶片選擇電極122。在半導體裝置11堆疊後，信號可從下面的半導體裝置或電路板，通過第一下垂直連接件124，到達晶片選擇電極122。
半導體裝置11可包含至少一第二下垂直連接件125。至少一第二下垂直連接件125可貫穿基材121，並對應地連接至至少一晶片選擇 接點123。
半導體裝置11可包含一絕緣層126。絕緣層126可形成於基材121上，並至少覆蓋晶片選擇電極122和至少一晶片選擇接點123。
半導體裝置11可包含至少一上垂直連接件127。至少一上垂直連接件127對應地連接至少一晶片選擇接點123，並貫穿絕緣層126。
半導體裝置11可包含一垂直連接件128。垂直連接件128可穿過基材121與絕緣層126。
半導體裝置11可包含複數導體129。複數導體129形成於絕緣層126。各導體129連接至少一上垂直連接件127與垂直連接件128中之一對應者。各導體129並延伸至第一下垂直連接件124與至少一第二下垂直連接件125中一對應者之上方。
如圖1所示，第一下垂直連接件124、至少一第二下垂直連接件125和垂直連接件128呈二維排列。因此，第一下垂直連接件124、至少一第二下垂直連接件125和垂直連接件128佔用較少的面積。
在一實施例中，第一下垂直連接件124、至少一第二下垂直連接件125和垂直連接件128可陣列排列。在一實施例中，第一下垂直連接件124、至少一第二下垂直連接件125和垂直連接件128可排列成矩形環狀或圓環狀。在一實施例中，第一下垂直連接件124、至少一第二下垂直連接件125和垂直連接件128可排列成U形圖案、V形圖案或任意圖案。
參照圖1所示，在一實施例中，導體129可在不同方向上延伸。在一實施例中，至少兩導體129可在不同方向上延伸。在一實施例中，至少兩導體129可互為垂直。
參照圖1所示，在一實施例中，半導體裝置11可包含一絕緣墊130。絕緣墊130可形成在連接垂直連接件128的導體129上。絕緣墊130可防止在下方半導體裝置11的垂直連接件128上所傳遞的信號經由在上方半導體裝置11的垂直連接件128傳遞。在一實施例中，絕緣墊130僅覆蓋連接垂直連接件128的導體129的部分；或者絕緣墊130小於對應的導體129。
圖2A為本發明另一實施例之晶片封裝1a之半導體裝置11a 之示意圖。參照圖2A所示，晶片封裝1a之半導體裝置11a包含較晶片封裝1之半導體裝置11更多的晶片選擇接點123、第二下垂直連接件125、上垂直連接件127和導體129。第一下垂直連接件124、第二下垂直連接件125和垂直連接件128可排列成矩形環或環形。
參照圖2A所示，在一實施例中，半導體裝置11a可包含絕緣墊130。絕緣墊130形成於連接垂直連接件128的導體129上。在一實施例中，絕緣墊130僅部分覆蓋連接垂直連接件128的導體129。
圖2B為本發明另一實施例之晶片封裝1b之半導體裝置11b之示意圖。參照圖2B所示，晶片封裝1b之半導體裝置11b具有與晶片封裝1a之半導體裝置11a相同數量的第二下垂直連接件125、晶片選擇接點123、上垂直連接件127及導體129；然半導體裝置11b之晶片選擇電極122的位置不同於半導體裝置11a之晶片選擇電極122的位置，而且半導體裝置11b的一晶片選擇接點123被重新安置。在一實施例中，在半導體裝置11b中，第二下垂直連接件125與垂直連接件128是繞著第一下垂直連接件124來形成，而且導體129相應地排列成螺旋形。在一實施例中，導體129可排列成矩形螺旋。在一實施例中，導體129可排列成圓螺旋形。在一實施例中，導體129可排列成非圓螺旋形。
參照圖2B所示，在一實施例中，半導體裝置11b可包含一絕緣墊130。絕緣墊130形成於連接垂直連接件128的導體129上。在一實施例中，絕緣墊130僅部分覆蓋連接垂直連接件128的導體129。
圖3為本發明一實施例之示意圖，其例示複數垂直件的排列。前述實施例之第一下垂直連接件124、第二下垂直連接件125及垂直連接件128可根據圖3實施例來安排。前述實施例之上垂直連接件127與垂直連接件128可根據圖3實施例來安排。
如圖3所示，晶片封裝之複數垂直連接件32可設置成兩列，如此複數垂直連接件32不會使用過多的晶片封裝的晶粒面積。兩相鄰的垂直連接件32可分開，使得一垂直連接件32位在另一垂直連接件32的禁用區(keep out zones)31外。在一實施例中，複數垂直連接件32可排列成一陣列，其中該陣列是多於3列和3行。
此外，一垂直連接件32的部分可在另一垂直連接件32的禁用區31內，如此複數垂直連接件32可更緊密排列。
圖4為本發明另一實施例之示意圖，其例示複數垂直件的排列。前述實施例之第一下垂直連接件124、第二下垂直連接件125及垂直連接件128可根據圖4實施例來安排。前述實施例之上垂直連接件127與垂直連接件128可根據圖4實施例來安排。
參照圖4所示，晶片封裝之複數垂直連接件32可排列成方形矩陣。如此，較一維排列的垂直連接件，複數垂直連接件32使用較少的面積。類似地，兩相鄰的垂直連接件32可分開，使得一垂直連接件32位在另一垂直連接件32的禁用區(keep out zones)31外。此外，一垂直連接件32的部分可在另一垂直連接件32的禁用區31內，如此複數垂直連接件32可更緊密排列。
圖5A至5D為示意圖，其例示本發明一實施例之晶片封裝之製備方法。參照圖5A所示，利用蝕刻法或雷射鑽孔法，將複數的孔洞52形成於一基材或底層51上。在一實施例中，複數的孔洞52呈二維排列。在一實施例中，複數的孔洞52排列成矩陣。在一實施例中，複數的孔洞52排列成環。在一實施例中，複數的孔洞52排列成螺旋狀。在一實施例中，複數的孔洞52排列成複數個同心環。之後，導電材料(可為鎢或其他適合材料)填入複數的孔洞52內，以形成複數下垂直連接件125。
如圖5B所示，金屬層53(包括銅、鎢或其他適合材料)形成於底層51，然後使用黃光蝕刻製程，將其圖案化，以形成至少一晶片選擇接點123和一晶片選擇電極122，其中至少一晶片選擇接點123和晶片選擇電極122各連接對應的下垂直連接件124或125，且各晶片選擇接點123更向一相鄰的下垂直連接件125延伸。然後，設置絕緣層126，覆蓋至少一晶片選擇接點123和晶片選擇電極122。
參照圖5C所示，複數個孔洞55形成於絕緣層126。複數個孔洞55對應晶片選擇接點123及一未連接任何晶片選擇接點123的下垂直連接件125。各孔洞55用於至少局部露出晶片選擇接點123的一末端，其中該末端是相對於晶片選擇接點123上連接對應下垂直連接件125的另一 末端；或露出下垂直連接件125的上末端，其中該上末端未連接任何晶片選擇接點123。
在一實施例中，孔洞55呈二維排列。在一實施例中，孔洞55排列成矩陣。在一實施例中，孔洞55排列成環狀。在一實施例中，孔洞55排列成螺旋形。在一實施例中，孔洞55排列成複數同心環。
接著，導電材料(例如但不限於：鎢)填入孔洞55，以獲得複數上垂直連接件127和垂直連接件128，其中該垂直連接件128從底層51延伸並穿過絕緣層126。
然後，沈積如銅、鎢或其他合適材料，以於絕緣層126上形成金屬層。將金屬層圖案化，以形成複數導體129，其中上垂直連接件127和垂直連接件128各連接對應的導體129。
參照圖5D所示，絕緣墊130形成於連接垂直連接件128的導體129上。絕緣墊130可圖形化成僅覆蓋導體129的一部份。
之後，底層51被薄化，以露出下垂直連接件125與垂直連接件128的末端。垂直連接件128垂直地穿過基材121和絕緣層126或穿過半導體裝置的晶粒。
然後，複數導電墊131形成於基材121上。複數導電墊131對應地連接下垂直連接件125和垂直連接件128。
圖6本發明一實施例之晶片封裝1c之堆疊的半導體裝置11c。參照圖6所示，晶片封裝1c可包含複數堆疊的堆疊的半導體裝置11c。各堆疊的半導體裝置11c包含複數下垂直連接件125、複數上垂直連接件127及至少一垂直連接件128，其中垂直連接件128是垂直地穿過半導體裝置11c的晶粒710。上垂直連接件127和下垂直連接件125可形成在不同的高度。一下垂直連接件124連接晶片選擇電極122，其中該晶片選擇電極122用於啟動對應的半導體裝置11c。複數個晶片選擇接點123形成在晶粒710中，而且各晶片選擇接點123連接一上垂直連接件127和一下垂直連接件125。複數導體129形成在晶粒710上，而且各導體129連接一上垂直連接件127或垂直連接件128。
絕緣墊130可形成在連接垂直連接件128的導體129。再 者，下垂直連接件125和垂直連接件128各連接對應的導電墊131，其中導電墊131形成在與導體129相對的對應半導體裝置11c的表面上。凸塊716(含複合結構凸塊)可進一步形成，以電性連接兩堆疊的半導體裝置11c。如圖6所示，凸塊716可對應導電墊131，而各凸塊716連接一導電墊131和一導體129或絕緣墊130。
在另一實施例中，在兩相鄰的堆疊半導體裝置中，在下方的半導體裝置的導體129以焊接或異向性導電膠，電性連接位在上方的半導體裝置上的對應下垂直連接件125。當信號施加在一下垂直連接件125或垂直連接件128，在堆疊中的一對應的半導體裝置可被啟動。
複數半導體裝置然後可設置在電路板上。
在一些實施例中，一半導體裝置包含一晶片。晶片具有複數穿過晶片的垂直連接通路。各垂直連接通路連接在晶片表面的一外部電極和在晶片相對面的一外部電極。各垂直連接通路包含一TSV。複數TSVs以二維方式緊鄰排列，如此相較於傳統使用類似且排成一列的TSVs的半導體裝置，本案實施例之複數TSVs使用較少的面積。因此，更多的半導體裝置可堆疊一起，而不明顯增加晶片封裝的大小。在一些實施例中，一垂直連接通路是在兩外部電極之間垂直地延伸。
本揭露之技術內容及技術特點已揭示如上，然而熟悉本項技術之人士仍可能基於本揭露之教示及揭示而作種種不背離本揭露精神之替換及修飾。因此，本揭露之保護範圍應不限於實施範例所揭示者，而應包括各種不背離本揭露之替換及修飾，並為以下之申請專利範圍所涵蓋。
1‧‧‧晶片封裝
11‧‧‧半導體裝置
12‧‧‧晶粒
121‧‧‧基材
122‧‧‧晶片選擇電極
123‧‧‧晶片選擇接點
124‧‧‧第一下垂直連接件
125‧‧‧第二下垂直連接件
126‧‧‧絕緣層
127‧‧‧上垂直連接件
128‧‧‧垂直連接件
129‧‧‧導體
130‧‧‧絕緣墊

Claims (20)

  1. 一種晶片封裝，包含至少一半導體裝置，該至少一半導體裝置包含：一晶粒，包含一晶粒電路和一基材；一晶片選擇電極，形成於該基材並電性連接該晶粒電路；複數晶片選擇接點，形成於該基材並電性隔離於該晶粒電路；一第一下垂直連接件，貫穿該基材並連接該晶片選擇電極；複數第二下垂直連接件，貫穿該基材並對應連接該些晶片選擇接點；一絕緣層，形成於該基材上；複數上垂直連接件，穿過該絕緣層並對應連接該些晶片選擇接點；一垂直連接件，垂直地穿過該基材與該絕緣層；以及複數導體，形成於該絕緣層上，其中各該導體連接至該些上垂直連接件與該垂直連接件中之一對應者，並延伸至該第一下垂直連接件與該些第二下垂直連接件中一對應者之上方；其中該第一下垂直連接件、該些第二下垂直連接件和該垂直連接件呈二維排列。
  2. 根據申請專利範圍第1項所述之晶片封裝，其中該些導體中至少兩者沿不同方向延伸。
  3. 根據申請專利範圍第1項所述之晶片封裝，其中該些導體中至少兩者是互為垂直延伸。
  4. 根據申請專利範圍第1項所述之晶片封裝，其中該第一下垂直連接件、該些第二下垂直連接件和該垂直連接件呈陣列排列。
  5. 根據申請專利範圍第1項所述之晶片封裝，其中該第一下垂直連接件、該些第二下垂直連接件和該垂直連接件排列成環狀。
  6. 根據申請專利範圍第1項所述之晶片封裝，其中該些導體形成螺旋形。
  7. 根據申請專利範圍第1項所述之晶片封裝，其中該第一下垂直連接件與該些第二下垂直連接件中相鄰兩者之一是位在該第一下垂直連接件與該些第二下垂直連接件中該相鄰兩者之另一之禁用區外。
  8. 根據申請專利範圍第1項所述之晶片封裝，其中該第一下垂直連接件與該些第二下垂直連接件中相鄰兩者之一之部分是位在該第一下垂直連接件與該些第二下垂直連接件中該相鄰兩者之另一之禁用區內。
  9. 根據申請專利範圍第1項所述之晶片封裝，包含複數半導體裝置和一電路板，其中該些半導體裝置對應該些晶片選擇接點，且該些半導體裝置堆疊在該電路板。
  10. 根據申請專利範圍第1項所述之晶片封裝，包含一絕緣墊，其中該絕緣墊設置在連接該垂直連接件的該導體，且該絕緣墊小於對應的該導體。
  11. 一種晶片封裝之製備方法，包含：形成一第一下垂直連接件、複數第二下垂直連接件和一第三下垂直連接件於一半導體裝置之一基材；形成一晶片選擇電極和複數晶片選擇接點於該基材，其中該晶片選擇電極連接該第一下垂直連接件，而該些晶片選擇接點對應地連接該些第二下垂直連接件；形成一絕緣層於該基材上；形成複數上垂直連接件於該絕緣層內，其中該些上垂直連接件對應地連接該些晶片選擇接點和該第三下垂直連接件，而且該第三下垂直連接件和與其連接的該上垂直連接件形成一直的垂直連接件；以及形成複數導體於該絕緣層上，其中該些導體對應地連接該些上垂直連接件和該直的垂直連接件；其中該第一下垂直連接件、該些第二下垂直連接件和該第三下垂直連接件呈二維排列。
  12. 根據申請專利範圍第11項所述之製備方法，其中該些導體中至少兩者沿不同方向延伸。
  13. 根據申請專利範圍第11項所述之製備方法，其中該些導體中至少兩者是互為垂直延伸。
  14. 根據申請專利範圍第11項所述之製備方法，其中該第一下垂直連接件、該些第二下垂直連接件和該第三下垂直連接 件呈陣列排列。
  15. 根據申請專利範圍第11項所述之製備方法，其中該一下垂直連接件、該些第二下垂直連接件和該第三下垂直連接件排列成環狀。
  16. 根據申請專利範圍第11項所述之製備方法，其中該一下垂直連接件、該些第二下垂直連接件和該第三下垂直連接件排列成螺旋形。
  17. 根據申請專利範圍第11項所述之製備方法，其中該第一下垂直連接件、該些第二下垂直連接件和該第三下垂直連接件中相鄰兩者之一是位在該第一下垂直連接件、該些第二下垂直連接件和該第三下垂直連接件中該相鄰兩者之另一之禁用區外。
  18. 根據申請專利範圍第11項所述之製備方法，其中該第一下垂直連接件、該些第二下垂直連接件和該第三下垂直連接件中相鄰兩者之一之部分是位在該第一下垂直連接件、該些第二下垂直連接件和該第三下垂直連接件中該相鄰兩者之另一之禁用區內。
  19. 根據申請專利範圍第11項所述之製備方法，包含堆疊複數半導體裝置，其中在兩相鄰堆疊的半導體裝置中，下方的半導體裝置的該些導體利用焊接或使用異向性導電膠對應連接上方的半導體裝置上的該第一下垂直連接件和該些第二下垂直連接件。
  20. 根據申請專利範圍第11項所述之製備方法，包含形成一絕緣墊於連接該直的垂直連接件的該導體上，其中該絕緣墊 小於對應的該導體。
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