JP2011146513A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2011146513A
JP2011146513A JP2010005912A JP2010005912A JP2011146513A JP 2011146513 A JP2011146513 A JP 2011146513A JP 2010005912 A JP2010005912 A JP 2010005912A JP 2010005912 A JP2010005912 A JP 2010005912A JP 2011146513 A JP2011146513 A JP 2011146513A
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Japan
Prior art keywords
conductor
substrate
chip
semiconductor device
fixed
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JP2010005912A
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English (en)
Inventor
Kazuyoshi Ajiro
和由 網代
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2010005912A priority Critical patent/JP2011146513A/ja
Priority to US13/004,992 priority patent/US20110169165A1/en
Publication of JP2011146513A publication Critical patent/JP2011146513A/ja
Pending legal-status Critical Current

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Abstract

【課題】コスト増加を招くことなく、ＩＣチップの作動により発生する熱等を効率的に排除可能にする。
【解決手段】本発明に係る半導体装置１は、基板１０と、前記基板１０上に固定されるＩＣチップ３と、前記基板１０の表面に配される導電体１１と、前記基板１０の表面及び前記導電体１１を被覆すると共に、前記ＩＣチップ３の固定面に対応する部分に前記導電体１１を露出させる開口部１７が形成されたソルダーレジスト１２と、前記固定面と前記開口部１７による前記導電体１１の露出部１８とに接触する接着剤５とを備える。
【選択図】図１

Description

本発明は、プリント基板上にＩＣ(Integrated Circuit)チップが搭載されてなる半導体装置に関し、特に熱等の不要な要素を排除するための技術に関するものである。
現在、各種電気機器において、所望の機能を提供するＩＣチップがプリント基板上に固定された状態で利用されている。前記ＩＣチップは、その作動に伴い、熱、電気的ノイズ等を発生させるため、上記のような構成の半導体装置には、放熱機能、ノイズ抑制機能等を備えることが要求される。
図５は、従来の半導体装置１０１の構成を例示している。前記半導体装置１０１は、プリント基板１０２上にＡｇペースト等の接着剤１０５を介してＩＣチップ１０３が固定されると共に、樹脂等のパッケージング１０４により全体が被覆されてなるものである。前記プリント基板１０２は、基板１１０の表面に、配線としての導電体１１１が配されると共に、絶縁層としてのソルダーレジスト１１２が被覆されてなる。前記導電体１１１は、前記基板１１０を貫通する複数のビア１１５を介して、前記ＩＣチップ１０３が固定された面からその反対側の面まで延設され、外部デバイスとの接続ポイントである半田ボール１１３と接続している。前記ＩＣチップ１０３は、半導体等からなるサブストレート１２０上に、所定の機能を提供する機能素子群１２１が固定されてなる。前記プリント基板１０２と前記ＩＣチップ１０３とは、ボンディングワイヤ１０６を介して電気信号の送受が可能に接続されている。前記ソルダーレジスト１１２は、前記ＩＣチップ１０３が固定された面において、前記ボンディングワイヤ１０６のボンディングポイント１１４等の接続ポイントを除く全ての部分で前記導電体１１０を被覆している。
また、特許文献１において、３層のＢＧＡ(Ball Grid Array)パッケージが、上下のトレース間に設けられたＶＳＳプレーンと、外周部分の上下面に設けられたＶＳＳトレースと、前記ＶＳＳプレーンと上下面の前記ＶＳＳトレースとを電気的及び熱的に接続するビアとを備える構成が開示されている。これにより、内層に配置された前記ＶＳＳプレーンが低インピーダンスの電流経路を構成するとされている。
また、特許文献２において、絶縁基材の内部に、放熱用の上部金属層と放熱用の下部金属層との２層を互いに離隔して配置し、前記絶縁基材の裏面側に放熱金属層を配置し、前記上部金属層は、凹所の金属メッキ層に接続され、前記上部金属層と前記下部金属層とが金属メッキ層が施されたインナーバイアホールにより接続された構成が開示されている。これにより、ヒートシンクを用いずに放熱性、耐湿性を向上させることができるとされている。
また、特許文献３において、ＩＣチップをプリント回路基板の第１の導体部及び第２の導体部上に、これらを跨ぐように搭載し、前記両導体部をそれぞれ接地させる構成が開示されている。これにより、アナログ回路からの電流とデジタル回路からの電流とがサブストレートを通じて混在することによる不具合を防止できるとされている。
特開平８−１７２１４１号公報 特開平４−４２９８９号公報 特開２００２−３１３９８０号公報
上記図５に示す従来の半導体装置１０１においては、前記接着剤１０５が前記ソルダーレジスト１１２と前記サブストレート１２０との間に介在されている。一般的な前記ソルダーレジスト１１２は、熱伝導性及び電気伝導性が低い性質を有するものである。従って、上記半導体装置１０１においては、前記機能素子部１２１の作動により発生する熱、電気的ノイズ等の排除要素１３０が、前記ソルダーレジスト１１２に遮断され、前記サブストレート１２０内に蓄積されることとなる。このように、従来の半導体装置１０１においては、放熱性能、ノイズ抑制性能等の面で改善の余地がある。
また、上記特許文献１，２に記載の構成は、放熱性等を向上させるために多層構造を採用したものであり、製造工程、部品の増加に伴うコスト増加の問題がある。また、上記特許文献３に記載の構成は、アナログ用及びデジタル用の導体部を個別に用意し、これらの導体部をそれぞれチップエッジよりも外側まで延設するものである。このような構造においては、熱ストレスによりパッケージ内に発生する応力により、配線クラックが生ずる可能性があり、また放熱性の面で改善の余地が大きいものである。
本発明は、上記課題の解決を目的に含むものであり、本発明の一態様は、基板と、前記基板上に固定されるＩＣチップと、前記基板の表面に配される導電体と、前記基板の表面及び前記導電体を被覆すると共に、前記ＩＣチップの固定面に対応する部分に前記導電体を露出させる開口部が形成されたソルダーレジストと、前記固定面と前記開口部による前記導電体の露出部とに接触する接着剤とを備える半導体装置である。
上記態様によれば、前記ソルダーレジストの塗布範囲のうち前記ＩＣチップの固定面に対応する部分が、前記開口部により前記導電体が露出した状態となる。そして、前記接着剤は、前記開口部を介して前記ＩＣチップと前記導電体とに直接接触した状態となる。即ち、前記ＩＣチップから前記導電体までの熱的な伝導性が、前記ソルダーレジストの不介在により、良好となる。これにより、前記ＩＣチップに発生した熱は、前記接着剤及び前記導電体を介して外部に効率的に排除される。また、前記ＩＣチップのサブストレート、前記接着剤等に用いられる材質を選択することにより、前記ＩＣチップから前記導電体までを熱的にだけでなく、電気的にも接続することができ、このような構成によれば、前記ＩＣチップに生じた電気的ノイズ等を排除することも可能となる。
本発明によれば、コスト増加を招くことなく、ＩＣチップの作動により発生する熱等の不要な要素を効率的に排除することが可能となる。
本発明の実施の形態１に係る半導体装置の構成を示す断面図である。 実施の形態１に係るプリント基板のＩＣチップを搭載する前の状態、及び開口部の形状の一例を示す上面図である。 実施の形態１に係るプリント基板のＩＣチップを搭載する前の状態、及び開口部の形状の他例を示す上面図である。 実施の形態１において固定箇所にＩＣチップを搭載した際の断面構造を模式的に示す図である。 従来の半導体装置の構成を示す断面図である。
実施の形態１
図１は、本発明の実施の形態１に係る半導体装置１の構成を示している。前記半導体装置１は、プリント基板２上にＩＣチップ３が搭載されると共に、樹脂等のパッケージング４により被覆されてなるものである。本実施の形態においては、基板１０の表面に銅箔等の前記導電体１１が配されると共に絶縁膜であるソルダーレジスト１２が塗布されてなるプリント基板２上に、接着剤としてＡｇペースト５を用いて前記ＩＣチップ３が固定される。また、前記プリント基板２と前記ＩＣチップ３とは、複数のボンディングワイヤ６により電気信号の送受が可能に接続される。
前記プリント基板２は、前記基板１０、前記導電体１１、前記ソルダーレジスト１２、及び半田ボール１３を含んで構成される。
前記基板１０は、フェノール係樹脂等から構成される板状の部材である。前記基板１０には、その両面を貫通する複数のビア１５が形成されている。
前記導電体１１は、銅箔等から構成され、主に電気配線として使用される。前記導電体１１は、前記ビア１１を介して前記ＩＣチップ３が固定された面からその反対側の面まで延設され、前記半田ボール１３と接続されている。
前記ソルダーレジスト１２は、エポキシ系樹脂等の絶縁性、感光性等を有する合成樹脂膜である。前記ソルダーレジスト１２は、前記導電体１１と前記ボンディングワイヤ６とのボンディングポイント１４等の電気的接続ポイント（パッド、ランド）を除く部分を被覆する。また、本実施の形態に係る前記ソルダーレジスト１２は、前記ＩＣチップ３の固定面に対応する部分に開口部１７を有している。前記開口部１７により、前記導電体１１の一部が露出部１８となる。
前記半田ボール１３は、前記半導体装置１が搭載される外部デバイスとの電気的接続ポイントである。前記半田ボール１３は、前記導電体１１と接続する。
前記ＩＣチップ３は、サブストレート２０、及び機能素子群２１を含んで構成される。
本実施の形態に係る前記サブストレート２０は、単結晶シリコン等の半導体から構成される板状の部材である。前記サブストレート２０上に、所定の機能を提供する前記機能素子群２１が固定される。前記機能素子群２１は、各種半導体素子の組み合わせ等から構成される。前記サブストレート２０の前記機能素子群２１が固定された面とは反対側の面（固定面）が、前記Ａｇペースト５により前記プリント基板２に固定される。
また、図１において、前記サブストレート２０内に排除要素３０が示されている。前記排除要素３０は、前記機能素子群２１の作動により生ずる熱、電気的ノイズ等の不要な要素をイメージ的に表現したものである。
図２及び図３は、前記プリント基板２の前記ＩＣチップ３を搭載する前の状態、及び前記開口部１７の形状を例示している。図２及び図３において、前記ソルダーレジスト１２、前記開口部１７、前記露出部１８（前記導電体１１）、前記ボンディングポイント１４、前記ビア１５、及び前記ＩＣチップ３の固定箇所２５が示されている。両図が示すように、前記開口部１７の形状としては、四角形状、円形状等の各種形状が許容される。前記開口部１７の存在により、前記導電体１１の一部が前記露出部１８として露出した状態となる。本実施の形態においては、前記露出部１８は、前記開口部１７の全範囲に渡って前記導電体１１が敷き詰められた状態（ベタ状態）となっている。また、前記開口部１７（前記露出部１８）は、前記固定箇所２５の範囲内に収まっている。
図４は、前記固定箇所２５に前記ＩＣチップ３を搭載した際の断面構造を模式的に示している。同図が示すように、前記ＩＣチップ３は、前記ソルダーレジスト１２上に前記Ａｇペースト５を介して固定される。この時、前記Ａｇペースト５は、前記開口部１７に充填されることにより、前記ＩＣチップ３の前記サブストレート２０と前記導電体１１の前記露出部１８とに接触する。また、前記露出部１８を含む前記導電体１１は、前記基板１０に形成された前記ビア１５を介して前記半田ボール１３（図１参照）に接続されている。更に、前記サブストレート２０の固定面（前記Ａｇペースト５と接触する面）には、ショットキーバリアの発生を抑制する表面処理が施されている。前記表面処理としては、粗面加工、又は前記固定面に金を蒸着させ電極を形成する処理が好適である。
上記構成により、図１に示すように、前記機能素子群２１の作動により前記サブストレート２０内に生じた前記排除要素３０は、前記サブストレート２０→前記Ａｇペースト５→前記露出部１８（前記導電体１１）→前記ビア１５（前記導電体１１）→前記半田ボール１３→外部へと伝達し、排除される。
また、本実施の形態においては、前記露出部１８が前記ベタ状態となっているため、熱伝導性及び電気伝導性が高く、前記排除要素３０を外部へ放出する効果が高い。また、前記開口部１７（前記露出部１８）は、前記固定箇所２５（図２又は図３参照）の範囲内に収まっているため、前記ＩＣチップ３の固定時に前記Ａｇペースト５等にクラックが発生する可能性が低い。更に、本実施の形態においては、前記サブストレート２０と前記半田ボール１３とが電気的に接続されていると共に、前記サブストレート２０の前記固定面に前記ショットキーバリアの発生を抑制する表面処理が施されていることにより、前記排除要素３０に熱だけでなく電気的ノイズが含まれている場合であっても、ショットキーバリアによる影響が軽減され、効果的にその排除が行われる。
尚、本発明は、上記実施の形態に限られるものではなく、趣旨を逸脱しない範囲で適宜変更することが可能なものである。例えば、上記実施の形態においては、前記プリント基板２としてＢＧＡ型の構成を示したが、本発明はこれに限定するものではない。また、上記実施の形態においては、前記サブストレート２０から前記半田ボール１３までが熱的にだけでなく電気的にも接続された構成を示したが、熱的にだけ接続する構成であってもよい。
１ 半導体装置
２ プリント基板
３ ＩＣチップ
５ Ａｇペースト
６ ボンディングワイヤ
１０ 基板
１１ 導電体
１２ ソルダーレジスト
１３ 半田ボール
１４ ボンディングポイント
１５ ビア
１７ 開口部
１８ 露出部
２０ サブストレート
２１ 機能素子群
３０ 排除要素

Claims (7)

  1. 基板と、
    前記基板上に固定されるＩＣチップと、
    前記基板の表面に配される導電体と、
    前記基板の表面及び前記導電体を被覆すると共に、前記ＩＣチップの固定面に対応する部分に前記導電体を露出させる開口部が形成されたソルダーレジストと、
    前記固定面と前記開口部による前記導電体の露出部とに接触する接着剤と、
    を備える半導体装置。
  2. 前記露出部を含む前記導電体は、前記基板に形成されたビアを介して、前記ＩＣチップが固定された面とは反対側の面に設けられた外部接続用導電体と熱的に接続する、
    請求項１に記載の半導体装置。
  3. 前記露出部は、前記開口部の全範囲に渡って前記導電体が敷き詰められた状態である、
    請求項１又は２に記載の半導体装置。
  4. 前記開口部は、前記固定面の範囲内に収まる、
    請求項１〜３のいずれか１つに記載の半導体装置。
  5. 前記接着剤は、導電性を有し、
    前記固定面は、半導体から構成され、ショットキーバリアの発生を抑制する表面処理が施されている、
    請求項１〜４のいずれか１つに記載の半導体装置。
  6. 前記表面処理は、粗面加工である、
    請求項５に記載の半導体装置。
  7. 前記表面処理は、前記固定面に金を蒸着させ電極を形成する処理である、
    請求項５に記載の半導体装置。
JP2010005912A 2010-01-14 2010-01-14 半導体装置 Pending JP2011146513A (ja)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012070375A1 (en) 2010-11-26 2012-05-31 Canon Kabushiki Kaisha Optical member and imaging apparatus
JP2015156463A (ja) * 2014-01-14 2015-08-27 新光電気工業株式会社 配線基板及び半導体パッケージ
WO2017006391A1 (ja) * 2015-07-03 2017-01-12 ルネサスエレクトロニクス株式会社 半導体装置
WO2022004178A1 (ja) * 2020-07-02 2022-01-06 ソニーセミコンダクタソリューションズ株式会社 インターポーザ、回路装置、インターポーザの製造方法、および回路装置の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352021A (ja) * 2000-06-07 2001-12-21 Sony Corp 半導体パッケージ、半導体パッケージの実装構造及び半導体パッケージの製造方法
JP2007059486A (ja) * 2005-08-22 2007-03-08 Rohm Co Ltd 半導体装置及び半導体装置製造用基板
JP2009516361A (ja) * 2005-10-14 2009-04-16 シリコン・スペース・テクノロジー・コーポレイション 耐放射線性のあるアイソレーション構造及びその製造方法
JP2009267267A (ja) * 2008-04-28 2009-11-12 Tdk Corp 電子部品搭載装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307689A (ja) * 1998-02-17 1999-11-05 Seiko Epson Corp 半導体装置、半導体装置用基板及びこれらの製造方法並びに電子機器
DE10352349B4 (de) * 2003-11-06 2006-11-16 Infineon Technologies Ag Halbleiterchip mit Flip-Chip-Kontakten und Verfahren zur Herstellung desselben
JP2006190771A (ja) * 2005-01-05 2006-07-20 Renesas Technology Corp 半導体装置
US7851896B2 (en) * 2005-07-14 2010-12-14 Chipmos Technologies Inc. Quad flat non-leaded chip package
US7595553B2 (en) * 2006-11-08 2009-09-29 Sanyo Electric Co., Ltd. Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352021A (ja) * 2000-06-07 2001-12-21 Sony Corp 半導体パッケージ、半導体パッケージの実装構造及び半導体パッケージの製造方法
JP2007059486A (ja) * 2005-08-22 2007-03-08 Rohm Co Ltd 半導体装置及び半導体装置製造用基板
JP2009516361A (ja) * 2005-10-14 2009-04-16 シリコン・スペース・テクノロジー・コーポレイション 耐放射線性のあるアイソレーション構造及びその製造方法
JP2009267267A (ja) * 2008-04-28 2009-11-12 Tdk Corp 電子部品搭載装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012070375A1 (en) 2010-11-26 2012-05-31 Canon Kabushiki Kaisha Optical member and imaging apparatus
JP2015156463A (ja) * 2014-01-14 2015-08-27 新光電気工業株式会社 配線基板及び半導体パッケージ
WO2017006391A1 (ja) * 2015-07-03 2017-01-12 ルネサスエレクトロニクス株式会社 半導体装置
JPWO2017006391A1 (ja) * 2015-07-03 2017-10-19 ルネサスエレクトロニクス株式会社 半導体装置
US10134665B2 (en) 2015-07-03 2018-11-20 Renesas Electronics Corporation Semiconductor device
WO2022004178A1 (ja) * 2020-07-02 2022-01-06 ソニーセミコンダクタソリューションズ株式会社 インターポーザ、回路装置、インターポーザの製造方法、および回路装置の製造方法

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