JP2009516361A - 耐放射線性のあるアイソレーション構造及びその製造方法 - Google Patents
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Abstract
【解決手段】種々の形態の放射線によって生じる有害な影響を減少する又は排除するための特別な構造を含む半導体デバイスを、従来の設計及びプロセスを用いて製造する。その半導体デバイスは、1つ或いは複数の寄生アイソレーションデバイス及び/又は埋め込み層の構造を備えている。これら新規性のある構造を適用するための設計及び/又はプロセスステップは、従来のCMOS製造プロセスと互換性があり、したがって、比較的低コストで、比較的容易に導入することができる。
【選択図】図4
Description
Claims (28)
- 半導体デバイスであって、
上面及び底面を有する基板と、
前記基板の前記上面に近接して形成された複数のトランジスタと、
イオン注入によって前記複数のトランジスタの下方に実質的に連続的に延在するようにして形成された、第1の導電型を有し、かつ不純物濃度が前記基板の不純物濃度よりも高い埋め込み層と、
前記埋め込み層からデバイスパッケージのコンタクトへ電流を伝導するように構成され、かつ前記基板の前記底面に形成された金属層とを含むことを特徴とする半導体デバイス。 - 前記基板が、前記第1の導電型を有するバルクシリコンウェハから形成されることを特徴とする請求項1に記載の半導体デバイス。
- 前記基板の前記上面の上に形成されたエピタキシャル層をさらに含み、
前記複数のトランジスタが、前記エピタキシャル層内に形成された複数のソース領域及びドレイン領域をさらに含むことを特徴とする請求項1に記載の半導体デバイス。 - 前記エピタキシャル層が、前記第1の導電型を有していることを特徴とする請求項3に記載の半導体デバイス。
- 前記エピタキシャル層の不純物濃度が、前記基板の前記不純物濃度よりも低いことを特徴とする請求項3に記載の半導体デバイス。
- 前記埋め込み層の配置が、前記基板の前記上面の上方に配置される、前記基板の前記上面の下方に配置される、及び前記基板の前記上面に重なって配置される、のうちのいずれか1つであることを特徴とする請求項3に記載の半導体デバイス。
- 前記金属層が、化学気相蒸着、電気メッキ、又はスパッタリングのうちのいずれか1つ或いは複数を用いて形成されることを特徴とする請求項1に記載の半導体デバイス。
- 前記金属層が、複数の金属層をさらに含むことを特徴とする請求項1に記載の半導体デバイス。
- 前記金属層が、Ti、NiV、Ag、Au、Cr、AuAs、Ni、AuGe、又はAlのうちのいずれか1つ或いは複数をさらに含むことを特徴とする請求項1に記載の半導体デバイス。
- 前記金属層が、前記基板の前記底面に沿って、実質的に連続的に延在することを特徴とする請求項1に記載の半導体デバイス。
- 前記金属層が、前記基板の前記底面に沿ってパターンが形成されることを特徴とする請求項1に記載の半導体デバイス。
- パッケージの少なくとも1つのコンタクト電極が、前記金属層に形成されることをさらに含むことを特徴とする請求項1に記載の半導体デバイス。
- 前記複数のトランジスタのうちの少なくとも1つが電界効果トランジスタであり、
前記電界効果トランジスタが、
第1の幅を有するソース領域と、
第2の幅を有するドレイン領域と、
前記ソース領域及び前記ドレイン領域の間に配置されたチャネル領域とを備え、
前記チャネル領域が、或るチャネル長さを有し、かつ前記第1の幅及び前記第2の幅のそれぞれよりも広い幅の第3の幅を有し、それによって、少なくとも1つのチャネル拡張部を形成し、
前記少なくとも1つのチャネル拡張部が、前記ソース領域及び前記ドレイン領域の間で、前記チャネル長さよりも長い、ネットチャネルエッジ長さを有することを特徴とする請求項1に記載の半導体デバイス。 - 前記少なくとも1つのチャネル拡張部が、
前記ソース領域及び前記ドレイン領域から離隔して、前記少なくとも1つのチャネル拡張部の長さ方向に沿って配置されたチャネル拡張部不純物領域をさらに含むことを特徴とする請求項13に記載の半導体デバイス。 - 前記チャネル拡張部不純物領域が、少なくとも1つの前記ソース領域及び前記ドレイン領域の深さよりも深い深さまで延在していることを特徴とする請求項13に記載の半導体デバイス。
- 前記チャネル拡張部不純物領域が、前記基板の前記不純物濃度よりも高い不純物濃度を有することを特徴とする請求項13に記載の半導体デバイス。
- 前記チャネル拡張部不純物領域が、第2の導電型を有していることを特徴とする請求項13に記載の半導体デバイス。
- 方法であって、
上面及び底面を有するウェハを供給するステップと、
前記ウェハへイオンを注入して、第1の導電型を有し、かつ不純物濃度が前記ウェハの不純物濃度よりも高い埋め込み層を、前記ウェハ内に実質的に連続的に形成するステップと、
前記ウェハの前記上面に近接して複数のトランジスタを形成するステップと、
前記ウェハの前記底面に金属層を蒸着するステップとを含み、
前記複数のトランジスタが、前記埋め込み層の下方にて延在し、
前記金属層が、前記埋め込み層からデバイスパッケージのコンタクトへ電流を伝導するように構成されていることを特徴とする方法。 - 前記ウェハが、前記第1の導電型を有するバルクシリコンウェハであることを特徴とする請求項18に記載の方法。
- 前記ウェハが、
基板と、
前記基板上に形成された半導体のエピタキシャル層とを含むことを特徴とする請求項18に記載の方法。 - 前記イオンを注入するステップが、
前記埋め込み層を、前記基板内、前記半導体のエピタキシャル層内、並びに一部を前記基板内かつ一部を前記半導体のエピタキシャル層内、のいずれか1つに配置するために、前記ウェハに対して、或るエネルギ及び或る角度でイオンを注入するステップをさらに含むことを特徴とする請求項20に記載の方法。 - 前記金属層を蒸着するステップが、
前記金属層を化学気相蒸着を用いて蒸着するステップ、前記金属層を電気メッキするステップ、又は前記金属層をスパッタリングするステップのいずれか1つ或いは複数のステップをさらに含むことを特徴とする請求項18に記載の方法。 - 前記金属層を蒸着するステップが、
前記ウェハの前記底面に複数の金属層を蒸着するステップをさらに含むことを特徴とする請求項18に記載の方法。 - 前記ウェハの厚さを、機械的研削、化学機械研磨、ウェットエッチング、又はドライエッチングのうちの1つ或いは複数を用いて薄くするステップをさらに含むことを特徴とする請求項18に記載の方法。
- 前記複数のトランジスタを形成するステップが、
第1のウェル領域内に、第1の幅を有するソース領域を形成するステップと、
前記第1のウェル領域内に、第2の幅を有するドレイン領域を形成するステップと、
前記第1のウェル領域内にチャネル領域を形成するステップとをさらに含み、
前記チャネル領域が、前記ソース領域及び前記ドレイン領域の間に配置され、
前記チャネル領域が、或るチャネル長さを有し、前記第1の幅及び前記第2の幅のそれぞれよりも広い幅の第3の幅を有し、それによって、少なくとも1つのチャネル拡張部を形成し、
前記少なくとも1つのチャネル拡張部が、前記ソース領域及び前記ドレイン領域の間で、前記チャネル長さよりも長い、ネットチャネルエッジ長さを有していることを特徴とする請求項18に記載の方法。 - 前記チャネル領域を形成するステップが、
前記ソース領域及びドレイン領域から離隔して、前記少なくとも1つのチャネル拡張部の長さ方向に沿って配置されるようにチャネル拡張部不純物領域を形成するために、イオンを注入するステップをさらに含むことを特徴とする請求項25に記載の方法。 - 前記チャネル拡張部不純物領域が、少なくとも1つの前記ソース領域及び前記ドレイン領域の深さよりも深い深さまで延在することを特徴とする請求項25に記載の方法。
- 前記チャネル拡張部不純物領域が、前記ウェハの前記不純物濃度よりも高い不純物濃度を有することを特徴とする請求項25に記載の方法。
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JP2011146513A (ja) * | 2010-01-14 | 2011-07-28 | Renesas Electronics Corp | 半導体装置 |
KR101383510B1 (ko) * | 2011-12-07 | 2014-04-08 | 경희대학교 산학협력단 | Soi 로직 회로의 바이어스 회로 |
WO2016132418A1 (ja) * | 2015-02-18 | 2016-08-25 | 富士電機株式会社 | 半導体集積回路 |
JPWO2016132418A1 (ja) * | 2015-02-18 | 2017-05-25 | 富士電機株式会社 | 半導体集積回路 |
US10217765B2 (en) | 2015-02-18 | 2019-02-26 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit |
JP2018037443A (ja) * | 2016-08-29 | 2018-03-08 | 富士電機株式会社 | 半導体集積回路及び半導体モジュール |
KR102009458B1 (ko) * | 2019-04-15 | 2019-08-09 | 경희대학교 산학협력단 | 완전 공핍형 실리콘 온 인슐레이터 공정을 이용한 메모리 장치의 안정도에 대한 총 이온화 선량 효과의 측정 방법 |
Also Published As
Publication number | Publication date |
---|---|
EP1949425A2 (en) | 2008-07-30 |
US20070141794A1 (en) | 2007-06-21 |
US20130059421A1 (en) | 2013-03-07 |
US20100267212A1 (en) | 2010-10-21 |
US8252642B2 (en) | 2012-08-28 |
JP5036719B2 (ja) | 2012-09-26 |
WO2007061531A3 (en) | 2009-04-30 |
US8278719B2 (en) | 2012-10-02 |
WO2007061531A2 (en) | 2007-05-31 |
EP1949425A4 (en) | 2010-08-18 |
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