TWI527174B - 具有半導體元件之封裝結構 - Google Patents

具有半導體元件之封裝結構 Download PDF

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TWI527174B
TWI527174B TW099140103A TW99140103A TWI527174B TW I527174 B TWI527174 B TW I527174B TW 099140103 A TW099140103 A TW 099140103A TW 99140103 A TW99140103 A TW 99140103A TW I527174 B TWI527174 B TW I527174B
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sidewall
conductive
metal pad
curvature
semiconductor substrate
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TW201222749A (en
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陳國華
蔡莉雯
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日月光半導體製造股份有限公司
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Priority to US13/113,961 priority patent/US9024445B2/en
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Description

具有半導體元件之封裝結構
本發明係關於一種半導體元件及具有半導體元件之封裝結構，詳言之，係關於一種具有導通柱之半導體元件及具有該半導體元件之封裝結構。
習知半導體元件(例如晶片或中介板(Interposer))具有有複數個導通柱(Via)及複數個金屬墊(Metal Pad)，該等金屬墊係位於該等導通柱上方，且電性連接該等導通柱。以俯視觀之，每一金屬墊之面積會大於每一導通柱面積，而且該等金屬墊之外圍側壁係為圓形。因此，該等金屬墊並無法靠的太近，導致該等導通柱之間距並無法有效地縮小。
本發明提供一種具有半導體元件之封裝結構。該封裝結構包括一半導體元件、一晶片及一底膠。該半導體元件包括一基材本體、複數個導通柱(Conductive Vias)、一絕緣材料、一第二保護層及複數個金屬墊(Metal Pad)。該基材本體具有一第一表面、一第二表面及至少一貫孔。該等導通柱係位於該至少一貫孔內。該絕緣材料係位於該等導通柱及該至少一貫孔之側壁之間。該第二保護層係位於該第二表面，且具有至少一開口，以顯露該等導通柱。該等金屬墊係位於該至少一開口內且電性連接至該等導通柱。該等金屬墊包括至少一第一金屬墊，該第一金屬墊具有至少一第一弧狀側壁及至少一第一參考側壁，其中該第一弧狀側壁之曲率與該第一參考側壁之曲率不同。
該晶片係位於該半導體元件上，該晶片具有複數個導體元件，以電性連接該等金屬墊。該底膠係位於該晶片及該半導體元件之間，以包覆該等導體元件。
藉此，該等金屬墊可以更靠近，使得該等導通柱亦可以更靠近，因而，在有限空間內，可以排列較多的導通柱。
參考圖1至圖7，顯示本發明第一實施例之半導體元件之製程之示意圖。參考圖1，提供一基材本體10。該基材本體10包括一第一表面101、一第二表面102及複數個孔洞103。在本實施例中，該基材本體10係為一矽基材，該等孔洞103係為盲孔，且開口於該第一表面101。
參考圖2，形成一絕緣材料11(例如；聚亞醯胺(Polyimide,PI)、環氧樹脂(Epoxy)、苯環丁烯(Benzocyclobutene,BCB)等非導電性高分子)於該等孔洞103之側壁上，且定出複數個中心槽。之後再填滿一導電材料12(例如銅金屬)於該等中心槽內。之後，翻轉180度。
參考圖3，以研磨及/或蝕刻方式移除部份該第二表面102以薄化該基材本體10，使得該等孔洞103變成複數個貫孔104，且該等導電材料12變成複數個導通柱13。
參考圖4，形成一第二保護層(Passivation Layer)14於該第二表面102。該第二保護層14係為非導電性高分子材料，例如：聚亞醯胺(Polyimide,PI)、環氧樹脂(Epoxy)、苯環丁烯(Benzocyclobutene,BCB)等。在本實施例中，該第二保護層14係為一感光性高分子材料，例如是苯環丁烯(Benzocyclobutene,BCB)，且係利用旋轉塗佈(Spin Coating)或噴霧塗佈(Spray Coating)方式形成該第二保護層14。
參考圖5，進行微影製程，以形成至少一開口141，而顯露該等導通柱13。該開口141之尺寸及位置係可由微影製程中所使用之光罩所定義。
參考圖6，形成一金屬層於該第二保護層14上及該開口141內，以接觸該等導通柱13。之後，進行蝕刻製程，以形成複數個金屬墊(Metal Pad)19，而製得本發明第一實施例之半導體元件1。該等金屬墊19彼此互不連接，且該等金屬墊19之尺寸及位置係可由蝕刻製程中所使用之光罩所定義。較佳地，以俯視觀之，每一金屬墊19之面積會大於每一導通柱13之面積。
參考圖7，顯示本發明第一實施例之半導體元件之俯視示意圖。該等金屬墊19包括一第一金屬墊16及複數個原始金屬墊15。該等原始金屬墊15之外圍係為一圓柱狀側壁151。該第一金屬墊16具有一第一弧狀側壁161及一第一參考側壁162，其中該第一弧狀側壁161之曲率與該第一參考側壁162之曲率不同。
參考圖6及7，分別顯示本發明第一實施例之半導體元件之剖視及俯視示意圖。該半導體元件1包括一基材本體10、複數個導通柱13、一絕緣材料11、一第二保護層14及複數個金屬墊19。
該基材本體10具有一第一表面101、一第二表面102及至少一貫孔104。在本實施例中，該基材本體10係為一矽基材，且該至少一貫孔104係貫穿該基材本體10。該等導通柱13係位於該至少一貫孔104。在本實施例中，該等導通柱13係為實心柱狀。
該絕緣材料11係位於該等導通柱13及該至少一貫孔104之側壁之間。該第二保護層14係位於該第二表面102，且具有至少一開口141，以顯露該等導通柱13。該等金屬墊19係位於該至少一開口141內，且接觸及電性連接至該等導通柱13。
在本實施例中，該基材本體10具有複數個貫孔104，每一導通柱13係位於每一貫孔104內。該第二保護層14具有複數個開口141，每一開口141係顯露每一導通柱13。每一金屬墊19係位於每一開口141內且電性連接至每一導通柱13。該等金屬墊19係延伸至該第二保護層14上。
該等金屬墊19包括一第一金屬墊16及複數個原始金屬墊15。該等原始金屬墊15之外圍係為一圓柱狀側壁151。該第一金屬墊16具有至少一第一弧狀側壁161及至少一第一參考側壁162，其中該第一弧狀側壁161之曲率與該第一參考側壁162之曲率不同。因此，該等原始金屬墊15以俯視觀之係為一個完整之圓形，該第一金屬墊16以俯視觀之並非一個完整之圓形。較佳地，該第一參考側壁162之曲率小於該第一弧狀側壁161之曲率。在本實施例中，該第一參考側壁162係為一平直面，其曲率為0。或者，該第一參考側壁162也可以是弧狀，但是其曲率小於該第一弧狀側壁161之曲率。
該第一金屬墊16具有一第一延伸部163及一第二延伸部164，該第一延伸部163係延伸至該第一弧狀側壁161，該第二延伸部164係延伸至該第一參考側壁162，該第二延伸部164之長度係小於該第一延伸部163之長度。
該第一金屬墊16下之導通柱13具有一中心軸17a，該原始金屬墊15下之導通柱13具有一中心軸17b，該中心軸17a與該中心軸17b間之距離係為一第一間距P1，該二個中心軸17b間之距離係為一第二間距P2。由於該第一金屬墊16具有該第一參考側壁162，且該第一參考側壁162之曲率小於該第一弧狀側壁161之曲率，因此該第一間距P1可以小於第二間距P2。因此，該等導通柱13可以更靠近。
參考圖8，顯示本發明第二實施例之半導體元件之剖視示意圖。本實施例之半導體元件2與第一實施例之半導體元件1(圖6)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於，本實施例之半導體元件2更包括一第一保護層28。該第一保護層28係與該第二保護層14相同。該第一保護層28位於該第一表面101，且具有至少一開口281，以顯露該等導通柱13。在本實施例中，部份該等金屬墊19(例如金屬墊29)更位於該第一保護層28之開口281內且電性連接至該等導通柱13。位於該第一表面101之該等金屬墊29之結構與位於該第二表面102之該等金屬墊19之結構對稱且相等。
參考圖9，顯示本發明第三實施例之半導體元件之剖視示意圖。本實施例之半導體元件3與第一實施例之半導體元件1(圖6)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於，本實施例之半導體元件3更包括一電路層38及複數個導接元件39。該電路層38位於該第一表面101，且電性連接至該等導通柱13。該等導接元件39位於該電路層38上。在本實施例中，每一導接元件39包括一銲墊391及一凸塊392。要注意的是，該電路層38可以具有一重佈層(Redistribution Layer,RDL)，而可以重新分配該等導接元件39之位置。
參考圖10及11，分別顯示本發明第四實施例之半導體元件之剖視及俯視示意圖。本實施例之半導體元件4與第一實施例之半導體元件1(圖6)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於，該等導通柱43係為中空環柱狀，且該半導體元件4更包括一內絕緣材料48。該內絕緣材料48係位於該等導通柱43內。
參考圖12及13，分別顯示本發明第五實施例之半導體元件之剖視及俯視示意圖。該半導體元件5包括一基材本體10、複數個導通柱13、一絕緣材料11、一第二保護層14及複數個金屬墊19。
該基材本體10具有一第一貫孔104a及一第二貫孔104b。該等導通柱13包括一第一導通柱13a及一第二導通柱13b。該第一導通柱13a係位於該第一貫孔104a內，該第二導通柱13b係位於該第二貫孔104b內。該絕緣材料11包括一第一絕緣材料11a及一第二絕緣材料11b。該第一絕緣材料11a係位於該第一導通柱13a及該第一貫孔104a之側壁之間，該第二絕緣材料11b係位於該第二導通柱13b及該第二貫孔104b之側壁之間。該第二保護層14具有一第一開口141a及一第二開口141b，該第一開口141a係顯露該第一導通柱13a，該第二開口141b係顯露該第二導通柱13b。
該等金屬墊19包括一第一金屬墊16及一第二金屬墊16b。該第一金屬墊16係位於該第一開口141a內且電性連接至該第一導通柱13a，該第一金屬墊16具有至少一第一弧狀側壁161及至少一第一參考側壁162，該第一弧狀側壁161之曲率與該第一參考側壁162之曲率不同。該第二金屬墊16b係位於該第二開口141b內且電性連接至該第二導通柱13b，該第二金屬墊16b具有至少一第二弧狀側壁161b及至少一第二參考側壁162b，該第二弧狀側壁161b之曲率與該第二參考側壁162b之曲率不同，且該第一參考側壁162係面對該第二參考側壁162b。
該第一導通柱13a具有一第一中心軸18a，該第二導通柱13b具有一第二中心軸18b，該第一中心軸18a及該第二中心軸18b之距離定義為一第三間距P3，該第三間距P3係小於該第一間距P1(圖6)，同時亦小於該第二間距P2(圖6)，因此該第一導通柱13a及該第二導通柱13b可以更靠近。
在本實施例中，該第一弧狀側壁161定義出一第一半徑r1，該第二弧狀側壁161b定義出一第二半徑r2，該第三間距P3係小於該第一半徑r1及該第二半徑r2之和。亦即：
P3＜r1+r2
參考圖14及15，分別顯示本發明第六實施例之半導體元件之剖視及俯視示意圖。本實施例之半導體元件6與第五實施例之半導體元件5(圖12及13)大致相同，其中相同之元件賦予相同之編號。本實施例與第五實施例之不同處在於，該第一貫孔104a、該第二貫孔104b、該第一絕緣材料11a及該第二絕緣材料11b之結構。在本實施例中，該第一貫孔104a及該第二貫孔104b並非圓柱狀，而是具有一弧狀側壁及一參考側壁。因此，該第一絕緣材料11a具有至少一第一弧狀側壁111a及至少一第一參考側壁112a，該第一絕緣材料11a之第一參考側壁112a係對應該第一金屬墊16之第一參考側壁162。該第二絕緣材料11b具有至少一第二弧狀側壁111b及至少一第二參考側壁112b，該第二絕緣材料11b之第二參考側壁112b係對應該第二金屬墊16b之第二參考側壁162b。
該第一中心軸18a及該第二中心軸18b之距離定義為一第四間距P4，該第四間距P4係小於該第三間距P3(圖13)，因此該第一導通柱13a及該第二導通柱13b可以更靠近。
參考圖16及17，分別顯示本發明第七實施例之半導體元件之剖視及俯視示意圖。本實施例之半導體元件7與第五實施例之半導體元件5(圖12及13)大致相同，其中相同之元件賦予相同之編號。本實施例與第五實施例之不同處在於，該第一導通柱13a及該第二導通柱13b係位於同一貫孔704內。
參考圖18及19，分別顯示本發明第八實施例之半導體元件之剖視及俯視示意圖。本實施例之半導體元件8與第七實施例之半導體元件7(圖16及17)大致相同，其中相同之元件賦予相同之編號。本實施例與第七實施例之不同處在於，在第七實施例中，該第二保護層14之每一開口141a,141b係顯露每一導通柱13a,13b。然而，在本實施例中，該第二保護層14之開口141c之面積係大於該至少二個導通柱13a,13b之截面積之和，以顯露該至少二個導通柱13a,13b。較佳地，該開口141c之面積係略小於該貫孔704之面積。因此，該等導通柱13a,13b之間不會有該第二保護層14。
參考圖20及21，分別顯示本發明第九實施例之半導體元件之剖視及俯視示意圖。本實施例之半導體元件9與第一實施例之半導體元件1(圖6)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於，在本實施例中，部分該等金屬墊19(即該等金屬墊96)具有複數個第一弧狀側壁961及複數個第一參考側壁962。因此該等導通柱13可以更靠近。藉此，在有限空間內，可以排列較多的導通柱13。
參考圖22及23，分別顯示本發明第十實施例之半導體元件之剖視及俯視示意圖。本實施例之半導體元件9a與第九實施例之半導體元件9(圖21)大致相同，其中相同之元件賦予相同之編號。本實施例與第九實施例之不同處在於，在本實施例中，該等導通柱13係位於同一貫孔904內，且該第二保護層14之開口141d之面積係大於該等個導通柱13之截面積之和，以顯露該等導通柱13。因此，部分該等金屬墊19(即該等金屬墊96)係位於該等導通柱13及該絕緣材料11上，且未接觸該第二保護層14。
參考圖24，顯示本發明第十一實施例之具有半導體元件之封裝結構之剖面示意圖。該封裝結構9b包括一半導體元件1、一晶片90及一底膠(Underfill)92。在本實施例中，該半導體元件1係為本發明第一實施例之半導體元件1(圖6)。然而，在其他實施例中，該半導體元件1係可置換成本發明第二至十實施例之半導體元件。該晶片90係位於該半導體元件1上。該晶片90具有複數個導體元件91(例如銲球)，以接觸且電性連接該等金屬墊19。該底膠91係位於該晶片90及該半導體元件1之間，以包覆且保護該等導體元件91。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
P1．．．第一間距
P2．．．第二間距
P3．．．第三間距
P4．．．第四間距
r1．．．第一半徑
r2．．．第二半徑
1．．．本發明第一實施例之半導體元件
2．．．本發明第二實施例之半導體元件
3．．．本發明第三實施例之半導體元件
4．．．本發明第四實施例之半導體元件
5．．．本發明第五實施例之半導體元件
6．．．本發明第六實施例之半導體元件
7．．．本發明第七實施例之半導體元件
8．．．本發明第八實施例之半導體元件
9．．．本發明第九實施例之半導體元件
9a．．．本發明第十實施例之半導體元件
9b．．．本發明第十一實施例之封裝結構
10．．．基材本體
11．．．絕緣材料
11a．．．第一絕緣材料
11b．．．第二絕緣材料
13．．．導通柱
13a．．．第一導通柱
13b．．．第二導通柱
14．．．第二保護層
15．．．原始金屬墊
16．．．第一金屬墊
16b．．．第二金屬墊
17a．．．中心軸
17b．．．中心軸
18a．．．第一中心軸
18b．．．第二中心軸
19．．．金屬墊
28．．．第一保護層
29．．．金屬墊
38．．．電路層
39．．．導接元件
43．．．導通柱
48．．．內絕緣材料
90．．．晶片
91．．．底膠
96．．．金屬墊
101．．．基材本體之第一表面
102．．．基板本體之第二表面
103．．．孔洞
104．．．貫孔
104a．．．第一貫孔
104b．．．第二貫孔
111a．．．第一弧狀側壁
111b．．．第二弧狀側壁
112a．．．第一參考側壁
112b．．．第二參考側壁
141．．．開口
141a．．．第一開口
141b．．．第二開口
141c．．．開口
141d．．．開口
151．．．圓柱狀側壁
161．．．第一弧狀側壁
161b．．．第二弧狀側壁
162．．．第一參考側壁
162b．．．第二參考側壁
163．．．第一延伸部
164．．．第二延伸部
281．．．開口
391．．．銲墊
392．．．凸塊
704．．．貫孔
904．．．貫孔
961．．．第一弧狀側壁
962．．．第一參考側壁
圖1至圖7顯示本發明第一實施例之半導體元件之製程之示意圖；
圖8顯示本發明第二實施例之半導體元件之剖視示意圖；
圖9顯示本發明第三實施例之半導體元件之剖視示意圖；
圖10顯示本發明第四實施例之半導體元件之剖視示意圖；
圖11顯示本發明第四實施例之半導體元件之俯視示意圖；
圖12顯示本發明第五實施例之半導體元件之剖視示意圖；
圖13顯示本發明第五實施例之半導體元件之俯視示意圖；
圖14顯示本發明第六實施例之半導體元件之剖視示意圖；
圖15顯示本發明第六實施例之半導體元件之俯視示意圖；
圖16顯示本發明第七實施例之半導體元件之剖視示意圖；
圖17顯示本發明第七實施例之半導體元件之俯視示意圖；
圖18顯示本發明第八實施例之半導體元件之剖視示意圖；
圖19顯示本發明第八實施例之半導體元件之俯視示意圖；
圖20顯示本發明第九實施例之半導體元件之剖視示意圖；
圖21顯示本發明第九實施例之半導體元件之俯視示意圖；
圖22顯示本發明第十實施例之半導體元件之剖視示意圖；
圖23顯示本發明第十實施例之半導體元件之俯視示意圖；及
圖24顯示本發明第十一實施例之具有半導體元件之封裝結構之剖面示意圖。
P1．．．第一間距
P2．．．第二間距
1．．．本發明第一實施例之半導體元件
11．．．絕緣材料
13．．．導通柱
14．．．第二保護層
15．．．原始金屬墊
16．．．第一金屬墊
19．．．金屬墊
104．．．貫孔
151．．．圓柱狀側壁
161．．．第一弧狀側壁
162．．．第一參考側壁

Claims (18)

  1. 一種半導體基材，包括：複數個導通柱(Conductive Vias)，該等導通柱之每一者安置於一絕緣貫孔內且具有電性連接至該等導通柱之一金屬墊(Metal Pad)，其中一第一導通柱包括一第一金屬墊，該第一金屬墊具有一弧狀(curved)側壁及一參考側壁，該弧狀側壁之一曲率與該參考側壁之一曲率不同，且該第一金屬墊之該弧狀側壁定義一半徑，該半徑大於自該第一導通柱之一中心軸至相鄰之一第二導通柱之一第二金屬墊之一周邊的一距離。
  2. 如請求項1之半導體基材，其中該參考側壁之該曲率實質上為0。
  3. 如請求項1之半導體基材，其中該參考側壁面對該第二導通柱。
  4. 如請求項1之半導體基材，其中該第一導通柱之該中心軸與相鄰之該第二導通柱之一中心軸之間的一距離定義為一間距，該第一金屬墊之該弧狀側壁定義一第一半徑，該第二導通柱之該第二金屬墊之一弧狀側壁定義一第二半徑，及該間距等於或小於該第一半徑與該第二半徑之和。
  5. 如請求項1之半導體基材，其中該第一金屬墊具有一截角圓形之一形狀。
  6. 如請求項1之半導體基材，其中該第一導通柱係安置於 一第一貫孔內，該第一貫孔包括一弧狀側壁及一參考側壁。
  7. 如請求項6之半導體基材，其中該第一貫孔之該弧狀側壁之一曲率不同於該第一貫孔之該參考側壁之一曲率。
  8. 如請求項6之半導體基材，其中該第一貫孔之該參考側壁之該曲率實質上為0。
  9. 如請求項1之半導體基材，其中該第一導通柱及相鄰之該第二導通柱係安置於相同的貫孔內。
  10. 如請求項1之半導體基材，其中該第一導通柱及至少兩個其他之導通柱係安置於相同的貫孔內。
  11. 如請求項1之半導體基材，其中相鄰之該第二導通柱之該第二金屬墊具有一弧狀側壁及一參考側壁，且該弧狀側壁之一曲率不同於該參考側壁之一曲率，及其中該第一金屬墊之該參考側壁面對該第二金屬墊之該參考側壁。
  12. 一種半導體封裝，包括：一基材，其包含複數個導通柱(Conductive Vias)，該等導通柱之每一者安置於絕緣之一貫孔內且具有電性連接至該等導通柱之一金屬墊，其中一第一導通柱包括一第一金屬墊，當相對於該基材之頂部觀之時，該第一金屬墊顯示實質上如一截角圓形，此一形狀允許將該第一導通柱置放於更接近而沒有電性接觸之相鄰之一第二導通柱，其中該第一金屬墊之該弧狀側壁定義一半徑，該半徑大於自該第一導通柱之一中心軸至相鄰之 該第二導通柱之一第二金屬墊之一周邊的一距離；一被動層，安置於相鄰該基材且具有開口以顯露該等導通柱；及一晶片，耦接至該基材，該晶片具有複數個導體元件以電性連接該等金屬墊。
  13. 如請求項12之半導體封裝，其中該第一金屬墊包括一弧狀側壁及一參考側壁，其中該弧狀側壁之一曲率不同於該參考側壁之一曲率。
  14. 如請求項13之半導體封裝，其中該考側壁面墊該第二導通柱。
  15. 如請求項12之半導體封裝，其中該第一導通柱及該第二導通柱係安置於相同的貫孔內。
  16. 如請求項12之半導體封裝，其中該第一導通柱及該第二導通柱係安置於不同的貫孔內。
  17. 如請求項12之半導體封裝，其中當相對於該基材之頂部觀之時，該第二導通柱之該第二金屬墊顯示實質上如一截角圓形。
  18. 如請求項17之半導體封裝，其中該第二導通柱之該第二金屬墊包括一弧狀側壁及一參考側壁，及其中該弧狀側壁之一曲率不同於該參考側壁之一曲率。
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