CN101728364A - 芯片封装体及制作方法 - Google Patents

芯片封装体及制作方法 Download PDF

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CN101728364A
CN101728364A CN200910171343A CN200910171343A CN101728364A CN 101728364 A CN101728364 A CN 101728364A CN 200910171343 A CN200910171343 A CN 200910171343A CN 200910171343 A CN200910171343 A CN 200910171343A CN 101728364 A CN101728364 A CN 101728364A
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chip
electric conductor
packing
base board
board unit
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高东均
李正
安载善
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开了一种芯片封装体及制作方法。该芯片封装体，包括一积层基板、至少一芯片、多个导电体、一封装胶体以及一遮蔽层。芯片配置于积层基板上。导电体配置于积层基板上且环绕芯片。封装胶体至少包覆芯片、部分积层基板与导电体。遮蔽层配置于封装胶体上，且覆盖封装胶体与部分地覆盖至少每一导电体暴露于封装胶体的一上表面。

Description

芯片封装体及制作方法
技术领域
本发明是有关于一种半导体装置，且特别是有关于一种芯片封装体及制作方法。
背景技术
电磁干扰(electro-magnetic interference)对于大多数的电子产品或系统而言是一严肃且富有挑战性的问题。由于电磁干扰常中断、阻碍、降低或限制电子装置或整体电路系统的效能表现，因此需要有效的电磁干扰屏蔽，以确保电子装置或系统的效率与安全操作。
电磁干扰屏蔽的效能对于小尺寸、高密度的封装体或应用于高频率的敏感电子仪器非常重要。一般而言，大都是通过增加金属板和/或导电性的垫圈来提升电磁干扰屏蔽的效能，但此方式会提高制造成本。
发明内容
本发明提供一种芯片封装体的制作方法，可提供较佳的设计灵活性。
本发明提供一种具有提升电磁干扰屏蔽效能的芯片封装体。
本发明提出一种芯片封装体，其包括一积层基板、至少一配置于积层基板上的芯片、多个导电体、一封装胶体以及一遮蔽层。导电体配置于积层基板上且环绕芯片。封装胶体至少包覆芯片、部分积层基板与导电体，但部分地暴露出这些导电体的多个上表面。遮蔽层配置于封装胶体上，且覆盖封装胶体与部分地覆盖每一导电体暴露于封装胶体的上表面。
在本发明一实施例中，上述这些导电体可由焊料或部分的导线架或部分的印刷电路板所组成。
在本发明一实施例中，上述这些导电体可排列于积层基板的边界线，且暴露出每一导电体的至少一侧壁。
在本发明一实施例中，上述这些导电体可沿着积层基板的边界线排列，且未暴露出每一导电体的多个侧壁。
在本发明一实施例中，上述芯片通过多个凸块电性连接至芯片封装体的积层基板。
本发明提供一种芯片封装体的制作方法。首先，提供一阵列基板。阵列基板具有多个基板单元，其中每一基板单元是由多条切割线所定义，且每一基板单元上具有一芯片贴附区域。接着，形成多个导电体于每一基板单元上，且这些导电体环绕芯片贴附区域配置。配置至少一芯片于每一基板单元的芯片贴附区域上，其中芯片电性连接至基板单元，且芯片与这些导电体相互分离。形成一封装胶体于阵列基板上，以包覆芯片、部分这些基板单元与这些导电体。进行一标记制程以移除部分封装胶体至暴露出每一导电体的一上表面。然后，形成一遮蔽层于封装胶体上，以覆盖封装胶体与每一导电体被暴露出的上表面。最后，进行一单体化制程，以形成多个芯片封装体。
在本发明一实施例中，上述这些导电体排列于阵列基板的这些切割线与每一基板单元的多条边界线，或相距一间隔距离而环绕每一基板单元的这些边界线配置。
在本发明一实施例中，上述这些导电体是由一金属材料所形成，且这些导电体形成方式包括喷涂法(spraying process)、溅镀法(sputtering process)或电镀法(plating process)，或者，这些导电体是由一焊料所形成，且这些导电体形成方式包括喷涂法或印刷法。
在本发明一实施例中，上述标记制程包括一雷射挖空制程(laserdigging process)或一雷射钻孔制程(laser drilling process)。
基于上述，遮蔽层与其所连接的导电体配置于基板上的作用可视为芯片封装体周围防电磁干扰辐射的电磁干扰屏蔽。在本发明中，通过遮蔽层与具有弹性且多种设计型态的导电体，即可达成一完整的电磁干扰屏蔽的效果。因此，遮蔽层与导电体可提高芯片封装体的电磁干扰屏蔽效果，使芯片封装体具有较佳的电磁干扰屏蔽效能。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1G为本发明一实施例一种芯片封装体的制作方法；
图2为本发明一实施例一种芯片封装体的剖面示意图；
图3为本发明另一实施例一种芯片封装体的剖面示意图。
主要元件符号说明：
10、20-芯片封装体； 30-封装结构；    100-阵列基板；
102-基板单元；      102a-上表面；    103-芯片贴附区域；
104-接点；          106-凸块；       108-接地孔；
110-导电体；        110a-上表面；    110b-侧壁；
120-芯片；          130-封装胶体；   130b-侧壁；
140-遮蔽层；        d-间隔距离。
具体实施方式
本发明所述的芯片封装体的制作方法可用来制作多种封装结构，其中以制作堆栈式封装体、多层封装体或具有高频率装置的封装体(包括具有射频装置的封装体)最为适合。此外，本发明的芯片封装体的制作方法与利用积层基板的制造方法或阵列基板的制作方法的封装制程相互符合。
图1A至图1G为本发明一实施例一种芯片封装体的制作方法。在此必须说明的是，为了方便说明起见，图1A、图1B、图1B’与图1C为立体示意图，而1D至图1G为剖面示意图。
请先参考图1A，提供一阵列基板100。阵列基板100具有多个基板单元102(是由后续图示为虚线的切割线所定义)，其中每一基板单元102上包括多个接点104。这些接点104排列于每一基板单元102的芯片贴附区域103内。这些接点104的作用如同覆晶接合技术中的凸块焊垫。阵列基板100可为一积层基板，其例如是一印刷电路板(PrintedCircuit Board，PCB)。
接着，请参考图1B，多个导电体110形成于每一基板单元102的上表面102a上，且位于芯片贴附区域103外。较佳地，导电体110环绕每一基板单元102的边界或周长配置。请参考图1B，这些个别独立的导电体110排列于基板单元102的边界线(虚线)上。在本实施例中，后续的切割制程会沿着这些切割线而切穿这些导电体110。
此外，请参考图1B′，这些个别独立的导电体110也可沿着基板单元102的边界线排列，但不位于基板单元102的边界线(虚线)上。这些导电体110可排列接近于基板单元102的边界线，且这些导电体110与基板单元102的边界线相距一小间隔距离d，而间隔距离d可依据产品的需求而自由调整。因此，后续的切割制程虽然会沿着这些切割线但不会切穿这些导电体110。
导电体110例如是由一焊料所制成。当然，在其他实施例中，导电体110亦可以是一导电承载器的一部分，其中导电承载器例如是一导线架或一积层印刷电路板。导电体110的形状可为多边形的块状体(请参考图1B或图1B’的矩形块状体)。当然，导电体110的形状亦可以是块状、条状或甚至是一彼此相互连接的环状结构。一般来说，导电体110的形状或尺寸可依照屏蔽的需要、封装体电性的特性，或甚至是依据制程的参数而自由调整。
如果是利用一多层基板，例如是一多层印刷电路板，则可通过积层基板的制作过程中来形成所需的导电体110。也就是说，在形成基板上走线(trace)的过程中，亦同时形成导电体110，其中导电体110是除了走线之外的图案化金属块。
接着，请参考图1C，至少一芯片120配置于每一基板单元102的芯片贴附区域103内。虽然在此是提供芯片120配置于芯片贴附区域103内，但其他实施例中，亦可以是提供多个表面黏着型组件贴附于芯片贴附区域103内，此仍属于本发明可采用的技术方案，不脱离本发明所欲保护的范围。芯片120通过多个凸块106(请参考图1D)电性连接至基板单元102的这些接点104，其中这些凸块106介于芯片120与这些接点104之间。虽然在此是以覆晶接合技术作为说明，但于其他实施例中，亦包括利用打线接合技术来电性连接芯片120与这些接点104，仍属于本发明可采用的技术方案，不脱离本发明所欲保护的范围。芯片120与这些导电体110彼此完全分离。
接着，请参考图1D，通过一封胶制程而形成一封装胶体130于阵列基板100上，以包覆这些导电体110、芯片120、这些凸块106与至少一部分的基板单元102。封胶制程例如为一数组封胶制程(over-moldingprocess)。虽然在此所描述导电体110的高度高于芯片120加凸块106的整体高度，但在其他实施例中，亦可自由选择导电体110的高度小于或大于芯片120加凸块106的整体高度。
接着，请参考图1E，进行一标记制程以移除部分位于这些导电体110上的封装胶体130，以至少部分地暴露每一导电体110的上表面110a。这些导电体110的上表面110a可以是部分地或完全地被暴露。标记制程例如是一雷射挖空制程或一雷射钻孔制程。以导电体110环绕每一基板单元102的边界配置为例，标记制程可移除部分封装胶体130，据此形成一环状沟渠(ring-like trench)于封装胶体130内且于导电体110上，并环绕每一基板单元102的边界。
接着，请参考图1F，形成一遮蔽层140于封装胶体130上，以覆盖封装胶体130与导电体110被暴露出的上表面110a。遮蔽层140的形成方式包括喷涂法、电镀法或溅镀法。
最后，请参考图1G，进行一单体化制程，以形成多个独立的芯片封装体10。单体化制程例如是一刀片切割制程。
图2为本发明一实施例一种芯片封装体的剖面示意图。请参考图2，在本实施例中，芯片封装体20包括一基板单元102、多个凸块106、多个导电体110、至少一芯片120、一封装胶体130与一遮蔽层140。基板单元102可为一积层基板，其例如是一两层或一四层积层的印刷电路板基板。芯片120可为一半导体芯片，其例如是一射频(RF)芯片。遮蔽层140的材质可为铜、铝、铜铝合金或是一焊料。芯片120透过凸块106电性连接至基板单元102。封装胶体130包覆部分基板单元102、导电体110与芯片120。此外，遮蔽层140配置于封装胶体130上，且覆盖封装胶体130的上表面与这些导电体110被暴露出的上表面110a。遮蔽层140通过这些导电体110电性连接至基板单元102。
举例来说，导电体110可由一积层印刷电路板或一导线架所组成(例如是一积层印刷电路板或一导线架的一大部分或一小部分)。如果导电体110为一积层印刷电路板的一小部分，遮蔽层140可透过贯穿孔(through vias)或导电体110的电镀贯穿孔(plated through-holes)而电性连接至基板单元102。如果导电体110为一导线架的一部分，遮蔽层140可通过导电体110而电性连接至基板单元102，且导电体110可通过导电黏着层固接于基板单元102上，其中导电黏着层例如是一异方性导电胶膜(Anisotropic Conductive Film，ACF)。当然，导电体110亦可由焊料所组成，其例如是焊料块、焊料条或焊料环状结构。
此外，导电体110连接至基板单元102的一接地孔108，且遮蔽层140通过导电体110与接地孔108而接地。因此，可利用基板表面的金属线路或走线作为一接地平面，使本实施例的遮蔽层140可通过基板的接地平面而接地于封装结构内。在此必须说明的是，每一导电体110的至少一侧壁110b与遮蔽层140的边缘对齐，而此边缘即为切割制程时切穿导电体110所排列的切割线。换言之，每一导电体110的侧壁110b暴露于外。
请参考图3，在其他实施例中，封装胶体130覆盖每一导电体110的这些侧壁110b，也即每一导电体110的侧壁110b未暴露于外。换言之，导电体110除了被暴露的上表面110a外，其余的部分完全包覆于封装胶体130内。封装胶体130的侧壁130b通过单体化制程的切割与遮蔽层140的边缘对齐。基本上，封装结构30是依据图1B’(而不是图1B)的制作方法所形成，且切割制程虽是沿着切割线的方向来进行，但并没有切穿封装体110。
在本实施例芯片封装体的结构中，遮蔽层与导电体配置于基板上的作用可视为一电磁干扰屏蔽，用以保护芯片封装体免于周围辐射源的电磁干扰辐射。
此外，当遮蔽层形成于整个阵列基板与封装胶体上且于单体化制程之前，不需要半切割制程，可增加制程裕度与可靠度。
综上所述，由于遮蔽层与导电体可有效地遮蔽外界电磁干扰辐射，因此可提高本发明芯片封装体的电磁干扰屏蔽的效能。本发明芯片封装体的制作方法，是于封装结构内设立一接地路径，而不是利用一额外的金属板来作为接地平面。因此，这样的设计适合具有高频装置的封装，特别是一射频装置。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (14)

1.一种芯片封装体，包括：
一积层基板；
至少一芯片，配置于该积层基板上；
多个导电体，配置于该积层基板上且环绕该芯片；
一封装胶体，至少包覆该芯片、部分该积层基板与所述导电体；以及，
一遮蔽层，配置于该封装胶体上，且覆盖该封装胶体与部分地覆盖至少每一该导电体暴露于该封装胶体的一上表面。
2.根据权利要求1的芯片封装体，其中至少暴露每一该导电体的一侧壁，且该侧壁与该遮蔽层的边缘对齐。
3.根据权利要求1的芯片封装体，其中该封装胶体覆盖所述导电体的多个侧壁，且该封装胶体的边缘与该遮蔽层的边缘对齐。
4.根据权利要求1的芯片封装体，其中所述导电体环绕该芯片配置且呈环状排列，且该芯片与所述导电体相互分离。
5.根据权利要求1的芯片封装体，其中该遮蔽层通过该导电体与该积层基板的至少一接地孔而电性连接至该积层基板。
6.根据权利要求1的芯片封装体，其中该导电体是由一焊料所制成，且该导电体为一焊料块。
7.根据权利要求1的芯片封装体，其中该导电体为一印刷电路板的一部分。
8.根据权利要求1的芯片封装体，其中该导电体为一导线架的一部分。
9.一种芯片封装体的制作方法，包括：
提供一阵列基板，该阵列基板具有多个基板单元，其中每一该基板单元是由多条切割线所定义，且每一该基板单元上具有一芯片贴附区域；
形成多个导电体于每一该基板单元上，且所述导电体环绕该芯片贴附区域配置；
配置至少一芯片于每一该基板单元的该芯片贴附区域上，其中该芯片电性连接至该基板单元，且该芯片与所述导电体相互分离；
形成一封装胶体于该阵列基板上，以包覆该芯片、部分所述基板单元与所述导电体；
进行一标记制程以移除部分该封装胶体至暴露出每一该导电体的一上表面；
形成一遮蔽层于该封装胶体上，以覆盖该封装胶体与每一该导电体被暴露出的该上表面；以及，
进行一单体化制程，以形成多个芯片封装体。
10.根据权利要求9的芯片封装体的制作方法，其中所述导电体排列于该阵列基板的所述切割线上与每一该基板单元的多条边界线上。
11.根据权利要求9的芯片封装体的制作方法，其中所述导电体排列环绕每一该基板单元的多条边界线，且所述导电体与所述边界线相距一间隔距离。
12.根据权利要求9的芯片封装体的制作方法，其中所述导电体的材料包括一金属材料，且所述导电体的形成方式包括喷涂法、溅镀法或电镀法。
13.根据权利要求9的芯片封装体的制作方法，其中所述导电体的材料包括一焊料，且所述导电体的形成方式包括喷涂法或印刷法。
14.根据权利要求9的芯片封装体的制作方法，其中该标记制程包括一雷射挖空制程或一雷射钻孔制程。
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