CN101814484B - 芯片封装体及其制作方法 - Google Patents

芯片封装体及其制作方法 Download PDF

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CN101814484B
CN101814484B CN2009101713429A CN200910171342A CN101814484B CN 101814484 B CN101814484 B CN 101814484B CN 2009101713429 A CN2009101713429 A CN 2009101713429A CN 200910171342 A CN200910171342 A CN 200910171342A CN 101814484 B CN101814484 B CN 101814484B
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shielding layer
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ground hole
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殷荣孝
金德万
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Advanced Semiconductor Engineering Inc
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Abstract

本发明提供了一种芯片封装体及其制作方法，包括一积层基板、至少一芯片、一第一遮蔽层、一封装胶体以及一第二遮蔽层。积层基板上具有多个接点。芯片配置于积层基板上。第一遮蔽层配置于积层基板上，且暴露出接点与芯片。封装胶体至少覆盖芯片、接点、部份第一遮蔽层与部份积层基板。第二遮蔽层配置于封装胶体上且覆盖封装胶体。

Description

芯片封装体及其制作方法
技术领域
本发明涉及一种半导体装置，且特别是有关于一种芯片封装体及其制作方法。 
背景技术
对于大多数的电子装置或封装体而言，电磁干扰(electromagnetic interference，EMI)是一种共同但却不受欢迎的干扰，其中所谓的干扰也许是中断、阻碍、降低或限制电子装置或整体电路的效能表现。 
因此，在高频装置的封装体需求不断的提高的情况之下，更好的电磁干扰屏蔽效能也被提升。在现有技术中，通常是利用额外屏蔽板或接地板，来作为提升电子装置或封装体的电磁干扰屏蔽的效能，但此却会导致电子装置或封装体的厚度过厚且制程费用也较高。 
发明内容
本发明提供一种芯片封装体的制作方法，可简化制程。 
本发明提供一种具有提升电磁干扰屏蔽效能的芯片封装体。 
本发明提出一种芯片封装体，其包括一积层基板、至少一芯片、一第一遮蔽层、一封装胶体以及一第二遮蔽层。积层基板上具有多个接点与至少一接地孔。芯片配置于积层基板上。第一遮蔽层覆盖于积层基板的上表面与该接地孔，且具有多个第一开口和至少一第二开口，所述多个第一开口暴露出接点，该第二开口暴露出该芯片。封装胶体至少覆盖芯片、接点、部份第一遮蔽层与部份积层基板。第二遮蔽层配置于封装胶体上且覆盖封装胶体并电性连接至该接地孔。 
在本发明的一实施例中，上述的第一遮蔽层的材质与第二遮蔽层的材质都包括 焊料，且第一遮蔽层的材质与第二遮蔽层的材质可为相同材质，也可为不同材质。 
在本发明的一实施例中，上述的芯片用过多条焊线或多个凸块而电性连接至芯片封装体的基板。 
本发明提供一种芯片封装体的制作方法。首先，提供一基板。基板上具有多个接点、至少一接地孔与一芯片贴附区域。接着，形成一第一遮蔽层覆盖于基板的一上表面上与该接地孔，其中第一遮蔽层具有多个第一开口和至少一第二开口，所述多个第一开口暴露出接点，该第二开口暴露出该芯片贴附区域。配置至少一芯片于基板的芯片贴附区域上，其中芯片电性连接至基板。之后，形成一封装胶体于基板上，以包覆芯片、这些接点与至少一部份第一遮蔽层。最后，形成一第二遮蔽层于封装胶体上并电性连接至该接地孔。 
在本发明的一实施例中，上述的形成第一遮蔽层的方法包括网版印刷法(screen printing)，形成第二遮蔽层的方法包括网版印刷或电镀法(printing)。 
基于上述，第一遮蔽层配置于基板上的作用可视为芯片封装体底部防电磁辐射的电磁干扰屏蔽。在本发明的芯片封装体不需要额外金属板，只需通过第一遮蔽层与第二遮蔽层即可达到完整的电磁干扰屏蔽的效果。因此，第一遮蔽层与第二遮蔽层可提高芯片封装体的电磁干扰屏蔽效果，使芯片封装体具有较佳的电磁干扰屏蔽效能。 
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合 
附图说明
附图作详细说明如下。 
图1为本发明的一实施例的一种芯片封装体的剖面示意图； 
图2A至图2E为本发明的一实施例的一种芯片封装体的制作方法； 
图3为本发明的另一实施例的一种芯片封装体的剖面示意图。 
附图中主要元件符号说明： 
100、300-芯片封装体；102、302-基板； 
102a-上表面；        104、304-芯片； 
105、305-接地孔；           106、306-接点； 
108-芯片座；                110、310-第一遮蔽层； 
112-第一开口；              114-第二开口； 
120-焊线；                  130、330-封装胶体； 
140、340-第二遮蔽层；       320-凸块。 
具体实施方式
图1为本发明的一实施例的一种芯片封装体的剖面示意图。请参考图1，在本实施例中，芯片封装体100包括一基板102、至少一芯片104、多个接点106、一第一遮蔽层110、多条焊线120、一封装胶体130以及一第二遮蔽层140。基板102可为一积层基板，例如是一两层积层的印刷电路板基板。芯片104可为一半导体芯片，例如是一射频(Radio-Frequency，RF)芯片。接点106的材质可以是铜、铝或铜铝合金。第一遮蔽层110与第二遮蔽层140的材质都可以包括一焊料(solder material)，且第一遮蔽层110与第二遮蔽层140的材质可以相同也可以不同。接点106配置于基板102的上表面且环绕芯片座108。第一遮蔽层110配置于基板102的上表面，且暴露出接点106与芯片座108。芯片104配置于芯片座108上，且通过焊线120电性连接至基板102的接点106。封装胶体130包覆芯片104、接点106、焊线120、部份基板102与部份第一遮蔽层110。此外，第二遮蔽层140配置于封装胶体130上，且覆盖封装胶体130的四个侧壁与上表面。另外，第二遮蔽层140覆盖基板102的一接地孔105，且第二遮蔽层140电性连接至接地孔105而接地。在此必须注意的是，如果封装胶体130完全地覆盖芯片104与基板102，则第一遮蔽层110覆盖接地孔105而接地。 
在本实施例的芯片封装体100中，第一遮蔽层110配置于基板102上的作用可视为一电磁干扰屏蔽(EMI shield)，特别是保护芯片封装体100免于底部辐射源的电磁干扰辐射。因此，相比较于现有的芯片封装体而言，本实 施例的芯片封装体100不需要包含一额外金属板，且可以提供一厚度较薄的封装体。 
第一遮蔽层110与第二遮蔽层140可提升芯片封装体100电磁干扰屏蔽的效能。特别是，第一遮蔽层110覆盖基板102的上表面，可帮助芯片封装体100的底部免于电磁干扰辐射。第二遮蔽层140覆盖芯片封装体100的上部份(即封装胶体130的暴露表面)且第一遮蔽层110保护芯片封装体100的底部免受电磁干扰辐射，可有效加强芯片封装体100的电磁干扰屏蔽效能。 
在本实施例中，封装胶体130的边缘可与接点106的边缘或接地孔105的边缘对齐。此外，本实施例的芯片封装体100还包括多个位于基板102的背表面的凸块(未示出)，其可作为与外界电性连接的接点。理论上，芯片封装体100可以是一堆叠式的上封装或封装结构的封装体或一部份系统级封装(system-in-package)结构。另外，在本实施例中，除了有源器件之外，芯片封装体100还包括无源器件，例如是电阻、电容与电感。 
图2A至图2E为本发明的一实施例的一种芯片封装体的制作方法。在此必须说明的是，为了方便说明起见，图2A至图2B示出上视图，而2C至图2E示出剖面示意图。请先参考图2A，依照本实施例的芯片封装体的制作方法，首先，提供一基板102，其中基板102上具有至少一芯片座108与多个接点106。这些接点106环绕芯片座108配置。 
接着，请参考图2B，形成一第一遮蔽层110于基板102的一上表面102a上。第一遮蔽层110的材质可以是一焊料。形成第一遮蔽层110的方法可以是网版印刷法。第一遮蔽层110的多个第一开口112暴露出底部相对应的接点106，同时第一遮蔽层110的一第二开口114暴露出芯片座108。一般来说，开口的尺寸大于其所对应暴露出的元件，可以防止发生短路的可能性。换言之，第一遮蔽层110应该完全地隔开接点106以防止发生短路。此外，在其他实施例中，第二开口114的尺寸可能大约等于芯片座108的尺寸。 
请参考图2C，至少一芯片104配置于基板102的芯片座108上。接着， 形成多条焊线120于基板102与芯片104之间，使芯片104通过焊线120电性连接至基板102的接点106。 
请参考图2D，通过一封装胶体130而完成一封胶制程，其中封装胶体130配置于基板102上且包覆芯片104、接点106与至少一部份的第一遮蔽层110。 
请参考图2E，形成一第二遮蔽层140于封装胶体130的暴露表面上。第二遮蔽层140的材质可以是一焊料。形成第二遮蔽层140的方法可以是网版印刷或电镀法。在形成封装胶体130之后与形成第二遮蔽层140之前，可任意地进行一半切割制程(a half cutting process)。 
最后，进行一单体化制程(singulation process)以形成多个独立的芯片封装体100。 
在本实施例中，芯片封装体100的芯片104是通过打线接合技术而电性连接至基板102上的。当然，在其他实施例中，芯片封装体100也可包括一芯片104通过倒装接合技术而电性连接至基板102上。请参考图3，图3的芯片封装体300与图2E的芯片封装体100相似，其不同之处在于：芯片封装体300包括一芯片304，且此芯片304通过多个位于芯片304与接点306之间的凸块320，而电性连接至基板302的接点306。第一遮蔽层310配置于基板302的上表面且暴露出倒装区域(flip-chip area)。也就是说，第一遮蔽层310完全隔离倒装区域的周围，以防止第一遮蔽层310与接点306或凸块320发生短路。 
封装胶体330包覆芯片304、接点306、凸块320、部份基板302与第一遮蔽层310。此外，第二遮蔽层340配置于封装胶体330上，且覆盖封装胶体330的四个侧表面与上表面。另外，第二遮蔽层340覆盖基板302的多个接地孔305，且第二遮蔽层340电性连接至接地孔305而接地。在此必须注意的是，如果封装胶体330完全包覆芯片304与基板302，则第一遮蔽层310会覆盖接地孔305而接地。 
综上所述，由于第一遮蔽层与第二遮蔽层可有效地遮蔽外界电磁干扰辐射，因此可提高本发明的芯片封装体的电磁干扰屏蔽的效能。本发明的芯片封装体的制作方法，是改用一没有额外接底板的薄化基层基板，使芯片封装体的厚度与体积可以更为小型化。因此，这样的设计适合具有高频装置的封装，特别是一射频装置。 
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。 

Claims (11)

1.一种芯片封装体，包括：
一积层基板，该积层基板上具有多个接点与至少一接地孔；
至少一芯片，配置于该积层基板上；
一第一遮蔽层，覆盖于该积层基板的上表面与该接地孔，且具有多个第一开口和至少一第二开口，所述多个第一开口暴露出所述多个接点，该第二开口暴露出该芯片；
一封装胶体，至少包覆该芯片、所述多个接点、部份该第一遮蔽层与部份该积层基板；以及
一第二遮蔽层，配置于该封装胶体上且覆盖该封装胶体并电性连接至该接地孔。
2.根据权利要求1所述的芯片封装体，其中所述多个第一开口的尺寸大于其所对应暴露出的所述多个接点的尺寸。
3.根据权利要求1所述的芯片封装体，其中该芯片配置于该积层基板的一芯片座上，且该芯片通过多条焊线电性连接至所述多个接点。
4.根据权利要求1所述的芯片封装体，其中该芯片通过多个配置于该芯片下方的凸块而电性连接至所述多个接点。
5.根据权利要求3所述的芯片封装体，其中该第二开口的尺寸不小于该芯片座的尺寸。
6.根据权利要求4所述的芯片封装体，其中该第二开口的尺寸大于一排列所述多个凸块区域的尺寸。
7.根据权利要求1所述的芯片封装体，其中该第二遮蔽层电性连接至该积层基板的至少一接地孔。
8.一种芯片封装体的制作方法，包括：
提供一基板，该基板上具有多个接点、至少一接地孔与一芯片贴附区域；
形成一第一遮蔽层覆盖于该基板的一上表面上与该接地孔，其中该第一遮蔽层具有多个第一开口和至少一第二开口，所述多个第一开口暴露出该接点，该第二开口暴露出该芯片贴附区域；
配置至少一芯片于该基板的该芯片贴附区域上，其中该芯片电性连接至该基板；
形成一封装胶体于该基板上，以包覆该芯片、所述多个接点与至少一部份该第一遮蔽层；以及
形成一第二遮蔽层于该封装胶体上并电性连接至该接地孔。
9.根据权利要求8所述的芯片封装体的制作方法，其中形成该第一遮蔽层的方法包括网版印刷法。
10.根据权利要求8所述的芯片封装体的制作方法，其中形成该第二遮蔽层的方法包括网版印刷或电镀法。
11.根据权利要求8所述的芯片封装体的制作方法，其中形成该第二遮蔽层以覆盖该封装胶体的一暴露表面与该基板上的至少一接地孔。
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