CN115274623A - 具有电磁干扰屏蔽的半导体封装 - Google Patents

具有电磁干扰屏蔽的半导体封装 Download PDF

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CN115274623A
CN115274623A CN202210453659.7A CN202210453659A CN115274623A CN 115274623 A CN115274623 A CN 115274623A CN 202210453659 A CN202210453659 A CN 202210453659A CN 115274623 A CN115274623 A CN 115274623A
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metal
layer
semiconductor package
die
dielectric layer
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陈洁
唐逸麒
R·M·穆鲁甘
万亮
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本申请案的实施例涉及一种具有电磁干扰屏蔽的半导体封装。半导体封装包含多层封装衬底，所述多层封装衬底包含：第一层，其包含第一介电层及第一金属层，所述第一金属层包含第一金属迹线；及第二层，其包含第二介电层。集成电路IC裸片包含接合焊盘，其中所述IC裸片的底侧附接到所述第一金属迹线。金属导柱通过所述第二介电层连接到所述第一金属迹线。所述第二层上的第三层包含：所述第二层上的第三介电层，其延伸到所述半导体封装的底侧；及第二金属层，其包含第二金属迹线，所述第二金属迹线包含连接到所述接合焊盘的内部第二金属迹线及所述金属导柱上方的外部第二金属迹线；及经填充通孔，其设置在可接达接触焊盘外部，所述可接达接触焊盘将所述第二金属迹线连接到所述半导体封装的底侧。

Description

具有电磁干扰屏蔽的半导体封装
技术领域
本公开涉及用于半导体封装的电磁屏蔽，所述半导体封装包含至少一个集成电路(IC)。
背景技术
电子设计者在设计包括作为精密和/或敏感IC的至少一个IC或包含精密和/或敏感组件的半导体封装时所面临的挑战在于来自相邻电子组件的电磁干扰(EMI)。精密和/或敏感组件可包括功率金属氧化物半导体场效应晶体管(功率MOSFET)、控制器/驱动器、及模数转换器(ADC)、数字电路系统、控制及补偿电路系统、数模转换器(DAC)，或保护及诊断电路系统。引起EMI的相邻电子组件可包括IC或例如电感器的离散装置。因为大多数电子组件在其操作期间会发射至少一些EMI，所以使精密和/或敏感IC接近EMI发射电子组件可能会导致精密或敏感IC的性能受损。
发明内容
提供本发明内容是为了以简化形式介绍所公开概念的简要选择，所述概念将在以下具体实施方式中进一步描述，所述具体实施方式包含提供的图式。此发明内容不意欲限制所要求主题的范围。
所公开的方面认识到，精密和/或敏感IC的性能可能会受到EMI影响，所述EMI通常由任一有源电路引起，并且还会由位于IC附近的例如电感器的一些无源装置引起。对EMI敏感的IC的一个特定实例包括音频功率放大器IC，其中音频质量，例如频率响应、增益、噪音及失真在存在EMI的情况下会降级。在存在EMI的情况下可能会经受降级的精密的精密IC的实例包含ADC和DAC。此类精密和/或敏感IC，例如在汽车应用的状况下，将通常连同可能发射EMI的其它装置经组装在同一印刷电路板(PCB)上。
举例来说，当敏感IC裸片经封装于包含鸥翼引线的传统电源板封装(PWP)中时，由于PWP设计灵活性有限，因此难以屏蔽从相邻EMI发射装置发射的EMI到达敏感电路系统。即使PWP封装实现了一些EMI屏蔽，但具有到IC的接合焊盘的接合线的鸥翼引线的相对较高电感可显著增加振铃，且因此降低由PWP封装提供的EMI屏蔽效应。
所公开的方面利用有时被称为可路由引线框架(RLF)的多级封装衬底来提供EMI经屏蔽半导体封装，使得可以将精密或对EMI敏感的IC完全嵌入封装衬底中，包含通过金属层屏蔽EMI，所述金属层通常将在其应用中接地(例如，接地到公共PCB上的接地端子)。相较于具有接合线的常规的半导体封装，所公开的封装衬底还提供缩减的寄生效应，包含由于不存在任何接合线而缩减的电感。
在具有精密或敏感IC裸片的在本文中被称作EMI经屏蔽半导体封装的经公开封装衬底附接到PCB的焊盘的典型应用中，EMI屏蔽件包括：顶部EMI屏蔽件，其包括第一层金属；及底部EMI屏蔽件，其包括另一金属层。顶部和底部EMI屏蔽件通过金属导柱连接在一起，所述金属导柱放置在精密或敏感IC裸片的区域之外。相应的EMI屏蔽件连同放置在IC的区域之外的金属导柱可限定在IC的区域之外的在本文中被称作围绕IC的环的区域，其中EMI屏蔽件连同金属导柱共同地相似于IC裸片的法拉第笼。
顶部EMI屏蔽件通常具有大于IC裸片的面积的面积，且对准成在IC之整个区域上方。金属导柱，例如包括铜，被认为提供了从封装衬底的顶部金属层到底部EMI屏蔽件的低电阻竖直连接，这可以由其上安装有封装衬底的PCB提供。替代地，或除了由PCB提供的底部EMI屏蔽件之外，封装衬底的内部金属迹线可覆盖IC裸片的区域的至少50％，以本身提供底部EMI屏蔽件。
所公开的方面包含一种半导体封装，其包括多层封装衬底，所述多层封装衬底包含：第一层，其包含第一介电层和至少包含第一金属迹线的第一金属层；及第二层，其包含第二介电层。IC裸片包含半导体表面，所述半导体表面包含电路系统，其中所述电路系统的节点连接到接合焊盘。金属导柱通过第二介电层连接到第一金属迹线。第二层上的第三层包含：第三介电层，其延伸到半导体封装的底侧；第二金属层，其包含多个第二金属迹线，所述多个第二金属迹线包括连接到接合焊盘的内部第二金属迹线和金属导柱上方的外部第二金属迹线；以及穿过第三介电层的经填充通孔，其设置在可接达接触焊盘外部，所述可接达接触焊盘将第二金属迹线连接到半导体封装的底侧。
附图说明
现在将参考附图，附图未必是按比例绘制，其中：
图1A到G是根据一实例方面的工艺内的EMI经屏蔽半导体封装的连续横截面视图，所述工艺内的EMI经屏蔽半导体封装包括嵌入于多层封装衬底内的精密或敏感IC，所述连续横截面视图对应于用于形成EMI经屏蔽半导体封装的实例方法中的步骤之后的结果。图1A展示在于包括嵌入于第一介电层中的第一金属迹线的载体上形成第一层之后的工艺内结果。图1B展示在使用第一迹线上方的裸片附接材料来附接IC裸片之后的工艺内结果，所述IC裸片包含电路系统，所述电路系统连接到接合焊盘，且其顶侧向上。图1C展示在横向于IC裸片的第一金属迹线上形成金属导柱之后的工艺内结果。图1D展示在形成第二介电层之后且接着通常为暴露金属导柱的顶部表面的研磨工艺的工艺内结果。图1E展示在通常为穿过接合焊盘上方的第二介电层以到达接合焊盘的钻孔工艺之后的工艺内结果。
图1F展示在于第二层上形成第三层以及形成经填充通孔之后的工艺内结果，所述第三层包含：第三介电层，其延伸到半导体封装的底侧；及第二金属层，其包含多个第二金属迹线，所述多个第二金属迹线包括IC裸片的区域上方的内部第二金属迹线，和放置在IC裸片的区域之外的外部第二金属迹线。经填充通孔设置在可接达接触焊盘外部，所述可接达接触焊盘将第二金属迹线连接到半导体封装的底侧。图1G展示在去除载体且使半导体封装翻转之后且接着通常为锯切工艺的工艺内结果，所述锯切工艺在EMI经屏蔽半导体封装的面板的典型状况下进行以提供多个经单一化的EMI经屏蔽封装。
图2为根据一实例方面的对应于图1C中所展示的结构的俯视图，其如上文所描述展示在于横向于IC裸片的第一迹线上形成金属导柱之后的工艺内结果。
图3A及图3B分别展示根据一实例方面的半导体封装组合件的顶部透视图和横截面视图，所述半导体封装组合件包括经公开EMI经屏蔽半导体封装，所述EMI经屏蔽半导体封装包括嵌入于封装衬底内的IC，所述封装衬底安装在PCB的顶部上的焊盘上，所述封装衬底向IC提供底部金属屏蔽件。在图3B中，还展示PCB，其中其介电质使经嵌入的经填充通孔连接到金属焊盘。
具体实施方式
参看图式描述实例方面，其中相同的参考标号用于指代类似或等效的元件。图解说明的动作或事件的排序不应被视为限制性的，因为一些动作或事件可能用不同的次序出现和/或与其它动作或事件并行地出现。此外，实施根据本公开的方法可能不需要一些图解说明的动作或事件。
并且，如本文中所使用的术语“连接到”或“与……连接”(等等)在未进一步定义的情况下，描述间接或直接电连接。因此，如果第一装置“连接”到第二装置，那么连接可通过其中在路径中仅存在寄生效应的直接电连接，或通过经由包含其它装置和连接的中间项的间接电连接。对于间接连接，中间项一般不会修改信号的信息，但是可能会调整其电流电平、电压电平和/或功率电平。
现将定义本文中所使用的若干术语。如本文中所使用的多层封装衬底为特定封装衬底布置，其包括多个(至少两个)经堆叠层，其中每一层经预配置有例如镀铜层的金属镀层，或互连以在封装中提供电气连接。此封装衬底通常通过在引线框架衬底周围形成例如模制化合物(通常包括环氧树脂材料)或其它介电有机化合物的介电层来构建，所述引线框架衬底包括经图案化顶部金属层与经图案化金属底部层之间的金属材料。此封装衬底可包括横向堆叠及竖直堆叠的单裸片或多裸片配置，从而实现低剖面且细间距的封装，这启用了当应用于所公开的方面时具有公认的益处的不同堆叠、材料和制造过程。
如本文中所使用的IC裸片包括至少具有半导体表面的衬底(通常为全半导体衬底，例如包括其上具有任选的外延层的硅)，其中存在形成于半导体表面中的电路元件(包含晶体管，且通常为二极管、电阻器、电容器等)，所述电路元件在一起经配置以用于通常实现至少一个电路功能。所述电路系统的各种节点连接到IC的顶侧上的接合焊盘，其中所述接合焊盘通常包括IC的顶部层金属。IC可包括功率装置，例如放大器或功率调节器。
图1A到G是工艺内的EMI经屏蔽半导体封装的连续横截面视图，所述工艺内的EMI经屏蔽半导体封装包括嵌入于多层封装衬底内的精密或敏感IC，所述连续横截面视图对应于用于形成EMI经屏蔽半导体封装的实例方法中的步骤之后的结果。图1A展示在于载体105(例如金属载体)上形成第一层115之后的工艺内结果，所述第一层包括经展示第一金属层，所述第一金属层包含第一金属迹线115a，所述第一金属迹线嵌入于第一介电层115b中，所述第一介电层可包括模制化合物。所述方法结束后的第一金属迹线115a将为下面的IC提供顶部EMI屏蔽件。尽管第一金属迹线115a经展示为覆盖IC裸片120的整个区域的连续结构，但第一金属迹线115a也可以是包含间隙的经图案化结构，使得其不覆盖IC裸片的区域中的全部。
图1B展示在使用用以附接IC裸片120的底侧的裸片附接材料124来附接IC裸片120之后的工艺内结果，所述IC裸片包含电路系统180，所述电路系统连接到接合焊盘121，且其顶侧向上。裸片附接材料124可包括介电材料或可包括导电及导热材料，例如具有银颗粒或焊料的环氧树脂。
举例来说，在介电裸片附接材料的状况下，裸片附接材料124可包括第一金属迹线115a上的裸片附接膜(DAF)。IC裸片的电路系统180包括电路元件(包含晶体管，且通常为二极管、电阻器、电容器等)，所述电路元件可形成于块状衬底材料上的外延层中，其中电路系统180在一起经配置以用于通常实现至少一个电路功能。实例电路功能包含模拟(例如，放大器或功率转换器)、射频(RF)、数字或非易失性存储器功能。
图1C展示在于横向于IC裸片120放置的第一金属迹线115a上形成金属导柱132之后的工艺内结果。金属导柱132通常包括铜，且具有在IC裸片120的顶侧表面上方延伸的高度。电镀工艺可用于形成金属导柱132。金属导柱132可在一个布置中具有矩形棱柱形状，其经定义为具有全部为矩形的六个面的3维实心形状。另外，金属导柱132通常可具有多种其它形状，例如圆柱形，其中金属导柱132的形状通常可取决于给定应用来设计。
尽管通常形成多个间隔开的金属导柱132，例如如下文在图1C及图2中所描绘，但也可代替形成多个间隔开的金属导柱132，可围绕IC裸片120形成连续(单一)的金属环。在间隔开的金属导柱132的状况下，标称间距可为0.5mm±20％。再次，在间隔开的金属导柱132的状况下，金属导柱132可共同地覆盖围绕IC裸片120的区域的10％到40％。关于邻近的金属导柱132之间的间隙，通常，所述间隙的最小值为0.1mm，且其最大值可取决于IC裸片大小。金属导柱132的面积可以是0.05mm2及2mm2。
图1D展示在例如使用模制工艺以形成模制化合物来形成第二介电层116b且接着进行研磨以暴露金属导柱132的顶部表面之后的工艺内结果。图1E展示在例如使用激光钻孔来形成穿过第二介电层116b的通孔116c之后的工艺内结果，其中通孔116c定位于接合焊盘121上方。通孔116c到达接合焊盘121的顶部表面，以使得能够接触如下文所描述的接合焊盘121。
图1F展示在于第二层上形成第三层117之后的工艺内结果，所述第三层包含：第二金属层117a，其包含多个第二金属迹线，所述多个第二金属迹线包括各自连接到金属导柱132的外部金属迹线117a1，及包含竖直区段的内部金属迹线117a2，所述竖直区段填充图1E中所展示的通孔116c以形成连接到接合焊盘121的经填充通孔117v。第三层117还包含：第三介电层117b，其例如包括模具层；及经填充通孔117c，所述经填充通孔设置在可接达接触焊盘外部，所述可接达接触焊盘将第二金属迹线连接到在图1F的顶部处展示的半导体封装的底侧，所述半导体封装具有嵌入于其中的第二经填充通孔117c，其接触内部金属迹线117a2及外部金属迹线117a1。
尽管未展示，但所述方法可进一步包括在第三层117上形成第四层。在一个布置中，第四层基本上与第三层相同，且第四层的金属迹线对准到内部金属迹线117a2中的外部金属迹线117a1。形成此第四层的优点可以是更好的热性能及PCB级可靠性，其中第四层用于连接到PCB。
图1G展示在去除载体105且使工艺内封装衬底翻转并且接着进行单一化之后的工艺内结果，所述单一化通常包括锯切工艺，所述锯切工艺在EMI经屏蔽半导体封装的面板的典型状况下进行，以提供经展示为EMI经屏蔽半导体封装190的多个经单一化EMI经屏蔽半导体封装。在去除载体105之后，在单一化之前可存在表面光洁度处理。EMI经屏蔽半导体封装190的总厚度可以是350μm到600μm，例如约450μm。金属导柱132可具有在EMI经屏蔽半导体封装190的总厚度的50％与90％之间的高度。
图2为根据一实例方面的对应于图1C中所展示的结构的俯视图200，其如上文所描述展示在于横向于IC裸片120的第一金属迹线115a上形成金属导柱132之后的工艺内结果。可看出相邻金属导柱132之间存在间隙133。尽管展示为具有矩形横截面，但如上文所描述的金属导柱132也可具有其它形状，包含圆形横截面或其它椭圆形横截面。
图3A及图3B分别展示半导体封装组合件300的顶部透视图和横截面视图，所述半导体封装组合件包括公开的EMI经屏蔽半导体封装，其包括IC裸片120(例如上文所描述的图1G中所展示的EMI经屏蔽半导体封装190)，所述IC裸片嵌入于封装衬底内，所述封装衬底安装在PCB 320的顶部表面上的焊盘321上，所述封装衬底为IC裸片120提供底部金属屏蔽件371，其经展示为覆盖IC裸片120的整个区域。IC 120上方存在经展示为315a的顶部金属EMI屏蔽件，其对应于上文所描述的第一金属迹线115a。PCB320上之金属迹线经展示为322。在图3B中，还展示PCB 320，其中其介电层326使经嵌入的经填充通孔327连接到金属焊盘328。
实例
所公开的方面通过以下特定实例进一步说明，所述特定实例不应理解为以任何方式限制本发明的范围或内容。
运行EMI模拟，以比较常规的经熔融薄缩小外形封装(TSSOP)与所公开的EMI经屏蔽装置的结果。TSSOP为具有鸥翼引线的矩形表面安装塑料IC封装。电场数据证实，相较于常规的经熔融TSSOP，包含EMI屏蔽件的经公开封装衬底将在IC裸片的顶部表面上接收的电场缩减到三分之一(从30V/m到10V/m)。
所公开的方面可集成到多种组装流程中，以形成多种不同半导体封装和相关产品。半导体封装可包括单个IC裸片或多个IC裸片，例如包括多个经堆叠IC裸片或横向放置的IC裸片的配置。可使用多种封装衬底。IC裸片可包含其中的各个元件和/或其上的层，包含障壁层、介电层、装置结构、有源元件及无源元件，其包含源极区、漏极区、位线、基极、发射极、集电极、导线、导电通孔等。此外，IC裸片可由多种工艺形成，包含双极、绝缘栅双极晶体管(IGBT)、CMOS、BiCMOS和MEMS。
本发明涉及的领域的技术人员将了解，要求保护的发明的范围内可以有所公开的方面的许多变化，并且在不脱离本公开的范围的情况下可以对上文所描述的方面进行进一步的添加、删除、替代和修改。

Claims (21)

1.一种半导体封装，其包括：
多层封装衬底，其包括：第一层，其包含第一介电层及至少包含第一金属迹线的第一金属层；及第二层，其包含第二介电层；
集成电路IC裸片，其包括具有半导体表面的衬底，所述半导体表面包含电路系统，其中所述电路系统的节点连接到接合焊盘，所述IC的底侧通过裸片附接材料附接到所述第一金属迹线；
金属导柱，其通过所述第二介电层连接到所述第一金属迹线；
所述第二层上的第三层，其包含：第三介电层，其延伸到所述半导体封装的底侧；及第二金属层，其包含多个第二金属迹线，所述多个第二金属迹线包括连接到所述接合焊盘的内部第二金属迹线和所述金属导柱上方的外部第二金属迹线；以及经填充通孔，其设置在可接达接触焊盘外部，所述可接达接触焊盘将所述第二金属迹线连接到所述半导体封装的底侧。
2.根据权利要求1所述的半导体封装，其中所述第一金属迹线覆盖所述IC裸片的区域中的全部。
3.根据权利要求1所述的半导体封装，其中所述第一金属迹线是包含间隙的经图案化结构，使得其不覆盖所述IC裸片的区域中的全部。
4.根据权利要求1所述的半导体封装，其中所述内部第二金属迹线共同地覆盖所述IC裸片的所述区域的至少50％。
5.根据权利要求1所述的半导体封装，其中所述IC裸片包括功率金属氧化物半导体场效应晶体管MOSFET、具有栅极驱动器的控制器、模数转换器ADC、数字电路系统、控制及补偿电路系统，或数模转换器DAC。
6.根据权利要求1所述的半导体封装，其中所述IC裸片包括音频放大器。
7.根据权利要求1所述的半导体封装，其中所述金属导柱具有为所述半导体封装的厚度的50％到90％的高度。
8.根据权利要求1所述的半导体封装，其中所述导柱的面积是在0.05mm2与2mm2之间。
9.根据权利要求1所述的半导体封装，其中所述金属导柱包括所述金属导柱中的多个间隔开的金属导柱。
10.一种半导体封装组合件，其包括：
半导体封装，其包括：
多层封装衬底，其包括：第一层，其包含第一介电层及至少包含第一金属迹线的第一金属层；及第二层，其包含第二介电层；
集成电路IC裸片，其包括具有半导体表面的衬底，所述半导体表面包含电路系统，其中所述电路系统的节点连接到接合焊盘，所述IC裸片的底侧通过裸片附接材料附接到所述第一金属迹线；
金属导柱，其通过所述第二介电层连接到所述第一金属迹线；
所述第二层上的第三介电层，其包含：第三介电层，其延伸到所述半导体封装的底侧；及第二金属层，其包含多个第二金属迹线，所述多个第二金属迹线包括连接到所述接合焊盘的内部第二金属迹线和所述金属导柱上方的外部第二金属迹线；以及经填充通孔，其设置在可接达接触焊盘外部，所述可接达接触焊盘将所述第二金属迹线连接到所述半导体封装的底侧，及
印刷电路板PCB，其中所述半导体封装接合到所述PCB的顶部表面上，其中所述PCB的所述顶部表面向所述半导体封装组合件提供底部金属EMI屏蔽件。
11.根据权利要求10所述的半导体封装组合件，其中所述第一金属迹线覆盖所述IC裸片的整个区域。
12.根据权利要求10所述的半导体封装组合件，其中所述第一金属迹线是包含间隙的经图案化结构，使得其不覆盖所述IC裸片的区域中的全部。
13.根据权利要求10所述的半导体封装组合件，其中所述IC裸片包括功率金属氧化物半导体场效应晶体管MOSFET、具有栅极驱动器的控制器、模数转换器ADC、数字电路系统、控制及补偿电路系统、数模转换器DAC，或音频放大器。
14.根据权利要求10所述的半导体封装组合件，其中所述金属导柱包括所述金属导柱中的多个间隔开的金属导柱。
15.根据权利要求10所述的半导体封装组合件，其中所述内部第二金属迹线共同地覆盖所述IC裸片的区域的至少50％。
16.一种组装半导体封装的方法，其包括：
形成多层封装衬底，其包括：
形成第一层，所述第一层包含第一介电层和至少包含第一金属迹线的第一金属层；
附接集成电路IC裸片，所述IC裸片包括具有半导体表面的衬底，所述半导体表面包含电路系统，其中所述IC裸片的底侧通过裸片附接材料附接到所述第一金属迹线；
在所述第一金属迹线上形成在所述IC裸片的区域之外的金属导柱；
形成第二层，其包含：
形成厚度延伸到所述金属导柱的顶侧的第二介电层；
在所述第二介电层中形成到达所述接合焊盘的通孔；
在所述第二层上形成第三层，其包含：
形成延伸到所述半导体封装的底侧的第三介电层，
形成第二金属层，所述第二金属层包含多个第二金属迹线，所述多个第二金属迹线包括连接到所述接合焊盘的内部第二金属迹线和所述金属导柱上方的外部第二金属迹线，及
形成穿过所述第三介电层的经填充通孔，所述经填充通孔设置在可接达接触焊盘外部，所述可接达接触焊盘将所述第二金属迹线连接到所述半导体封装的底侧。
17.根据权利要求16所述的方法，其中所述第一金属迹线覆盖所述IC裸片的所述区域中的全部。
18.根据权利要求16所述的方法，其中所述金属导柱包括所述金属导柱中的多个间隔开的金属导柱。
19.根据权利要求16所述的方法，其中所述内部第二金属迹线共同地覆盖所述IC裸片的所述区域的至少50％。
20.根据权利要求16所述的方法，其中所述裸片附接材料包括导热材料，且其中所述IC裸片包括功率金属氧化物半导体场效应晶体管MOSFET、具有栅极驱动器的控制器、模数转换器ADC、数字电路系统、控制及补偿电路系统、数模转换器DAC，或音频放大器。
21.根据权利要求16所述的方法，其中所述导柱具有为所述半导体封装的厚度的50％到90％的高度。
CN202210453659.7A 2021-04-30 2022-04-27 具有电磁干扰屏蔽的半导体封装 Pending CN115274623A (zh)

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