TWI569398B - 半導體元件封裝及其製作方法 - Google Patents
半導體元件封裝及其製作方法 Download PDFInfo
- Publication number
- TWI569398B TWI569398B TW099116088A TW99116088A TWI569398B TW I569398 B TWI569398 B TW I569398B TW 099116088 A TW099116088 A TW 099116088A TW 99116088 A TW99116088 A TW 99116088A TW I569398 B TWI569398 B TW I569398B
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit substrate
- exposed
- substrate
- conductive layer
- slits
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 71
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 134
- 238000005520 cutting process Methods 0.000 claims description 35
- 239000008393 encapsulating agent Substances 0.000 claims description 30
- 230000002093 peripheral effect Effects 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 239000000565 sealant Substances 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910001220 stainless steel Inorganic materials 0.000 claims description 3
- 239000010935 stainless steel Substances 0.000 claims description 3
- 239000011135 tin Substances 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000000994 depressogenic effect Effects 0.000 claims 2
- 239000003566 sealing material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Description
本發明是有關於一種半導體元件封裝,且特別是有關於一種具有電磁干擾屏蔽(electromagnetic interference shielding)的半導體元件封裝。
半導體元件日益複雜,而至少部分的原因是源於使用者對於增加處理速度(processing speed)與縮小元件尺寸的需求。雖然增加處理速度與縮小元件尺寸的好處相當顯著,但是這些半導體元件的特性亦會產生問題。特別是,較高的時脈速度(clock speed)會使訊號準位(signal level)轉換的頻率增加,以致於頻率較高或波長較短的電磁發射(electromagnetic emission)強度增加。電磁發射可從一源半導體元件(source semiconductor device)輻射而出並入射鄰近的半導體元件。若是對鄰近的半導體元件的電磁發射強度夠高,則電磁發射會不利於(鄰近的)半導體元件的運作。此現象有時被稱為電磁干擾(electromagnetic interference,EMI)。尺寸較小的半導體元件會使電磁干擾的問題更加嚴重,因為這些(尺寸較小的)半導體元件會以較高的密度配置於一電子系統中,以致於鄰近的半導體元件接收到較強且不希望得到的電磁發射。
減少電磁干擾的一種方法是在半導體元件封裝中屏蔽一組半導體元件。特別是,可藉由在封裝體外部加裝接地的導電罩體(casing)或是導電殼體(housing)來達到屏蔽的效果。當由封裝體內部輻射出的電磁發射照射到罩體的內表面時,至少部分的電磁發射可被電性短路,以降低可穿透罩體且不利於鄰近的半導體元件的電磁發射強度。相同地,當由鄰近的半導體元件輻射出的電磁發射照射到罩體的外表面時,會發生相似的電性短路以降低封裝體中的半導體元件所受到的電磁干擾。
雖然導電罩體可減少電磁干擾,但是使用導電罩體會有許多缺點。特別是,罩體一般是藉由黏著劑而固定在半導體元件封裝的外部。不幸的是,由於黏著劑的接合性會受到溫度、濕度以及其他環境因素的影響而降低,因此,罩體容易剝離或脫落。而且,當將罩體固定至封裝體時,罩體的尺寸與形狀以及封裝體的尺寸與形狀需相互配合,且二者的配合度需在一較小的容忍範圍內。使尺寸與形狀能夠相互配合,以及使罩體與封裝體的相對位置具有一定的準確度會導致製作成本提高並耗費製程時間。由於需要使尺寸與形狀能相互配合,因此,不同尺寸與形狀的半導體元件封裝需要搭配不同的罩體,以容納不同的封裝體,而這會進一步地增加製作成本與時間。
克服前述背景中所提及的問題的半導體元件封裝及其製作方法如下所述。
本發明提供一種具有電磁干擾屏蔽的半導體元件封裝及其製作方法。
本發明提出一種半導體元件封裝包括一線路基板、一電子元件、一封裝膠體以及一導電層。線路基板包括一承載面、一底面、一側面、一導電層以及一接地環,其中側面延伸於承載面與底面之間,接地環為一實質上連續的圖案,且接地環沿著線路基板的邊緣延伸,接地環暴露於線路基板的側面,且導電層包括接地環。電子元件鄰近承載面,並電性連接線路基板的導電層。封裝膠體鄰近承載面,並包覆電子元件。導電層配置於封裝膠體與接地環上。
在本發明之一實施例中,承載面的一周邊部向下凹陷以形成一凹陷部,凹陷部沿著線路基板的邊緣延伸,且線路基板的側面包括凹陷部,接地環暴露於凹陷部中。
在本發明之一實施例中,線路基板為一多層線路基板,凹陷部向下凹陷至線路基板的一內層,且導電層位於內層上。
在本發明之一實施例中,凹陷部的一底部呈弧狀。接地環暴露於凹陷部之弧狀的底部。
在本發明之一實施例中,部分接地環係暴露於圍繞整個線路基板的邊緣延伸的側面。導電層實質上配置於接地環之暴露於側面的整個部分上。
本發明提出一種半導體元件封裝包括一線路基板、一電子元件、一封裝膠體以及一電磁干擾屏蔽。線路基板包括一第一表面、一第二相對面以及一第一接地環,第一接地環包括一第一外露連接面,第一外露連接面配置於線路基板的第一表面與第二相對面之間,且第一接地環在實質上平行於第一表面與第二相對面的一第一平面上繞著線路基板延伸至少50%。電子元件鄰近第一表面,並電性連接線路基板。封裝膠體鄰近第一表面,並包覆電子元件。電磁干擾屏蔽鄰近封裝膠體以及第一接地環之第一外露連接面。
在本發明之一實施例中,電磁干擾屏蔽包括一共形的覆蓋層,共形的覆蓋層實質上全面覆蓋第一接地環的第一外露連接面。第一接地環的第一外露連接面在第一平面上圍繞整個線路基板。
在本發明之一實施例中,電磁干擾屏蔽包括一共形的覆蓋層,共形的覆蓋層的材質包括鋁、銅、鉻、金、銀、鎳、錫以及不銹鋼至少其中之一。
在本發明之一實施例中,線路基板更包括一第二接地環,第二接地環包括一第二外露連接面,第二外露連接面位於線路基板的第一表面與第二相對面之間,第二接地環在實質上平行於第一平面的一第二平面上繞著線路基板延伸至少50%。電磁干擾屏蔽實質上全面覆蓋第二接地環的第二外露連接面。
在本發明之一實施例中,線路基板包括一側面,側面延伸於線路基板的第一表面與第二相對面之間,側面包括一凹陷部。第一接地環的第一外露連接面暴露於凹陷部。
在本發明之一實施例中,凹陷部呈弧狀。
本發明提出一種半導體元件封裝的製作方法如下所述。提供一基板,基板包括一承載面、一底面與一接地環。將一半導體元件電性連接至基板的承載面。提供一封膠材料至基板的承載面,以形成一覆蓋半導體元件的封膠結構。形成一第一組切割狹縫,第一組切割狹縫貫穿封膠結構並部分穿過基板,以(a)使封膠結構的一部分覆蓋半導體元件,(b)暴露出基板的一側面的一部分,以及(c)使接地環的一部分暴露於側面。形成一導電層,導電層鄰近覆蓋半導體元件的封膠結構的部分、第一組切割狹縫所暴露出的側面的部分、以及第一組切割狹縫所暴露出的接地環的部分。形成一第二組切割狹縫,第二組切割狹縫貫穿導電層以及基板,以(a)次分割導電層以形成一電磁干擾屏蔽,電磁干擾屏蔽係鄰近半導體元件、側面之暴露於第一組切割狹縫的部分以及接地環之暴露於第一組切割狹縫的部分,(b)次分割基板以形成一基板單元,基板單元包括一承載面,且半導體元件鄰近基板單元的承載面,以及(c)使基板單元包括接地環,其中接地環為一實質上連續的圖案,連續的圖案係沿著基板單元的邊緣延伸。
在本發明之一實施例中,第一組切割狹縫的至少其中之一的寬度為300微米至500微米。
在本發明之一實施例中,第二組切割狹縫的至少其中之一的寬度為250微米至350微米。
在本發明之一實施例中,第二組切割狹縫與第一組切割狹縫對齊,且第二組切割狹縫的至少其中之一的寬度小於第一組切割狹縫的至少其中之一的寬度。
在本發明之一實施例中,第一組切割狹縫的至少其中之一呈弧狀。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
下列的定義可應用在關於本發明之某些實施例的某些方面。在此將詳述這些定義。
在此所使用的單詞『一』與『該』可代表複數個,除非上下文明顯指出『一』與『該』代表單數個。因此,舉例來說,當提到一接地元件時,可包括多個接地元件的情況,除非上下文明顯指出『一』代表單數個。
在此所使用的詞『組』代表一或多個元件的群體。因此,舉例來說,一組膜層可包括單一膜層或多個膜層。一組的元件亦可代表該組的構件。一組的元件可以是彼此相同或彼此不同。在一些例子中,一組的元件可共有一或多個相同的特性。
在此所使用的詞『鄰近』代表接近或是鄰接。鄰近的元件可以是彼此分離或是彼此實質上接觸或直接接觸。在一些例子中,鄰近的元件可彼此相連或是彼此為一體成型。
在此所使用的詞例如『內』、『頂』、『底』、『上』、『下』、『向下』以及『橫向』代表一組元件的相對方向(方位),例如依照圖所示,但是毋須以特定的方向製作或是使用這些元件。
在此所使用的詞『連接』代表操作上的耦接(coupling)或是連接(linking)。連接元件可以是彼此直接耦接或是彼此間接耦接,例如透過另一組元件。
在此所使用的詞『實質上』、『基本上』代表一可以考慮的程度或範圍。當其與一事件或情況並用時,該詞可代表該事件或情況準確發生的例子以及該事件或情況發生在一近似值的例子,例如計算此處所描述的製程操作的一般容忍度。
在此所使用的詞『導電的』代表一種傳導電流的能力。導電材料一般是相當於表現出輕微或是無反抗電流流動的材料。導電率的單位為S‧m-1(Siemens per meter)。通常,導電材料是一導電率約大於104S‧m-1的材料,例如至少約105S‧m-1或是至少約106S‧m-1。材料的導電率有時會隨溫度而變。除非有特別說明,否則都是指室溫下的材料導電率。
本發明可用來製作多種封裝結構,例如堆疊式封裝(tacked type package)、多晶片封裝(multiple-chip package)或高頻率元件封裝(high frequency device package)。
圖1A~圖1F繪示本發明一實施例之半導體元件封裝的製程示意圖。
請參照圖1A,一線路基板條102具有多個線路基板110(或基板單元110),線路基板110是由多條後續的切割線190(圖1A中的虛線)所定義出來的,其中各線路基板110具有一承載面110a與一底面110b。線路基板條102可為一積層板(laminated substrate),例如是雙層積層板、四層積層板或是其他的多層積層板,本實施例是以四層積層板為例。各線路基板110亦具有一側面,該側面延伸於承載面110a與底面110b之間,如圖1D所示(下文中將會介紹)。各線路基板110具有四層導電層,該四層導電層包括一頂導電層112、一第一內導電層114、一第二內導電層116以及一底導電層118。導電層112、114、116、118皆為圖案化導電層且彼此電性連接。
圖2繪示圖1A~圖1F的線路基板條102的第一內導電層114的圖案的上視圖。關於各線路基板110,第一內導電層114具有一接地環114a。在一實施例中,接地環114a為一實質上連續的圖案,且該圖案沿著線路基板110的邊緣延伸。或者是,接地環是不連續的圖案。舉例來說,接地環可包括一條接地條或是多條不連續的接地條,各條或是全部的接地條在一實質上平行於承載面110a以及底面110b的第一平面上繞著線路基板110延伸至少約50%,例如至少約60%或是至少約70%,以及高達約100%。在線路基板條102中,相鄰的多個接地環114a可為一體成型,並為一沿著切割線190延伸的框體。此外,本發明的實施例並未限制接地環的位置或是數量。在其他實施例中,接地環可配置於頂導電層、內導電層與底導電層的任一層中。
請參照圖1B,電子元件120(或半導體元件120)配置於承載面110a上並透過多個導電凸塊106電性連接至線路基板110,其中導電凸塊106配置於電子元件120與線路基板110之間。在此,電子元件120可為晶片。各電子元件120較佳地是配置於對應的線路基板110的一中心部中。雖然在此是描述覆晶接合技術,但本發明還包括打線接合或是其他可行的接合技術。
請參照圖1C,進行一封膠製程(molding process),以於線路基板條102上形成一封裝膠體130(或一封膠結構130),封裝膠體130包覆晶片120、凸塊106與各線路基板110之至少部分。前述封裝製程例如為一覆蓋成型製程(over-molding process)。封裝膠體130的材質例如為環氧樹脂或矽膠。
請參照圖1D與圖3,其中圖3繪示圖1D的結構的透視圖,沿著各線路基板110的邊緣對封裝膠體130進行一半切切割製程(例如沿著切割線190),以移除部分的封裝膠體130與線路基板條102。特別是,半切切割製程是利用一切割工具(未繪示)進行切割,且切割深度D1大於封裝膠體130的厚度T1,以完全地切穿封裝膠體130並部分地切入各線路基板110的一周邊部117(或凹陷部117)。如此一來,可形成一開口170(或是一第一組切割狹縫170),以暴露各線路基板110的邊緣上的接地環114a的一側壁S2(或是一連接面S2),例如接地環114a暴露於各線路基板110之位於凹陷部117中的側面110c。在本實施例中,側面110c可包括線路基板110之位於凹陷部117中的實質上垂直與實質上水平的表面。線路基板110的側面可包括位於凹陷部117中的側面110c,以及沿著切割線190延伸所定義出的線路基板110的側面。
請參照圖1E,在半切切割製程之後,形成一導電層140,以共形地覆蓋封裝膠體130以及線路基板條102。導電層140可作為電磁干擾屏蔽,其直接配置於封裝膠體130與線路基板110上,而毋須使用外加的金屬殼體,故可降低製作成本與時間。特別是,導電層140係共形地覆蓋封裝膠體130的頂面130a、封裝膠體130的側壁130b、各開口170的側壁170a以及各開口170的底面170b。導電層140可與開口170所暴露出的各接地環114a的側壁S2接觸。導電層140的形成方式例如為噴塗印刷(spray coating)、電鍍(或無電鍍)或濺鍍(sputtering method)。金屬材料例如為鋁、銅、鉻、金、銀、鎳、錫、不銹鋼、焊料及前述之組合。導電層140的較佳厚度是介於1微米與20微米之間。
在另一實施例中,電磁干擾屏蔽為一預形成殼體(pre-formed casing),且預形成殼體鄰近封裝膠體130以及線路基板條102。
請參照圖1F,進行一切單製程(singulation process),其係沿各線路基板110的邊緣(例如後續的切割線190,或是一第二組切割狹縫190,如圖1F中的虛線所示)全切割(full-cutting)周邊部117,以使多個線路基板110彼此分離,從而得到多個獨立的封裝結構100。全切割製程(full-cutting process)例如是刀具切割製程(blade sawing process)或是雷射切割製程。
由於在線路基板條102上進行的半切切割製程可使接地環114a暴露於各線路基板110的側面110c,因此,之後形成的導電層140可藉由接觸接地環114a的側壁S2而接地。由於接地環114a沿著線路基板110的邊緣延伸,因此,在線路基板110的四個邊皆可建立接地的連結,以增加與導電層140的接觸面積。因此,可提昇封裝結構的可靠度以及電磁干擾屏蔽的效果,並且可擴大切割製程的容錯視窗(sawing tolerance window)。
一般而言,前述的半切切割製程或是前述的全切割製程的切割道(cutting path)的寬度或深度可依遮蔽需求、封裝體的其他電子特性、或是製程參數而作改變。較佳的是,請參照圖1F,半切切割製程的切割道的寬度W1是介於300微米與500微米之間,全切割製程的切割道的寬度W2是介於250微米與350微米之間。
在本發明的某些實施例中,半切切割製程的切割深度可依據接地環的排列而作改變,故可改變線路基板的周邊部的深度。圖4繪示本發明一實施例之四層線路基板的各導電層的圖案。如圖4所示,頂導電層112具有一接地環112a,第一內導電層114具有一接地環114a,第二內導電層116具有一接地環116a,以及底導電層118具有一接地環118a。在線路基板的任一導電層中,接地環可任意排列,且本發明包括前述排列之組合。以下將介紹本發明之多種不同的封裝結構的實施例。
在圖1A~圖1F的製程步驟之後,如圖5所示,可獲得半導體元件封裝500。半導體元件封裝500包括線路基板110、電子元件120、封裝膠體130以及導電層140。電子元件120配置於承載面110a上,並電性連接線路基板110。封裝膠體130配置於承載面110a上,並包覆配置於承載面110a上的電子元件120。一凹陷部117(例如周邊部)沿著線路基板110的邊緣延伸並向下延伸至一第二介電層184,且形成凹陷部117的方法包括進行一半切切割製程以使第一內導電層114的接地環114a暴露於線路基板110的側面110c。導電層140形成在封裝膠體130上以及接地環114a的側壁S2上,其中側壁S2係暴露於線路基板110的側面110c。在本實施例中,線路基板110之位於第一內導電層114之上的頂導電層112可不具有接地環,而在第一內導電層114之下的第二內導電層116或底導電層118可具有(或不具有)接地環116a或118a(如圖4所示)。雖然凹陷部117並未向下凹陷至第二內導電層116或底導電層118,接地環116a、118a仍可經由線路基板110中的接地通道而電性連接接地環114a以及導電層140。
以下敘述皆包含在本發明的範圍內,前述的凹陷部可向下凹陷至線路基板的任一內層,以暴露位於內層上的導電層所具有的接地環。前述內層可為一介電層或是另一導電層。
圖6繪示本發明另一實施例之半導體元件封裝結構的剖面圖。請參照圖6,封裝結構600相似於圖5的封裝結構500,兩者的差異之處在於頂導電層112具有如圖4所示的一接地環112a,且凹陷部117向下凹陷至線路基板110的一第一介電層182。導電層140配置於封裝膠體130上以及接地環112a的側壁S1(或連接面S1)上,側壁S1係暴露於線路基板110的側面110c。在頂導電層112之下的第一內導電層114、第二內導電層116以及底導電層118可選擇性地分別包括接地環114a、116a、118a,如圖4所示。
圖7繪示本發明又一實施例之半導體元件封裝結構的剖面圖。請參照圖7,封裝結構700相似於圖5的封裝結構500,兩者的差異之處在於頂導電層112以及第一內導電層114分別具有接地環112a、114a(如圖4所示)。凹陷部117向下凹陷至線路基板110的第二介電層184並暴露出第二內導電層116的接地環116a。導電層140配置於封裝膠體130、接地環112a的側壁S1以及接地環114a的側壁S2上,側壁S1、S2暴露於線路基板110的側面110c。換言之,在第二介電層184之上的接地環112a、114a係經由側壁S1、S2而連接導電層140。此外,導電層140可形成在暴露於凹陷部117的接地環116a上。位於第二內導電層116之下的底導電層118可具有(或不具有)如圖4所示的接地環118a。
圖8繪示本發明再一實施例之半導體元件封裝結構的剖面圖。請參照圖8,封裝結構800相似於圖5的封裝結構500,兩者的差異之處在於頂導電層112、第一內導電層114、第二內導電層116以及底導電層118分別具有如圖4所示的接地環112a、114a、116a、118a。凹陷部117向下凹陷至線路基板110的一第三介電層186,且可暴露出(或未暴露出)底導電層118的接地環118a。導電層140形成在封裝膠體130、接地環112a的側壁S1、接地環114a的側壁S2以及接地環116a的側壁S3(或是連接面S3),其中側壁S1、S2、S3暴露於線路基板110的側面110c。換言之,位於第三介電層186之上的接地環112a、114a、116a係經由側壁S1、S2、S3而連接至導電層140。此外,導電層140可形成在凹陷部117所暴露出的接地環118a上。
因此,導電層可藉由接觸線路基板中的接地環的側壁而電性連接至接地平面或是線路基板的其他參考平面。舉例來說,可在封裝結構中建立一電性接地途徑以作為電磁干擾屏蔽,而毋須使用額外的接地平面。此外,由於接地環是沿著線路基板的邊緣延伸,因此,可增加接地環與導電層的接觸面積。此外,可提昇封裝結構的可靠度以及電磁干擾屏蔽的效果,並且可擴大切割製程的容錯視窗。
此外,本發明的實施例並不限制凹陷部的外形,凹陷部的外形可依切割工具的形狀、遮蔽需求、或是封裝體的其他電子特性、或是製程參數而作改變。
圖9繪示本發明另一實施例之半導體元件封裝結構的剖面圖。請參照圖9,封裝結構900相似於圖5的封裝結構500,兩者的差異之處在於凹陷部117的一底部117a呈弧狀,且接地環114a暴露於或是接近凹陷部117的弧狀底部117a。使線路基板110的凹陷部117呈弧狀可增加接地環114a的連接面(例如側壁S2)的面積,以提升電性連接的可靠度與效率,從而降低電磁干擾。
簡而言之,進行半切切割製程以降低線路基板的周邊部的厚度,並可使導電層與線路基板中的接地環電性連接,因此,導電層較佳地是連接至接地環的側壁。在本發明之多個實施例的半導體封裝結構中,導電層共形地覆蓋封裝膠體與線路基板,以作為電磁干擾屏蔽層,其可保護封裝結構免於受到周圍輻射源所發出的輻射的影響。導電層可電性連接接地平面或是線路基板的其他參考平面。舉例來說,可在封裝結構中建立一電性接地途徑以作為電磁干擾屏蔽,而毋須使用額外的接地平面。實質上完全覆蓋的導電層可有效地增加封裝結構屏蔽電磁干擾的能力。此外,線路基板的周邊部可向下凹陷以暴露出接地環的側壁。使線路基板的凹陷部呈弧狀可增加接地環的連接面的面積,以提升作為電磁干擾屏蔽的電性連接的可靠度與效率。此外,此種設計可相容於高頻元件的封裝結構,特別是射頻元件(radio frequency device)。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、500、600、700、800、900...封裝結構(半導體元件封裝)
102...線路基板條
106...導電凸塊
110...線路基板(基板單元)
110a...承載面
110b...底面
110c...側面
112...頂導電層
112a、114a、116a、118a...接地環
114...第一內導電層
116...第二內導電層
117...周邊部(凹陷部)
117a...底部
118...底導電層
120...電子元件(半導體元件或晶片)
130...封裝膠體(封膠結構)
130a...頂面
130b、170a...側壁
140...導電層
170...開口(第一組切割狹縫)
170b...底面
182...第一介電層
184...第二介電層
186...第三介電層
190...切割線(第二組切割狹縫)
D1...切割深度
S1、S2、S3...側壁(連接面)
T1...厚度
W1、W2...寬度
圖1A~圖1F繪示本發明一實施例之半導體元件封裝的製程示意圖。
圖2繪示圖1A~圖1F的線路基板條的第一內導電層的圖案的上視圖。
圖3繪示圖1D的結構的透視圖。
圖4繪示本發明一實施例之四層線路板的各導電層的圖案。
圖5繪示本發明一實施例之半導體元件封裝結構的剖面圖。
圖6繪示本發明另一實施例之半導體元件封裝結構的剖面圖。
圖7繪示本發明又一實施例之半導體元件封裝結構的剖面圖。
圖8繪示本發明再一實施例之半導體元件封裝結構的剖面圖。
圖9繪示本發明另一實施例之半導體元件封裝結構的剖面圖。
100...封裝結構(半導體元件封裝)
102...線路基板條
106...導電凸塊
110...線路基板(基板單元)
110a...承載面
110b...底面
110c...側面
112...頂導電層
114a...接地環
114...第一內導電層
116...第二內導電層
117...周邊部(凹陷部)
118...底導電層
120...電子元件(半導體元件或晶片)
130...封裝膠體(封膠結構)
130a...頂面
130b、170a...側壁
140...導電層
170...開口(第一組切割狹縫)
190...切割線(第二組切割狹縫)
S2...側壁(連接面)
W1、W2...寬度
Claims (17)
- 一種半導體元件封裝,包括:線路基板,包括:承載面;底面;側面,延伸於該承載面與該底面之間;導電層;以及接地環,其為實質上連續的圖案,且該接地環沿著該線路基板的邊緣延伸,該接地環暴露於該線路基板的該側面,且該導電層包括該接地環,其中該承載面的周邊部向下凹陷以形成凹陷部,該凹陷部沿著該線路基板的邊緣延伸,且該線路基板的該側面包括該凹陷部,該接地環暴露於該凹陷部中;電子元件,鄰近該承載面,並電性連接該線路基板的該導電層;封裝膠體,鄰近該承載面,並包覆該電子元件;以及導電層,配置於該封裝膠體上,並與該接地環暴露於該線路基板的該側面接觸。
- 如申請專利範圍第1項所述之半導體元件封裝,其中該線路基板為多層線路基板,該凹陷部向下凹陷至該線路基板的內層,且該導電層位於該內層上。
- 如申請專利範圍第1項所述之半導體元件封裝,其中該凹陷部的底部呈弧狀。
- 如申請專利範圍第3項所述之半導體元件封裝,其中該接地環暴露於該凹陷部之呈弧狀的該底部。
- 如申請專利範圍第1項所述之半導體元件封裝,其中部分該接地環係暴露於繞著整個線路基板的邊緣延伸的該側面。
- 如申請專利範圍第5項所述之半導體元件封裝,其中該導電層實質上配置於該接地環之暴露於該側面的整個部分上。
- 一種半導體元件封裝,包括:線路基板,包括:第一表面;第二相對面;第一接地環,包括第一外露連接面,該第一外露連接面位於該線路基板的該第一表面與該第二相對面之間,且該第一接地環在實質上平行於該第一表面與該第二相對面的第一平面上繞著該線路基板延伸至少50%;以及第二接地環,該第二接地環包括第二外露連接面,該第二外露連接面位於該線路基板的該第一表面與該第二相對面之間,該第二接地環在實質上平行於該第一平面的第二平面上繞著該線路基板延伸至少50%;電子元件,鄰近該第一表面,並電性連接該線路基板;封裝膠體,鄰近該第一表面,並包覆該電子元件;以及電磁干擾屏蔽,鄰近該封裝膠體,並與該第一接地環之該第一外露連接面接觸。
- 如申請專利範圍第7項所述之半導體元件封裝,其中該電磁干擾屏蔽包括共形的覆蓋層,該共形的覆蓋層實質上全面覆蓋該第一接地環的該第一外露連接面。
- 如申請專利範圍第8項所述之半導體元件封裝,其中該第一接地環的該第一外露連接面在該第一平面上圍繞整個線 路基板。
- 如申請專利範圍第7項所述之半導體元件封裝,其中該電磁干擾屏蔽包括共形的覆蓋層,該共形的覆蓋層的材質包括鋁、銅、鉻、金、銀、鎳、錫以及不銹鋼至少其中之一。
- 如申請專利範圍第7項所述之半導體元件封裝,其中該電磁干擾屏蔽實質上全面覆蓋該第二接地環的該第二外露連接面。
- 如申請專利範圍第7項所述之半導體元件封裝,其中該線路基板包括側面,該側面延伸於該線路基板的該第一表面與該第二相對面之間,該側面包括凹陷部;以及該第一接地環的該第一外露連接面暴露於該凹陷部。
- 如申請專利範圍第12項所述之半導體元件封裝,其中該凹陷部呈弧狀。
- 一種半導體元件封裝的製作方法,包括:提供基板,該基板包括:承載面;底面;以及接地環;將半導體元件電性連接至該基板的該承載面;提供封膠材料至該基板的該承載面,以形成覆蓋該半導體元件的封膠結構;形成第一組切割狹縫,該第一組切割狹縫貫穿該封膠結構並部分穿過該基板,以(a)使該封膠結構的一部分覆蓋該半導體元件,(b)暴露出該基板的側面的一部分,以及(c)使該接地環的一部分暴露於該側面; 形成導電層,該導電層鄰近覆蓋該半導體元件的該封膠結構的該部分以及該第一組切割狹縫所暴露出的該側面的該部分及與該第一組切割狹縫所暴露出的該接地環的該部分接觸;以及形成第二組切割狹縫,該第二組切割狹縫貫穿該導電層以及該基板,以(a)次分割該導電層以形成電磁干擾屏蔽,該電磁干擾屏蔽係鄰近該半導體元件、該側面之暴露於該第一組切割狹縫的部分以及該接地環之暴露於該第一組切割狹縫的部分,(b)次分割該基板以形成基板單元,該基板單元包括承載面,且該半導體元件鄰近該基板單元的該承載面,以及(c)使該基板單元包括該接地環,其中該接地環為實質上連續的圖案,該連續的圖案係沿著該基板單元的邊緣延伸,其中該第二組切割狹縫與該第一組切割狹縫對齊,且該第二組切割狹縫的至少其中之一的寬度小於該第一組切割狹縫的至少其中之一的寬度。
- 如申請專利範圍第14項所述之半導體元件封裝的製作方法,其中該第一組切割狹縫的至少其中之一的寬度為300微米至500微米。
- 如申請專利範圍第14項所述之半導體元件封裝的製作方法,其中該第二組切割狹縫的至少其中之一的寬度為250微米至350微米。
- 如申請專利範圍第14項所述之半導體元件封裝的製作方法,其中該第一組切割狹縫的至少其中之一呈弧狀。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/622,419 US8368185B2 (en) | 2009-11-19 | 2009-11-19 | Semiconductor device packages with electromagnetic interference shielding |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201119004A TW201119004A (en) | 2011-06-01 |
TWI569398B true TWI569398B (zh) | 2017-02-01 |
Family
ID=44010679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW099116088A TWI569398B (zh) | 2009-11-19 | 2010-05-20 | 半導體元件封裝及其製作方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8368185B2 (zh) |
CN (1) | CN102074552B (zh) |
TW (1) | TWI569398B (zh) |
Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8350367B2 (en) * | 2008-02-05 | 2013-01-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US7989928B2 (en) | 2008-02-05 | 2011-08-02 | Advanced Semiconductor Engineering Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8410584B2 (en) * | 2008-08-08 | 2013-04-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US20100110656A1 (en) | 2008-10-31 | 2010-05-06 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US8110902B2 (en) * | 2009-02-19 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US8212340B2 (en) | 2009-07-13 | 2012-07-03 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US8987030B2 (en) * | 2009-08-13 | 2015-03-24 | Knowles Electronics, Llc | MEMS package and a method for manufacturing the same |
US9399574B2 (en) | 2009-08-13 | 2016-07-26 | Knowles Electronics Llc | MEMS package and a method for manufacturing the same |
US8378466B2 (en) | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
TWI497679B (zh) * | 2009-11-27 | 2015-08-21 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US9362196B2 (en) * | 2010-07-15 | 2016-06-07 | Kabushiki Kaisha Toshiba | Semiconductor package and mobile device using the same |
TWI540698B (zh) | 2010-08-02 | 2016-07-01 | 日月光半導體製造股份有限公司 | 半導體封裝件與其製造方法 |
US9386734B2 (en) * | 2010-08-05 | 2016-07-05 | Epcos Ag | Method for producing a plurality of electronic devices |
US9007273B2 (en) | 2010-09-09 | 2015-04-14 | Advances Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US20120126378A1 (en) * | 2010-11-24 | 2012-05-24 | Unisem (Mauritius ) Holdings Limited | Semiconductor device package with electromagnetic shielding |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
TWM409527U (en) * | 2011-02-23 | 2011-08-11 | Azurewave Technologies Inc | Forming integrated circuit module |
TWI447888B (zh) * | 2011-06-13 | 2014-08-01 | Advanced Semiconductor Eng | 具有凹部之半導體結構及其製造方法 |
CN102364666A (zh) * | 2011-09-30 | 2012-02-29 | 常熟市广大电器有限公司 | 一种抗电磁干扰的芯片封装方法 |
CN103137608A (zh) * | 2011-11-25 | 2013-06-05 | 亚旭电子科技(江苏)有限公司 | 系统级封装模块件及其制造方法 |
CN103137595A (zh) * | 2011-11-25 | 2013-06-05 | 亚旭电子科技(江苏)有限公司 | 系统级封装模块件及其制造方法 |
JP2013161831A (ja) * | 2012-02-01 | 2013-08-19 | Mitsumi Electric Co Ltd | 電子モジュール及びその製造方法 |
KR20130111780A (ko) * | 2012-04-02 | 2013-10-11 | 삼성전자주식회사 | Emi 차폐부를 갖는 반도체 장치 |
US8937376B2 (en) | 2012-04-16 | 2015-01-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with heat dissipation structures and related methods |
US8786060B2 (en) | 2012-05-04 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
US8704341B2 (en) | 2012-05-15 | 2014-04-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with thermal dissipation structures and EMI shielding |
US8653634B2 (en) | 2012-06-11 | 2014-02-18 | Advanced Semiconductor Engineering, Inc. | EMI-shielded semiconductor devices and methods of making |
US8872338B2 (en) * | 2012-11-13 | 2014-10-28 | Freescale Semiconductor, Inc. | Trace routing within a semiconductor package substrate |
US8952503B2 (en) | 2013-01-29 | 2015-02-10 | International Business Machines Corporation | Organic module EMI shielding structures and methods |
US9978688B2 (en) | 2013-02-28 | 2018-05-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having a waveguide antenna and manufacturing method thereof |
CN103400825B (zh) * | 2013-07-31 | 2016-05-18 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
JP5756500B2 (ja) * | 2013-08-07 | 2015-07-29 | 太陽誘電株式会社 | 回路モジュール |
CN107818969A (zh) * | 2013-11-08 | 2018-03-20 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
US9620457B2 (en) * | 2013-11-26 | 2017-04-11 | Infineon Technologies Ag | Semiconductor device packaging |
KR20150073350A (ko) | 2013-12-23 | 2015-07-01 | 에스케이하이닉스 주식회사 | 전자기간섭 차폐층을 갖는 반도체 패키지 및 그 제조방법 |
FR3020742B1 (fr) * | 2014-05-05 | 2016-05-27 | Valeo Systemes De Controle Moteur | Systeme electrique avec blindage |
US9478472B2 (en) * | 2014-05-19 | 2016-10-25 | Dyi-chung Hu | Substrate components for packaging IC chips and electronic device packages of the same |
WO2015194435A1 (ja) * | 2014-06-20 | 2015-12-23 | 株式会社村田製作所 | 回路モジュール及びその製造方法 |
TWI584387B (zh) * | 2014-08-15 | 2017-05-21 | 矽品精密工業股份有限公司 | 封裝結構之製法 |
DE102014217260A1 (de) | 2014-08-29 | 2016-03-17 | Robert Bosch Gmbh | Halbleiterbauelement und Verfahren zum Herstellen von Halbleiterbauelementen |
TWI558284B (zh) * | 2014-10-03 | 2016-11-11 | 欣興電子股份有限公司 | 電路板元件與其製造方法 |
KR102295522B1 (ko) | 2014-10-20 | 2021-08-30 | 삼성전자 주식회사 | 반도체 패키지 |
CN105990317A (zh) * | 2015-02-25 | 2016-10-05 | 晟碟信息科技(上海)有限公司 | 具有电磁干扰屏蔽层和半导体装置和其制造方法 |
US9997468B2 (en) | 2015-04-10 | 2018-06-12 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with shielding and method of manufacturing thereof |
US9461001B1 (en) | 2015-07-22 | 2016-10-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same |
US10689249B2 (en) * | 2015-09-16 | 2020-06-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package including a wall and a grounding ring exposed from the wall |
KR20170067947A (ko) * | 2015-12-08 | 2017-06-19 | 에스케이하이닉스 주식회사 | 측면 차폐부를 가지는 반도체 패키지 및 제조 방법 |
US20170179041A1 (en) * | 2015-12-22 | 2017-06-22 | Intel Corporation | Semiconductor package with trenched molding-based electromagnetic interference shielding |
KR20170092309A (ko) * | 2016-02-03 | 2017-08-11 | 삼성전기주식회사 | 양면 패키지 모듈 및 기판 스트립 |
US9761538B1 (en) * | 2016-03-14 | 2017-09-12 | Stmicroelectronics, Inc. | Method for making a shielded integrated circuit (IC) package with an electrically conductive polymer layer |
US9793222B1 (en) * | 2016-04-21 | 2017-10-17 | Apple Inc. | Substrate designed to provide EMI shielding |
US10854556B2 (en) * | 2016-10-12 | 2020-12-01 | Advanced Semiconductor Engineering Korea, Inc. | Semiconductor package device and method of manufacturing the same |
US10037949B1 (en) * | 2017-03-02 | 2018-07-31 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US11189574B2 (en) | 2017-05-31 | 2021-11-30 | Intel Corporation | Microelectronic package having electromagnetic interference shielding |
CN109509736A (zh) * | 2017-09-14 | 2019-03-22 | 晨星半导体股份有限公司 | 电路板及芯片封装体 |
TWI655739B (zh) * | 2018-04-19 | 2019-04-01 | 南亞電路板股份有限公司 | 封裝結構及其形成方法 |
JP7063390B2 (ja) * | 2018-09-28 | 2022-05-09 | 株式会社村田製作所 | 電子部品モジュール |
CN109712964A (zh) * | 2018-10-16 | 2019-05-03 | 华为机器有限公司 | 一种封装件及其制造方法、以及电子设备 |
US11282729B2 (en) * | 2018-12-27 | 2022-03-22 | Areesys Technologies, Inc. | Method and apparatus for poling polymer thin films |
US11910715B2 (en) | 2018-12-27 | 2024-02-20 | Creesense Microsystems Inc. | Method and apparatus for poling polymer thin films |
JP7055109B2 (ja) * | 2019-01-17 | 2022-04-15 | 三菱電機株式会社 | 半導体装置 |
CN110335862A (zh) * | 2019-06-17 | 2019-10-15 | 青岛歌尔微电子研究院有限公司 | 一种sip封装的屏蔽工艺 |
CN111063661A (zh) * | 2019-12-16 | 2020-04-24 | 东莞记忆存储科技有限公司 | 倒装芯片封装方法 |
KR20220003342A (ko) * | 2020-07-01 | 2022-01-10 | 삼성전기주식회사 | 전자 소자 패키지 및 이의 제조방법 |
CN111987056A (zh) * | 2020-08-31 | 2020-11-24 | 英韧科技(上海)有限公司 | 具有与暴露的金属边缘连接的导热外层的电路组件设计 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150193A (en) * | 1996-10-31 | 2000-11-21 | Amkor Technology, Inc. | RF shielded device |
Family Cites Families (137)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1439460A1 (de) * | 1964-10-19 | 1968-12-12 | Siemens Ag | Elektrisches Bauelement,insbesondere Halbleiterbauelement,mit einer aus isolierendemStoff bestehenden Huelle |
JPS59172253A (ja) * | 1983-03-18 | 1984-09-28 | Mitsubishi Electric Corp | 半導体装置 |
JPS59189142A (ja) | 1983-04-12 | 1984-10-26 | Ube Ind Ltd | 導電性熱可塑性樹脂組成物 |
US4814205A (en) | 1983-12-02 | 1989-03-21 | Omi International Corporation | Process for rejuvenation electroless nickel solution |
US4821007A (en) * | 1987-02-06 | 1989-04-11 | Tektronix, Inc. | Strip line circuit component and method of manufacture |
FR2649530B1 (fr) * | 1989-07-06 | 1994-04-29 | Alsthom Gec | Brin supraconducteur multifilamentaire |
US5140745A (en) | 1990-07-23 | 1992-08-25 | Mckenzie Jr Joseph A | Method for forming traces on side edges of printed circuit boards and devices formed thereby |
US5557142A (en) | 1991-02-04 | 1996-09-17 | Motorola, Inc. | Shielded semiconductor device package |
US5166772A (en) | 1991-02-22 | 1992-11-24 | Motorola, Inc. | Transfer molded semiconductor device package with integral shield |
JP2616280B2 (ja) | 1991-04-27 | 1997-06-04 | 株式会社村田製作所 | 発振器及びその製造方法 |
DE4340594C2 (de) * | 1992-12-01 | 1998-04-09 | Murata Manufacturing Co | Verfahren zur Herstellung und zum Einstellen der Charakteristik eines oberflächenmontierbaren chipförmigen LC-Filters |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5355016A (en) | 1993-05-03 | 1994-10-11 | Motorola, Inc. | Shielded EPROM package |
FI117224B (fi) * | 1994-01-20 | 2006-07-31 | Nec Tokin Corp | Sähkömagneettinen häiriönpoistokappale, ja sitä soveltavat elektroninen laite ja hybridimikropiirielementti |
US6455864B1 (en) * | 1994-04-01 | 2002-09-24 | Maxwell Electronic Components Group, Inc. | Methods and compositions for ionizing radiation shielding |
US5639989A (en) | 1994-04-19 | 1997-06-17 | Motorola Inc. | Shielded electronic component assembly and method for making the same |
JP3541491B2 (ja) * | 1994-06-22 | 2004-07-14 | セイコーエプソン株式会社 | 電子部品 |
US5677511A (en) | 1995-03-20 | 1997-10-14 | National Semiconductor Corporation | Overmolded PC board with ESD protection and EMI suppression |
US5600181A (en) * | 1995-05-24 | 1997-02-04 | Lockheed Martin Corporation | Hermetically sealed high density multi-chip package |
DE29514398U1 (de) | 1995-09-07 | 1995-10-19 | Siemens Ag | Abschirmung für Flachbaugruppen |
US5847930A (en) | 1995-10-13 | 1998-12-08 | Hei, Inc. | Edge terminals for electronic circuit modules |
JP3432982B2 (ja) * | 1995-12-13 | 2003-08-04 | 沖電気工業株式会社 | 表面実装型半導体装置の製造方法 |
US5998867A (en) | 1996-02-23 | 1999-12-07 | Honeywell Inc. | Radiation enhanced chip encapsulant |
JP2938820B2 (ja) * | 1996-03-14 | 1999-08-25 | ティーディーケイ株式会社 | 高周波モジュール |
US5694300A (en) | 1996-04-01 | 1997-12-02 | Northrop Grumman Corporation | Electromagnetically channelized microwave integrated circuit |
JP2850860B2 (ja) * | 1996-06-24 | 1999-01-27 | 住友金属工業株式会社 | 電子部品の製造方法 |
US5776798A (en) * | 1996-09-04 | 1998-07-07 | Motorola, Inc. | Semiconductor package and method thereof |
JPH10284935A (ja) * | 1997-04-09 | 1998-10-23 | Murata Mfg Co Ltd | 電圧制御発振器およびその製造方法 |
US5895229A (en) * | 1997-05-19 | 1999-04-20 | Motorola, Inc. | Microelectronic package including a polymer encapsulated die, and method for forming same |
JP3834426B2 (ja) * | 1997-09-02 | 2006-10-18 | 沖電気工業株式会社 | 半導体装置 |
US6566596B1 (en) * | 1997-12-29 | 2003-05-20 | Intel Corporation | Magnetic and electric shielding of on-board devices |
US5977626A (en) | 1998-08-12 | 1999-11-02 | Industrial Technology Research Institute | Thermally and electrically enhanced PBGA package |
US6092281A (en) | 1998-08-28 | 2000-07-25 | Amkor Technology, Inc. | Electromagnetic interference shield driver and method |
US6194250B1 (en) * | 1998-09-14 | 2001-02-27 | Motorola, Inc. | Low-profile microelectronic package |
JP3617368B2 (ja) * | 1999-04-02 | 2005-02-02 | 株式会社村田製作所 | マザー基板および子基板ならびにその製造方法 |
US6376769B1 (en) | 1999-05-18 | 2002-04-23 | Amerasia International Technology, Inc. | High-density electronic package, and method for making same |
US6255143B1 (en) * | 1999-08-04 | 2001-07-03 | St. Assembly Test Services Pte Ltd. | Flip chip thermally enhanced ball grid array |
FR2799883B1 (fr) | 1999-10-15 | 2003-05-30 | Thomson Csf | Procede d'encapsulation de composants electroniques |
US6261680B1 (en) * | 1999-12-07 | 2001-07-17 | Hughes Electronics Corporation | Electronic assembly with charge-dissipating transparent conformal coating |
DE10002852A1 (de) * | 2000-01-24 | 2001-08-02 | Infineon Technologies Ag | Abschirmeinrichtung und elektrisches Bauteil mit einer Abschirmeinrichtung |
US20010033478A1 (en) | 2000-04-21 | 2001-10-25 | Shielding For Electronics, Inc. | EMI and RFI shielding for printed circuit boards |
US6757181B1 (en) * | 2000-08-22 | 2004-06-29 | Skyworks Solutions, Inc. | Molded shield structures and method for their fabrication |
US6448632B1 (en) * | 2000-08-28 | 2002-09-10 | National Semiconductor Corporation | Metal coated markings on integrated circuit devices |
US6586822B1 (en) * | 2000-09-08 | 2003-07-01 | Intel Corporation | Integrated core microelectronic package |
TW454321B (en) * | 2000-09-13 | 2001-09-11 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat dissipation structure |
CN2457740Y (zh) | 2001-01-09 | 2001-10-31 | 台湾沛晶股份有限公司 | 集成电路晶片的构装 |
US20020093108A1 (en) * | 2001-01-15 | 2002-07-18 | Grigorov Ilya L. | Flip chip packaged semiconductor device having double stud bumps and method of forming same |
US6472743B2 (en) | 2001-02-22 | 2002-10-29 | Siliconware Precision Industries, Co., Ltd. | Semiconductor package with heat dissipating structure |
JP3718131B2 (ja) | 2001-03-16 | 2005-11-16 | 松下電器産業株式会社 | 高周波モジュールおよびその製造方法 |
US6900383B2 (en) * | 2001-03-19 | 2005-05-31 | Hewlett-Packard Development Company, L.P. | Board-level EMI shield that adheres to and conforms with printed circuit board component and board surfaces |
JP3878430B2 (ja) | 2001-04-06 | 2007-02-07 | 株式会社ルネサステクノロジ | 半導体装置 |
TW495943B (en) * | 2001-04-18 | 2002-07-21 | Siliconware Precision Industries Co Ltd | Semiconductor package article with heat sink structure and its manufacture method |
US6614102B1 (en) * | 2001-05-04 | 2003-09-02 | Amkor Technology, Inc. | Shielded semiconductor leadframe package |
US6686649B1 (en) * | 2001-05-14 | 2004-02-03 | Amkor Technology, Inc. | Multi-chip semiconductor package with integral shield and antenna |
JP3645197B2 (ja) | 2001-06-12 | 2005-05-11 | 日東電工株式会社 | 半導体装置およびそれに用いる半導体封止用エポキシ樹脂組成物 |
JP3865601B2 (ja) * | 2001-06-12 | 2007-01-10 | 日東電工株式会社 | 電磁波抑制体シート |
US6740959B2 (en) | 2001-08-01 | 2004-05-25 | International Business Machines Corporation | EMI shielding for semiconductor chip carriers |
US7126218B1 (en) | 2001-08-07 | 2006-10-24 | Amkor Technology, Inc. | Embedded heat spreader ball grid array |
US6856007B2 (en) * | 2001-08-28 | 2005-02-15 | Tessera, Inc. | High-frequency chip packages |
TW550997B (en) | 2001-10-18 | 2003-09-01 | Matsushita Electric Ind Co Ltd | Module with built-in components and the manufacturing method thereof |
KR100431180B1 (ko) * | 2001-12-07 | 2004-05-12 | 삼성전기주식회사 | 표면 탄성파 필터 패키지 제조방법 |
JP2003273571A (ja) | 2002-03-18 | 2003-09-26 | Fujitsu Ltd | 素子間干渉電波シールド型高周波モジュール |
US7633765B1 (en) | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US7161252B2 (en) | 2002-07-19 | 2007-01-09 | Matsushita Electric Industrial Co., Ltd. | Module component |
JP3738755B2 (ja) * | 2002-08-01 | 2006-01-25 | 日本電気株式会社 | チップ部品を備える電子装置 |
US6740546B2 (en) * | 2002-08-21 | 2004-05-25 | Micron Technology, Inc. | Packaged microelectronic devices and methods for assembling microelectronic devices |
JP4178880B2 (ja) * | 2002-08-29 | 2008-11-12 | 松下電器産業株式会社 | モジュール部品 |
US6781231B2 (en) * | 2002-09-10 | 2004-08-24 | Knowles Electronics Llc | Microelectromechanical system package with environmental and interference shield |
US7205647B2 (en) * | 2002-09-17 | 2007-04-17 | Chippac, Inc. | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
US7034387B2 (en) * | 2003-04-04 | 2006-04-25 | Chippac, Inc. | Semiconductor multipackage module including processor and memory package assemblies |
US6962869B1 (en) | 2002-10-15 | 2005-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | SiOCH low k surface protection layer formation by CxHy gas plasma treatment |
WO2004060034A1 (ja) | 2002-12-24 | 2004-07-15 | Matsushita Electric Industrial Co., Ltd. | 電子部品内蔵モジュール |
US20040150097A1 (en) * | 2003-01-30 | 2004-08-05 | International Business Machines Corporation | Optimized conductive lid mounting for integrated circuit chip carriers |
TWI235469B (en) * | 2003-02-07 | 2005-07-01 | Siliconware Precision Industries Co Ltd | Thermally enhanced semiconductor package with EMI shielding |
US7187060B2 (en) * | 2003-03-13 | 2007-03-06 | Sanyo Electric Co., Ltd. | Semiconductor device with shield |
CN100454533C (zh) | 2003-04-15 | 2009-01-21 | 波零公司 | 用于电子元件封装的emi屏蔽 |
US6838776B2 (en) * | 2003-04-18 | 2005-01-04 | Freescale Semiconductor, Inc. | Circuit device with at least partial packaging and method for forming |
JP4377157B2 (ja) | 2003-05-20 | 2009-12-02 | Necエレクトロニクス株式会社 | 半導体装置用パッケージ |
US6867480B2 (en) * | 2003-06-10 | 2005-03-15 | Lsi Logic Corporation | Electromagnetic interference package protection |
TWI236118B (en) | 2003-06-18 | 2005-07-11 | Advanced Semiconductor Eng | Package structure with a heat spreader and manufacturing method thereof |
US7129422B2 (en) | 2003-06-19 | 2006-10-31 | Wavezero, Inc. | EMI absorbing shielding for a printed circuit board |
KR100541084B1 (ko) | 2003-08-20 | 2006-01-11 | 삼성전기주식회사 | 표면 탄성파 필터 패키지 제조방법 및 그에 사용되는패키지 시트 |
JP2005072095A (ja) | 2003-08-20 | 2005-03-17 | Alps Electric Co Ltd | 電子回路ユニットおよびその製造方法 |
US7372151B1 (en) * | 2003-09-12 | 2008-05-13 | Asat Ltd. | Ball grid array package and process for manufacturing same |
US7030469B2 (en) * | 2003-09-25 | 2006-04-18 | Freescale Semiconductor, Inc. | Method of forming a semiconductor package and structure thereof |
US6943423B2 (en) | 2003-10-01 | 2005-09-13 | Optopac, Inc. | Electronic package of photo-image sensors in cellular phone camera modules, and the fabrication and assembly thereof |
US6992400B2 (en) * | 2004-01-30 | 2006-01-31 | Nokia Corporation | Encapsulated electronics device with improved heat dissipation |
US7276724B2 (en) * | 2005-01-20 | 2007-10-02 | Nanosolar, Inc. | Series interconnected optoelectronic device module assembly |
US7327015B2 (en) * | 2004-09-20 | 2008-02-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
JP4453509B2 (ja) * | 2004-10-05 | 2010-04-21 | パナソニック株式会社 | シールドケースを装着された高周波モジュールとこの高周波モジュールを用いた電子機器 |
KR100592787B1 (ko) * | 2004-11-09 | 2006-06-26 | 삼성전자주식회사 | 링 형태의 실리콘 디커플링 커패시터를 가지는 집적회로칩 패키지 |
US7629674B1 (en) | 2004-11-17 | 2009-12-08 | Amkor Technology, Inc. | Shielded package having shield fence |
US7656047B2 (en) * | 2005-01-05 | 2010-02-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and manufacturing method |
JP2006190767A (ja) * | 2005-01-05 | 2006-07-20 | Shinko Electric Ind Co Ltd | 半導体装置 |
US7633170B2 (en) * | 2005-01-05 | 2009-12-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and manufacturing method thereof |
US20090230487A1 (en) * | 2005-03-16 | 2009-09-17 | Yamaha Corporation | Semiconductor device, semiconductor device manufacturing method and lid frame |
US7446265B2 (en) | 2005-04-15 | 2008-11-04 | Parker Hannifin Corporation | Board level shielding module |
DE602006012571D1 (de) * | 2005-04-21 | 2010-04-15 | St Microelectronics Sa | Vorrichtung zum Schutz einer elektronischen Schaltung |
JP4614278B2 (ja) * | 2005-05-25 | 2011-01-19 | アルプス電気株式会社 | 電子回路ユニット、及びその製造方法 |
US7451539B2 (en) | 2005-08-08 | 2008-11-18 | Rf Micro Devices, Inc. | Method of making a conformal electromagnetic interference shield |
US8220145B2 (en) * | 2007-06-27 | 2012-07-17 | Rf Micro Devices, Inc. | Isolated conformal shielding |
JP4816647B2 (ja) * | 2005-11-28 | 2011-11-16 | 株式会社村田製作所 | 回路モジュールの製造方法および回路モジュール |
US7445968B2 (en) | 2005-12-16 | 2008-11-04 | Sige Semiconductor (U.S.), Corp. | Methods for integrated circuit module packaging and integrated circuit module packages |
US7342303B1 (en) | 2006-02-28 | 2008-03-11 | Amkor Technology, Inc. | Semiconductor device having RF shielding and method therefor |
JP5598787B2 (ja) | 2006-04-17 | 2014-10-01 | マイクロンメモリジャパン株式会社 | 積層型半導体装置の製造方法 |
DE102006019080B3 (de) * | 2006-04-25 | 2007-08-30 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Herstellungsverfahren für ein gehäustes Bauelement |
US20080128890A1 (en) | 2006-11-30 | 2008-06-05 | Advanced Semiconductor Engineering, Inc. | Chip package and fabricating process thereof |
CN101617400A (zh) * | 2007-01-31 | 2009-12-30 | 富士通微电子株式会社 | 半导体器件及其制造方法 |
CN101286488A (zh) * | 2007-04-12 | 2008-10-15 | 矽品精密工业股份有限公司 | 导线架与以导线架为芯片承载件的覆晶型半导体封装件 |
US7576415B2 (en) * | 2007-06-15 | 2009-08-18 | Advanced Semiconductor Engineering, Inc. | EMI shielded semiconductor package |
US7745910B1 (en) * | 2007-07-10 | 2010-06-29 | Amkor Technology, Inc. | Semiconductor device having RF shielding and method therefor |
US20090035895A1 (en) * | 2007-07-30 | 2009-02-05 | Advanced Semiconductor Engineering, Inc. | Chip package and chip packaging process thereof |
US7651889B2 (en) * | 2007-09-13 | 2010-01-26 | Freescale Semiconductor, Inc. | Electromagnetic shield formation for integrated circuit die package |
EP2051298B1 (en) * | 2007-10-18 | 2012-09-19 | Sencio B.V. | Integrated Circuit Package |
US8178956B2 (en) * | 2007-12-13 | 2012-05-15 | Stats Chippac Ltd. | Integrated circuit package system for shielding electromagnetic interference |
US7723157B2 (en) | 2007-12-28 | 2010-05-25 | Walton Advanced Engineering, Inc. | Method for cutting and molding in small windows to fabricate semiconductor packages |
US7989928B2 (en) * | 2008-02-05 | 2011-08-02 | Advanced Semiconductor Engineering Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8022511B2 (en) * | 2008-02-05 | 2011-09-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8212339B2 (en) * | 2008-02-05 | 2012-07-03 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8350367B2 (en) | 2008-02-05 | 2013-01-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8115285B2 (en) | 2008-03-14 | 2012-02-14 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
US7906371B2 (en) | 2008-05-28 | 2011-03-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield |
US8101460B2 (en) | 2008-06-04 | 2012-01-24 | Stats Chippac, Ltd. | Semiconductor device and method of shielding semiconductor die from inter-device interference |
US7772046B2 (en) * | 2008-06-04 | 2010-08-10 | Stats Chippac, Ltd. | Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference |
TWI453877B (zh) * | 2008-11-07 | 2014-09-21 | Advanced Semiconductor Eng | 內埋晶片封裝的結構及製程 |
US7829981B2 (en) | 2008-07-21 | 2010-11-09 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8410584B2 (en) * | 2008-08-08 | 2013-04-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US20100110656A1 (en) * | 2008-10-31 | 2010-05-06 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US7741151B2 (en) * | 2008-11-06 | 2010-06-22 | Freescale Semiconductor, Inc. | Integrated circuit package formation |
US7799602B2 (en) * | 2008-12-10 | 2010-09-21 | Stats Chippac, Ltd. | Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure |
US20100207257A1 (en) * | 2009-02-17 | 2010-08-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
US8110902B2 (en) | 2009-02-19 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
WO2010096781A1 (en) * | 2009-02-20 | 2010-08-26 | Brenner Mary K | Direct modulated modified vertical cavity surface emitting lasers |
US8212340B2 (en) * | 2009-07-13 | 2012-07-03 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US8030750B2 (en) * | 2009-11-19 | 2011-10-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8378466B2 (en) * | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
TWI497679B (zh) * | 2009-11-27 | 2015-08-21 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
-
2009
- 2009-11-19 US US12/622,419 patent/US8368185B2/en active Active
-
2010
- 2010-05-20 TW TW099116088A patent/TWI569398B/zh active
- 2010-06-01 CN CN2010101949453A patent/CN102074552B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150193A (en) * | 1996-10-31 | 2000-11-21 | Amkor Technology, Inc. | RF shielded device |
Also Published As
Publication number | Publication date |
---|---|
TW201119004A (en) | 2011-06-01 |
US8368185B2 (en) | 2013-02-05 |
US20110115059A1 (en) | 2011-05-19 |
CN102074552A (zh) | 2011-05-25 |
CN102074552B (zh) | 2013-01-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI569398B (zh) | 半導體元件封裝及其製作方法 | |
TWI387070B (zh) | 晶片封裝體及其製作方法 | |
US8030750B2 (en) | Semiconductor device packages with electromagnetic interference shielding | |
CN106449556B (zh) | 具有散热结构及电磁干扰屏蔽的半导体封装件 | |
US8212340B2 (en) | Chip package and manufacturing method thereof | |
TWI540698B (zh) | 半導體封裝件與其製造方法 | |
US9236356B2 (en) | Semiconductor package with grounding and shielding layers | |
JP6571124B2 (ja) | 電子部品モジュールの製造方法 | |
TWI528625B (zh) | 具有波導管天線之半導體封裝件及其製造方法 | |
JP2004119863A (ja) | 回路装置およびその製造方法 | |
KR20080081341A (ko) | 몰드형 어레이 패키지에 통합 무선 주파수 차폐물을제공하는 방법 및 시스템 | |
US20150171019A1 (en) | Semiconductor device and method of manufacturing the same | |
TWI692069B (zh) | 半導體裝置及半導體裝置之製造方法 | |
JP2013197209A (ja) | 半導体装置及びその製造方法 | |
CN109545770B (zh) | 半导体封装结构 | |
US11942437B2 (en) | Semiconductor package including an electromagnetic shield and method of fabricating the same | |
KR100611291B1 (ko) | 회로 장치, 회로 모듈 및 회로 장치의 제조 방법 | |
US10629544B2 (en) | Semiconductor packages | |
TWI663663B (zh) | 電子封裝構件及其製作方法 | |
TWI795959B (zh) | 表面黏著式功率半導體封裝元件及其製法 | |
US20230230949A1 (en) | Semiconductor package with exposed electrical contacts | |
KR101870421B1 (ko) | Ems 안테나 모듈 및 그 제조방법과 이를 포함하는 반도체 패키지 | |
TW201322317A (zh) | 系統級封裝模組件及其製造方法 | |
JP2012069698A (ja) | 電子回路モジュールの製造方法及び電子回路モジュール |