TWI528625B - 具有波導管天線之半導體封裝件及其製造方法 - Google Patents

具有波導管天線之半導體封裝件及其製造方法 Download PDF

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TWI528625B
TWI528625B TW102142680A TW102142680A TWI528625B TW I528625 B TWI528625 B TW I528625B TW 102142680 A TW102142680 A TW 102142680A TW 102142680 A TW102142680 A TW 102142680A TW I528625 B TWI528625 B TW I528625B
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conductive
semiconductor package
package
wafer
forming
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TW201434198A (zh
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顏瀚琦
陳士元
賴建伯
鄭銘賢
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日月光半導體製造股份有限公司
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Description

具有波導管天線之半導體封裝件及其製造方法
本發明是有關於一種半導體封裝件及其製造方法，且特別是有關於一種具有波導管天線之半導體封裝件及其製造方法。
無線通訊裝置，例如是手機(cell phone)，需要天線以傳輸及接收無線射頻(radio frequency,RF)訊號。傳統上，一無線通訊裝置包括一天線及一通訊模組(例如，一具有無線射頻通訊能力的半導體裝置)，其各設置於電路板的不同部分。在此情況下，天線及通訊模組各別製作且設置於電路板上後再電性連接。因此，導致高製造成本且難以縮小裝置尺寸。
此外，隨著感測器、雷達、高資料率連結及聚焦功率(focused power)，毫米波(millimeter-wave)頻率的應用變得更為急切。短波長運作的優點包括減小其物理尺寸。然而，由於電性連接容易成為影響波長的一可觀部分，使小尺寸天線的電路難以製造。
根據本發明之一實施例，提出一種半導體封裝件。半導體封裝件包括一基板、一接地層、一包覆體、一導電孔、一屏蔽層及至少一訊號發射開口。基板包括一晶片。接地層設置於基板上。包覆體覆蓋晶片及接地層。導電孔從包覆體之一上表面延伸至接地層。屏蔽層設置於包覆體，且電性連接於導電孔。訊號發射開口位於包覆體內且露出一定義一波導部的腔體。
根據本發明之一實施例，提出一種半導體封裝件。半導體封裝件包括一基板、一封裝體、一接地層、一包覆體、一導電孔、一屏蔽層及至少一訊號發射開口。基板包括一晶片。封裝體包覆晶片。接地層設置於封裝體之一上表面上。包覆體覆蓋封裝體及接地層。導電孔從包覆體之一上表面延伸至接地層。屏蔽層設置於包覆體且電性連接於導電孔。訊號發射開口位於包覆體內且露出一定義一波導部的腔體。
根據本發明之另一實施例，提出一種半導體封裝件的製造方法。製造方法包括以下步驟。提供一基板，基板包括一晶片；形成一包覆體包覆基板及晶片，其中包覆體具有一上表面；形成一導電元件以定義一波導腔體，其中導電元件設置於一接地層；形成一屏蔽層於包覆體之上表面，其中導電元件電性連接屏蔽層且屏蔽層具有一對應波導腔體之開孔；其中，接地層、屏蔽層與導電元件形成一波導管天線。
為了對本發明之上述及其他方面有更佳的瞭解，下 文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
100、200、300、400、500、600、700、800、900‧‧‧半導體封裝件
110‧‧‧基板
110s、130s、150s、531s‧‧‧側面
110b‧‧‧底面
110u、130u、531u‧‧‧上表面
111‧‧‧晶片
112‧‧‧被動元件
113‧‧‧接地元件
115‧‧‧饋入接點
117‧‧‧導電走線
120‧‧‧接地層
130‧‧‧包覆體
131、5311、5312、5313‧‧‧貫孔
140‧‧‧屏蔽層
140a‧‧‧開孔
141‧‧‧側部
150、151、152、450、553‧‧‧導電元件
150a‧‧‧訊號發射開口
150r‧‧‧波導腔體
190‧‧‧載板
195‧‧‧貼片
451‧‧‧第一分支
452‧‧‧第二分支
451e‧‧‧第一端
452e‧‧‧第二端
530‧‧‧覆蓋體
531‧‧‧封裝體
531a‧‧‧凹槽
551‧‧‧饋入元件
H‧‧‧間距
P‧‧‧切割道
S1‧‧‧距離
W‧‧‧寬度
第1A圖繪示依據本發明一實施例之半導體封裝件的立體圖。
第1B圖繪示第1A圖中沿方向1B-1B’的剖視圖。
第1C圖繪示第1A圖之俯視圖。
第2圖繪示依照本發明另一實施例之半導體封裝件的立體圖。
第3圖繪示依照本發明另一實施例之半導體封裝件的立體圖。
第4A圖繪示依照本發明另一實施例之半導體封裝件的立體圖。
第4B圖繪示第4A圖中沿方向4B-4B’的剖視圖。
第5A圖繪示依照本發明另一實施例之半導體封裝件的立體圖。
第5B圖繪示第5A圖中沿方向5B-5B’的剖視圖。
第6圖繪示依照本發明另一實施例之半導體封裝件的立體圖。
第7圖繪示依照本發明另一實施例之半導體封裝件的立體圖。
第8A圖繪示依照本發明另一實施例之半導體封裝件的立體圖。
第8B圖繪示第8A圖中沿方向8B-8B’的剖視圖。
第9A圖繪示依照本發明另一實施例之半導體封裝件的立體圖。
第9B圖繪示第9B圖中沿方向9B-9B’的剖視圖。
第10A至10G圖繪示第1A圖之半導體封裝件的製造過程圖。
第11圖繪示第2圖之半導體封裝件製造過程圖。
第12圖繪示第3圖之半導體封裝件製造過程圖。
第13A至13C圖繪示第4B圖之半導體封裝件製造過程圖。
第14A至14G圖繪示第5B圖之半導體封裝件製造過程圖。
第15圖繪示第6圖之半導體封裝件的製造過程圖。
第16圖繪示第7圖之半導體封裝件的製造過程圖。
第17A至17C圖繪示第8B圖之半導體封裝件的製造過程圖。
請參照第1A圖，其繪示依據本發明一實施例之半導體封裝件100的立體圖。半導體封裝件100包括基板110、饋入接點115、接地層120、包覆體130、屏蔽層140及數個導電元件150。
基板110設有至少一晶片111及至少一被動元件112，其中晶片111例如是無線射頻晶片。晶片111以朝下方位設置於基板110的上表面110u上，例如，晶片111的主動面朝向基板110。晶片111透過數個銲球電性連接於基板110。這樣的結構稱為覆晶(flip chip)。另一例中，晶片111以朝上方位設置於基板110上，例如，晶片111的主動面背向基板110。在此設計下，晶片111透過數個銲線電性連接於基板110。被動元件112可以是電阻、電感、電容或其不具主動電路的組合。此外，基板110例如是多層有機基板或一陶瓷基板。饋入接點115設置於基板110且電性連接於晶片111。
包覆體130包覆接地層120及晶片111，其中包覆體130具有上表面130u。包覆體130的材料包含酚醛基樹脂(Novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其他適當之包覆劑。較佳地，材料係低散熱係數(low dissipation factor)，其中材料的耗損因數(loss tangent)實質上低於約0.1。
屏蔽層140形成於包覆體130的上表面130u、包覆體130 的側面130s與基板110的側面110s。屏蔽層140具有開孔140a，其形成於屏蔽層140的側部141而露出一些導電元件150。屏蔽層140可包含鋁、銅、鉻、錫、金、銀、鎳、不銹鋼或任何其它合適材料或合金。此外，屏蔽層140可以是多層結構或單層結構。
被包覆體130包覆的導電元件150設置於接地層120且電性連接於屏蔽層140。因此，導電元件150、接地層120及屏蔽層140共同形成一波導管天線。導電元件150能引導RF精確地至所需部位，並作為一高通濾波器(High Pass Filter)。波導腔體150r由數個導電元件150及一訊號發射開口150a所定義，訊號發射開口150a形成於包覆體130的側面130s且對應於數個導電元件150。RF訊號於波導腔體150r內受到引導，然後從訊號發射開口150a發射出半導體封裝件100外。
如第1A圖所示，訊號發射開口150a的寬度W決定截止頻率(cutoff frequency)fc。截止頻率係所有低頻被數個導電元件150減弱的頻率，且所有高頻傳播於數個導電元件150內。截止頻率的公式如下式(1)。
如上式，c係於波導內的光速。
請參照第1B圖，其繪示第1A圖中沿方向1B-1B’的剖視圖。接地層120形成於基板110的上表面110u且電性連接於一形成於基板110內的接地元件113。接地元件113電性連接於一印刷電路板(PCB)或一基板的一接地端(未繪示)，使接地層120透過接地元件113電性連接於接地端。本實施例中，接地元件113係一導電孔(conductive via)，其從上表面 110u延伸至底面110b。另一實施例中，接地元件113係一圖案化導電層。
如第1B圖所示，包覆體130具有數個貫孔或開口131，如封膠貫孔(through mold via,TMV)，其從包覆體130的上表面130u延伸至接地層120。導電元件150係以導電材料填入包覆體130的開口131而形成，導電材料如銅、鋁、錫、鎳、金或銀。因此，導電元件可電性連接屏蔽層140與接地層120。導電元件包括導電元件151，其連接饋入接點115與屏蔽層140。其它導電元件150連接於接地層120。由於導電元件151用於傳輸RF訊號，其它導電元件150的一個可鄰近導電元件151設置，而減少電磁干擾(EMI)。
請參照第1C圖，其繪示第1A圖之俯視圖。半導體封裝件100更包括一導電走線117，其連接晶片111與饋入接點115。例如，導電走線117用於傳輸來自於導電元件151的RF訊號至晶片111，例如是基頻晶片(baseband chip)。因此，一些導電元件150鄰近晶片111及導電走線117設置，以避免導電走線117受到電磁干擾。此外，導電元件150包括二周邊導電元件152從包覆體130及訊號發射開口150a露出。另一例中，所有的導電元件150可被包覆體130覆蓋。
如第1C圖所示，相鄰二導電元件150的間距H從訊號發射開口150a往饋入接點115方向漸縮，使數個導電元件150排列成一漏斗型。相鄰二導電元件150的距離S1及相鄰二導電元件150的間距H可由發射之無線訊號的一等效波長決定。
請參照第2圖，其繪示依照本發明另一實施例之半導體封裝件200的立體圖。半導體封裝件200包括基板110、饋入接點115、接地層 120、包覆體130、屏蔽層140及數個導電元件150。
屏蔽層140具有開孔140a，其重疊於接地層120的一部分，使一RF訊號從開孔140a往上發射。開孔140a鄰近周邊導電元件152設置。然而，這樣的方位非用以限制本發明實施例。開孔140a的外形係一矩形。另一例中，開孔140a的外形可以是圓形、橢圓形或其它形式的多邊形。
請參照第3圖，其繪示依照本發明另一實施例之半導體封裝件300的立體圖。半導體封裝件300包括基板110、饋入接點115、接地層120、包覆體130、屏蔽層140及數個導電元件150。
屏蔽層140具有數個開孔140a，其重疊於接地層120的一部分，使一RF訊號從開孔140a往上發射。至少一開孔140a係形成於屏蔽層140的矩形開口。另一例中，至少一開孔140a係一圓形開口、橢圓形開口或其它形式的多邊形開口。本例中，數個開孔140a排列成線形。另一例中，數個開孔140a排列成矩陣形。
請參照第4A圖，其繪示依照本發明另一實施例之半導體封裝件400的立體圖。半導體封裝件400包括基板110、饋入接點115、接地層120、包覆體130、屏蔽層140及一導電元件450。
導電元件450係一導電架，且導電元件450、接地層120與屏蔽層140共同形成一波導管天線。波導腔體150r及訊號發射開口150a由導電元件450定義。在此情況下，一RF訊號於波導腔體150r受到引導，然後從訊號發射開口150a發射至半導體封裝件400外。
如第4A圖所示，導電元件450包括第一分支451及第二分支452。第一分支451與第二分支452彼此分離，且波導腔體150r定義於 第一分支451與第二分支452之間。第一分支451具有一第一端451e，第二分支452具有一第二端452e。屏蔽層140具有一開孔140a，其形成於屏蔽層140的側部141。第一分支451及第二分支452從包覆體130及開孔140a露出。第一分支451與第二分支452的間距H從相對二第一分支451與第二分支452往饋入接點115方向漸縮，使導電元件450排列成漏斗型。一無線訊號於波導腔體150r內受到引導，然後從訊號發射開口150a發射至半導體封裝件400外，其中訊號發射開口150a從開孔140a露出。
請參照第4B圖，其繪示第4A圖中沿方向4B-4B’的剖視圖。導電元件450設置於接地層120且透過接地層120電性連接於接地元件113。因此，導電元件450環繞饋入接點115及走線117，可避免饋入接點115及走線117受到電磁干擾。
請參照第5A圖，其繪示依照本發明另一實施例之半導體封裝件500的立體圖。半導體封裝件500包括基板110、饋入接點115、接地層120、覆蓋體530、屏蔽層140及數個導電元件150。
如第5A圖所示，晶片111及至少一被動元件112設置於基板110上，其中，晶片111例如是基頻晶片及RF晶片。覆蓋體530包括封裝體531及包覆體130。封裝體531覆蓋晶片111、饋入接點115及走線117且具有一上表面531u。接地層120形成於封裝體531的上表面531u，且包覆體130壓在接地層120上。數個導電元件150形成於包覆體130。因此，晶片111及導電元件150重疊，如垂直方位所示。此外，接地層120的至少一部分與晶片111重疊，以避免晶片111受到電磁干擾。
請參照第5B圖，其繪示第5A圖中沿方向5B-5B’的剖視圖。 半導體封裝件500包括基板110、饋入接點115、接地層120、包覆體130、屏蔽層140及一導電元件450。封裝體531具有一饋入貫孔5311及一饋入元件551，其中饋入貫孔5311露出饋入接點115，而饋入元件551藉由導電材料填入饋入貫孔5311而形成。饋入元件551被封裝體531包覆，且電性連接於饋入接點115。包覆體130具有一貫孔131露出饋入元件551，且導電元件150藉由填入導電材料於貫孔131而形成並電性連接於饋入元件551。
如第5B圖所示，封裝體531具有一接地貫孔5312及一接地元件552，其中接地貫孔5312露出接地元件113，而接地元件552藉由導電材料填入接地貫孔5312而形成並電性連接於接地元件113。包覆體130具有一露出接地元件552之貫孔131，且導電元件150藉由導電材料填入貫孔131而形成並電性連接於接地元件552。
如第5B圖所示，包覆體130具有數個貫孔131及其它數個導電元件150，其中貫孔131露出接地層130之數個貫孔131，而其它導電元件150藉由導電元件填入貫孔131而形成，並電性連接於接地層120及屏蔽層140。
請參照第6圖，其繪示依照本發明另一實施例之半導體封裝件600的立體圖。半導體封裝件600包括基板110、饋入接點115、接地層120、覆蓋體530、屏蔽層140及數個導電元件150。
屏蔽層140具有開孔140a，開孔140a與接地層120的一區域重疊，可使無線射頻訊號透過開孔140a朝上發射。本實施例中，開孔140a係屏蔽層140的一矩形開口。另一實施例中，開孔140a可形成圓形、橢圓 形或不同的多邊形；然而，本發明實施例不限於此。
請參照第7圖，其繪示依照本發明另一實施例之半導體封裝件700的立體圖。半導體封裝件700包括基板110、饋入接點115、接地層120、覆蓋體530、屏蔽層140及數個導電元件150。
屏蔽層140具有開孔140a，開孔140a與接地層120的一區域重疊，可使無線射頻訊號透過開孔140a朝上發射。此些開孔140a的至少一者係屏蔽層140的矩形開口。另一實施例中，此些開孔140a的至少一者可形成圓形、橢圓形或不同的多邊形。本實施例中，數個開孔140a排列成直線。另一例中，數個開孔140a排列成矩陣形。
請參照第8A圖，其繪示依照本發明另一實施例之半導體封裝件800的立體圖。半導體封裝件800包括基板110、饋入接點115(第8B圖)、接地層120、覆蓋體530、屏蔽層140及數個導電元件450。
導電元件450係一導電架，且導電元件450、導電元件450與接地層120共同形成一波長天線。波導腔體150r及訊號發射開口150a由導電元件450定義。無線射頻訊號於波導腔體150r內受到引導，然後經由訊號發射開口150a從半導體封裝件800發射。
請參照第8B圖，其繪示第8A圖中沿方向8B-8B’的剖視圖。覆蓋體530包括封裝體531及包覆體130。導電元件450設置於包覆晶片111、饋入接點115及導電走線117之封裝體531上方。接地層120形成於封裝體531之上表面531u，且包覆體130形成於接地層120上。
如第8B圖所示，封裝體531具有饋入貫孔5311及饋入元件551，其中饋入貫孔5311露出饋入接點115，而饋入元件551藉由導電 材料填入饋入貫孔5311而形成且電性連接於饋入接點115。包覆體130具有露出饋入元件551之貫孔131，而導電元件150藉由導電材料填入貫孔131而形成且透過饋入元件551電性連接於饋入接點115。
封裝體531具有一接地貫孔5312及一接地元件552。接地貫孔5312露出接地元件113，而接地元件552藉由填入接地貫孔5312而形成且電性連接於接地層120。在此設計下，接地層120透過被封裝體531包覆之接地元件552電性連接接地元件113。
封裝體531具有一貫孔5313及一導電元件553。貫孔5313露出第一基板110的上表面110u，而導電元件553藉由導電材料填入貫孔5313而形成，其中導電材料例如是以電鍍，或塗佈(apply)焊料貼(solder paste)或其它導電材料形成。此外，數個導電元件553可鄰近饋入元件551及饋入接點115設置，以避免饋入元件551及饋入接點115受到電磁干擾。
請參照第9A圖，其繪示依照本發明另一實施例之半導體封裝件900的立體圖。半導體封裝件900包括基板110、饋入接點115(第9B圖)、接地層120、覆蓋體530、屏蔽層140及數個導電元件450。
覆蓋體530包括封裝體531及包覆體130。封裝體531具有一上表面531u，接地層120形成於上表面531u上，而包覆體130形成於接地層120上。導電元件450設置於接地層120且包覆體130包覆導電元件450。為了有效率地使用包覆體130，上表面531u之一部分未受到包覆體130的覆蓋，因而形成一凹槽531a。
請參照第9B圖，其繪示第9A圖中沿方向9B-9B’的剖視圖。封裝體531包覆晶片111、饋入接點115及導電走線117。凹槽531a讓包覆 體130的浪費減少，使包覆體130的成本降低。此外，凹槽531a可提供一空間去容置一可能會干涉到半導體封裝件900之其它元件的元件。此外，凹槽531a可提供一空間去容納一元件，例如是連接器、被動元件及一主動元件，以提升系統的設計彈性。
請參照第10A至10G圖，其繪示第1A圖之半導體封裝件100的製造過程圖。
如第10A圖所示，提供具有饋入接點115、導電走線117(第1C圖)及接地層120之基板110，其中晶片111設置於設置於基板110上。導電走線117連接饋入接點115及晶片111，且接地層120物理性地隔離且電性隔離於饋入接點115。
如第10B圖所示，形成包覆晶片111至少一部分及晶片111的包覆體130，其中包覆體130具有一上表面130u。
如第10C圖所示，採用適合的雷射或刀具，形成數個貫孔131露出接地層120及饋入接點115。
如第10D圖所示，可採用濺鍍、電鍍、印刷、打線技術(wire-bonding technology)、表面黏貼技術(surface mount technology,SMT)、焊料貼合(solder paste)或其它塗佈導電材料的技術，藉由填入導電材料於貫孔131，形成數個定義一波導腔體150r(繪示於第1A圖)的導電元件150。導電元件150接觸接地層120，且數個導電元件150之一導電元件151連接饋入接點115。另一實施例中，導電元件150可以是線路(wire)，其可於包覆體130形成前採用打線技術形成。
如第10E圖所示，可採用雷射或刀具，形成數個切割道P 經過包覆體130、導電元件150及基板110。切割道形成後，導電元件150之一側面150s、包覆體130之一側面130s與基板110之一側面110s從切割道P露出。此外，在切割道形成前，基板110可貼合於載板190。切割道P可經過部分載板190，以切斷整個基板110與包覆體130。
如第10F圖所示，貼合一貼片195於導電元件150露出之側面150s，藉以定義屏蔽層之開孔140a(繪示於第1A及1B圖)。
如第10G圖所示，形成屏蔽層140覆蓋上表面130u及包覆體130之側面130s未受到貼片195覆蓋的部分。移除貼片195後，形成如第1A圖所示之半導體封裝件100。屏蔽層140可採用電鍍/微影蝕刻製程(etching photolithographic processes)形成。
請參照第11圖，其繪示第2圖之半導體封裝件製造過程圖。貼片195形成例如是矩形、圓形、橢圓形或其它合適外形，其貼合於重疊於接地層120之包覆體130的上表面130u，以定義屏蔽層140之開孔140a，如第2圖所示。貼片195鄰近訊號發射開口150a設置。製造方法相似於半導體封裝件100，容此不再贅述。
請參照第12圖，其繪示第3圖之半導體封裝件製造過程圖。數個貼片195形成例如是矩形、圓形、橢圓形或其它合適外形，其貼合於重疊於接地層120之包覆體130的上表面130u，以定義屏蔽層140之數個開孔140a，如第3圖所示。製造方法相似於半導體封裝件100，容此不再贅述
請參照第13A至13C圖，其繪示第4B圖之半導體封裝件製造過程圖。
如第13A圖所示，可採用例如是表面黏貼技術，設置導電元件450(第4A圖)於接地層120。
如第13B圖所示，形成包覆體130包覆導電元件450、基板110與晶片111，其中包覆體130具有上表面130u。
如第13B圖所示，可採用例如是雷射或刀具，形成貫孔131，其中貫孔131從包覆體130之上表面130u延伸至饋入接點115。
如第13C圖所示，可採用電鍍，或塗佈焊料貼或其它合適導電材料，填入導電材料於數個貫孔131以形成數個導電元件151。導電元件151延伸至且電性連接於饋入接點115。製造過程相似於半導體封裝件100，容此不再贅述。
請參照第14A至14G圖，其繪示第5B圖之半導體封裝件製造過程圖。
如第14A圖所示，提供具有饋入接點115、導電走線117、接地元件113與上表面110u的基板110，其中接地元件113設置於基板110內且從基板110的上表面110u延伸到下表面110b。晶片111設置於基板110的上表面110u，而導電走線117連接晶片111與饋入接點115。
如第14B圖所示，形成封裝體531包覆基板110的至少一部分、晶片111、饋入接點115及其它導電走線117，其中封裝體531具有上表面130u。封裝體531的材料包含酚醛基樹脂(Novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其他適當之包覆劑。封裝體531可包括合適的粒子，例如是氧化矽粉末。可利用數種封裝技術形成封裝體531，例如是壓縮成型(compression molding)、液 態封裝型(liquid encapsulation)、注射成型(injection molding)或轉注成型(transfer molding)。
如第14B圖所示，可採用例如是適當的雷射或刀具，於封裝體531中形成饋入貫孔5311，其中饋入貫孔5311露出饋入接點115。此外，可採用例如是適當的雷射或刀具，形成接地貫孔5312及貫孔5313，其中接地貫孔5312露出基板110之接地元件113，而貫孔5313露出基板110之上表面110u。
如第14C圖所示，藉由填入導電材料於饋入貫孔5311而形成饋入元件551，其中導電材料例如是以電鍍，或塗佈(apply)焊料貼(solder paste)或其它導電材料形成。饋入元件551接觸饋入接點115。此外，藉由填入導電材料於接地貫孔5312而形成接地元件552，其中導電材料例如是以電鍍，或塗佈(apply)焊料貼(solder paste)或其它導電材料形成。接地元件552接觸接地元件113。此外，藉由填入導電材料於貫孔531而3形成導電元件553。
如第14C圖所示，可採用材料形成技術，形成接地層120於封裝體531之上表面531u，其中接地層120重疊於晶片111。材料形成技術例如是化學氣相沈積、無電鍍法(electroless plating)、電解電鍍(electrolytic plating)、印刷、旋塗、噴塗、濺鍍(sputtering)或真空沈積法(vacuum deposition)。
如第14D圖所示，形成包覆體130包覆接地層120，其中包覆體130具有上表面130u。包覆體130及封裝體531共同形成覆覆體530。
如第14D圖所示，可採用例如是適當的雷射或刀具，從包 覆體130的上表面130u，形成數個露出接地層120及饋入元件551的貫孔131。
如第14E圖所示，藉由填入導電材料於貫孔131而形成數個導電元件150，其中導電材料例如是以電鍍，或塗佈(apply)焊料貼(solder paste)或其它導電材料形成。導電元件150接觸接地層120與饋入元件551。
如第14F圖所示，可採用雷射或刀具，形成數個切割道P經過包覆體130、封裝體531、導電元件150及基板110。切割道P形成後，導電元件150之側面150s、包覆體130之側面130s、封裝體531之側面531s與基板110之側面110s從切割道P露出。此外，切割道P形成前，基板110可設置於載板190。切割道P可經過載板190之一部分，以完全切斷基板110、封裝體531與包覆體130。
如第14G圖所示，貼片195貼合於露出之側面150s，以定義屏蔽層140的開孔140a(繪示於第5B圖)。然後，形成屏蔽層140覆蓋上表面130u及包覆體130之側面130s未受到貼片195覆蓋的部分。移除貼片195後，形成第5B圖之半導體封裝件500。可採用電鍍/蝕刻微影製程(etching photolithographic processes)形成屏蔽層140。
請參照第15圖，其繪示第6圖之半導體封裝件的製造過程圖。貼片195貼合於重疊於接地層120之區域之包覆體130之上表面130u，以定義第6圖之屏蔽層140之開孔140a，其中貼片195例如是矩形或其它合適形狀。製造過程相似於半導體封裝件100，容此不再贅述。
請參照第16圖，其繪示第7圖之半導體封裝件的製造過程圖。貼片195貼合於重疊於接地層120之區域之包覆體130之上表面130u， 以定義第7圖之屏蔽層140之數個開孔140a，其中貼片195例如是矩形或其它合適形狀。製造過程相似於半導體封裝件100，容此不再贅述。
請參照第17A至17C圖，其繪示第8B圖之半導體封裝件的製造過程圖。
如17A圖所示，可採用例如是表面黏貼技術，設置第8B圖之導電元件450於接地層120上。饋入元件551物理性地分隔且電性隔離導電元件450，亦即，導電元件450未接觸饋入元件551。
如第17B圖所示，形成包覆體130包覆導電元件450，其中包覆體130具有上表面130u。可採用適當雷射或切割刀具，從包覆體130之上表面130u形成貫孔131露出饋入元件551。
如第17C圖所示，可採用例如是電鍍，藉由填入導電材料於貫孔131內而形成導電元件150，其中導電材料例如是以電鍍，或塗佈(apply)焊料貼(solder paste)或其它導電材料形成。導電元件150接觸饋入接點115，以電性連接饋入接點115。製造過程相似於半導體封裝件100，容此不再贅述。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體封裝件
110‧‧‧基板
130s‧‧‧側面
110u、130u‧‧‧上表面
111‧‧‧晶片
112‧‧‧被動元件
115‧‧‧饋入接點
117‧‧‧導電走線
120‧‧‧接地層
130‧‧‧包覆體
140‧‧‧屏蔽層
140a‧‧‧開孔
141‧‧‧側部
150、151‧‧‧導電元件
150a‧‧‧訊號發射開口
150r‧‧‧波導腔體
W‧‧‧寬度

Claims (20)

  1. 一種半導體封裝件，包括：一基板，包括一晶片；一接地層，設置於該基板上；一包覆體，覆蓋該晶片及該接地層；一導電孔，從該包覆體之一上表面延伸至該接地層；一屏蔽層，設置於該包覆體，且電性連接於該導電孔；以及至少一訊號發射開口，位於該包覆體且露出一定義一波導部(waveguide)的腔體。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中該接地層、該屏蔽層及一導電元件形成一天線。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中該導電孔係可用於傳輸一無線射頻訊號(radio frequency signal)。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中該至少一訊號發射開口包括一開口，該開口形成於該包覆體之一側面。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中該至少一訊號發射開口包括複數個開口，該些開口形成於該包覆體的該上表面。
  6. 如申請專利範圍第5項所述之半導體封裝件，其中該些開口實質上為矩形且排列成一線性形式。
  7. 如申請專利範圍第1項所述之半導體封裝件，更包括複數個導電元件，該些導電元件沿該波導的複數個側壁排列。
  8. 如申請專利範圍第1項所述之半導體封裝件，更包括一位於該腔體內的導電架，該導電架從該導電孔向外延伸至該至少一訊號發射開口。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中該波導呈一漏斗形。
  10. 一種半導體封裝件，包括：一基板，包括一晶片；一封裝體，包覆該晶片；一接地層，設置於該封裝體之一上表面；一包覆體，覆蓋該封裝體及該接地層；一導電孔，從該包覆體之一上表面延伸至該接地層；一屏蔽層，設置於該包覆體，且電性連接於該導電孔；以及至少一訊號發射開口，位於該包覆體且露出一定義一波導部 的腔體。
  11. 如申請專利範圍第10項所述之半導體封裝件，其中該導電孔用於傳輸一無線射頻訊號。
  12. 如申請專利範圍第10項所述之半導體封裝件，其中該接地層、該屏蔽層及一導電元件形成一天線。
  13. 如申請專利範圍第10項所述之半導體封裝件，其中該波導部與該晶片重疊。
  14. 如申請專利範圍第10項所述之半導體封裝件，其中該波導部呈一漏斗形。
  15. 一種半導體封裝件之製造方法，包括：提供一基板，該基板包括一晶片；形成一包覆體包覆該基板及該晶片，其中該包覆體具有一上表面；形成一導電元件以定義一波導腔體，其中該導電元件設置於一接地層；以及形成一屏蔽層於該包覆體之該上表面，其中該導電元件電性連接該屏蔽層且該屏蔽層具有一對應該波導腔體之開孔； 其中，該接地層、該屏蔽層與該導電元件形成一波導管天線。
  16. 如申請專利範圍第15項所述之製造方法，其中於形成該屏蔽層之步驟包括：依據該開孔的位置，設置一膠帶於該包覆體。
  17. 如申請專利範圍第15項所述之製造方法，其中於形成該包覆體之步驟包括：形成一封裝體包覆該晶片，其中該封裝體具有一上表面；形成該接地層於該封裝體的該上表面；形成該包覆體包覆該接地層。
  18. 如申請專利範圍第17項所述之製造方法，其中於形成該封裝體之步驟包括：形成一饋入貫孔於該封裝體。
  19. 如申請專利範圍第15項所述之製造方法，其中於形成該導電元件以定義該波導腔體之步驟包括：形成複數個該導電元件環繞該波導腔體。
  20. 如申請專利範圍第15項所述之製造方法，其中於形成該導電元件以定義該波導腔體之步驟包括：形成該導電元件於一貫 孔內，且更包括：形成一貫孔於該包覆體，其中該貫孔從該包覆體之該上表面延伸至該接地層。
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