CN104022106B - 具有波导管天线的半导体封装件及其制造方法 - Google Patents

具有波导管天线的半导体封装件及其制造方法 Download PDF

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CN104022106B
CN104022106B CN201310645953.9A CN201310645953A CN104022106B CN 104022106 B CN104022106 B CN 104022106B CN 201310645953 A CN201310645953 A CN 201310645953A CN 104022106 B CN104022106 B CN 104022106B
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cladding
semiconductor package
ground plane
package part
screen layer
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CN104022106A (zh
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颜瀚琦
陈士元
赖建伯
郑铭贤
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Advanced Semiconductor Engineering Inc
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Abstract

半导体封装件包括基板、接地层、封装体、屏蔽层及导电元件。基板包括芯片。封装体覆盖芯片及接地层，且封装体具有上表面。屏蔽层形成于封装体的上表面。导电元件环绕波导空腔，且延伸至接地层。接地层、屏蔽层与导电元件形成波导管天线。

Description

具有波导管天线的半导体封装件及其制造方法
技术领域
本发明是有关于一种半导体封装件及其制造方法，且特别是有关于一种具有波导管天线的半导体封装件及其制造方法。
背景技术
无线通信装置，例如是手机（cell phone），需要天线以传输及接收无线射频（radio frequency,RF）信号。传统上，一无线通信装置包括一天线及一通信模块（例如，一具有无线射频通信能力的半导体装置），其各设置于电路板的不同部分。在此情况下，天线及通信模块各别制作且设置于电路板上后再电性连接。因此，导致高制造成本且难以缩小装置尺寸。
此外，随着感测器、雷达、高数据率连结及聚焦功率（focused power），毫米波（millimeter-wave）频率的应用变得更为急切。短波长运作的优点包括减小其物理尺寸。然而，由于电性连接容易成为影响波长的一可观部分，使小尺寸天线的电路难以制造。
发明内容
根据本发明的一实施例，提出一种半导体封装件。半导体封装件包括一基板、一接地层、一包覆体、一导电孔、一屏蔽层及至少一信号发射开口。基板包括一芯片。接地层设置于基板上。包覆体覆盖芯片及接地层。导电孔从包覆体的一上表面延伸至接地层。屏蔽层设置于包覆体，且电性连接于导电孔。信号发射开口位于包覆体内且露出一定义一波导部的腔体。
根据本发明的一实施例，提出一种半导体封装件。半导体封装件包括一基板、一封装体、一接地层、一包覆体、一导电孔、一屏蔽层及至少一信号发射开口。基板包括一芯片。封装体包覆芯片。接地层设置于封装体的一上表面上。包覆体覆盖封装体及接地层。导电孔从包覆体的一上表面延伸至接地层。屏蔽层设置于包覆体且电性连接于导电孔。信号发射开口位于包覆体内且露出一定义一波导部的腔体。
根据本发明的另一实施例，提出一种半导体封装件的制造方法。制造方法包括以下步骤。提供一基板，基板包括一芯片；形成一包覆体包覆基板及芯片，其中包覆体具有一上表面；形成一导电元件以定义一波导腔体，其中导电元件设置于一接地层；形成一屏蔽层于包覆体的上表面，其中导电元件电性连接屏蔽层且屏蔽层具有一对应波导腔体的开孔；其中，接地层、屏蔽层与导电元件形成一波导管天线。
为了对本发明的上述及其他方面有更佳的了解，下文特举较佳实施例，并配合附图，作详细说明如下：
附图说明
图1A绘示依据本发明一实施例的半导体封装件的立体图。
图1B绘示图1A中沿方向1B-1B’的剖视图。
图1C绘示图1A的俯视图。
图2绘示依照本发明另一实施例的半导体封装件的立体图。
图3绘示依照本发明另一实施例的半导体封装件的立体图。
图4A绘示依照本发明另一实施例的半导体封装件的立体图。
图4B绘示图4A中沿方向4B-4B’的剖视图。
图5A绘示依照本发明另一实施例的半导体封装件的立体图。
图5B绘示图5A中沿方向5B-5B’的剖视图。
图6绘示依照本发明另一实施例的半导体封装件的立体图。
图7绘示依照本发明另一实施例的半导体封装件的立体图。
图8A绘示依照本发明另一实施例的半导体封装件的立体图。
图8B绘示图8A中沿方向8B-8B’的剖视图。
图9A绘示依照本发明另一实施例的半导体封装件的立体图。
图9B绘示图9B中沿方向9B-9B’的剖视图。
图10A至10G绘示图1A的半导体封装件的制造过程图。
图11绘示图2的半导体封装件制造过程图。
图12绘示图3的半导体封装件制造过程图。
图13A至13C绘示图4B的半导体封装件制造过程图。
图14A至14G绘示图5B的半导体封装件制造过程图。
图15绘示图6的半导体封装件的制造过程图。
图16绘示图7的半导体封装件的制造过程图。
图17A至17C绘示图8B的半导体封装件的制造过程图。
符号说明：
100、200、300、400、500、600、700、800、900：半导体封装件
110：基板
110s、130s、150s、531s：侧面
110b：底面
110u、130u、531u：上表面
111：芯片
112：被动元件
113：接地元件
115：馈入接点
117：导电走线
120：接地层
130：包覆体
131、5311、5312、5313：贯孔
140：屏蔽层
140a：开孔
141：侧部
150、151、152、450、553：导电元件
150a：信号发射开口
150r：波导腔体
190：载板
195：贴片
451：第一分支
452：第二分支
451e：第一端
452e：第二端
530：覆盖体
531：封装体
531a：凹槽
551：馈入元件
H：间距
P：切割道
S1：距离
W：宽度
具体实施方式
请参照图1A，其绘示依据本发明一实施例的半导体封装件100的立体图。半导体封装件100包括基板110、馈入接点115、接地层120、包覆体130、屏蔽层140及数个导电元件150。
基板110设有至少一芯片111及至少一被动元件112，其中芯片111例如是无线射频芯片。芯片111以朝下方位设置于基板110的上表面110u上，例如，芯片111的主动面朝向基板110。芯片111通过数个焊球电性连接于基板110。这样的结构称为覆晶（flip chip）。另一例中，芯片111以朝上方位设置于基板110上，例如，芯片111的主动面背向基板110。在此设计下，芯片111通过数个焊线电性连接于基板110。被动元件112可以是电阻、电感、电容或其不具主动电路的组合。此外，基板110例如是多层有机基板或一陶瓷基板。馈入接点115设置于基板110且电性连接于芯片111。
包覆体130包覆接地层120及芯片111，其中包覆体130具有上表面130u。包覆体130的材料包含酚醛基树脂（Novolac-based resin）、环氧基树脂（epoxy-based resin）、硅基树脂（silicone-based resin）或其他适当的包覆剂。较佳地，材料是低散热系数（lowdissipation factor），其中材料的耗损因数（loss tangent）实质上低于约0.1。
屏蔽层140形成于包覆体130的上表面130u、包覆体130的侧面130s与基板110的侧面110s。屏蔽层140具有开孔140a，其形成于屏蔽层140的侧部141而露出一些导电元件150。屏蔽层140可包含铝、铜、铬、锡、金、银、镍、不锈钢或任何其它合适材料或合金。此外，屏蔽层140可以是多层结构或单层结构。
被包覆体130包覆的导电元件150设置于接地层120且电性连接于屏蔽层140。因此，导电元件150、接地层120及屏蔽层140共同形成一波导管天线。导电元件150能引导RF精确地至所需部位，并作为一高通滤波器（High Pass Filter）。波导腔体150r由数个导电元件150及一信号发射开口150a所定义，信号发射开口150a形成于包覆体130的侧面130s且对应于数个导电元件150。RF信号于波导腔体150r内受到引导，然后从信号发射开口150a发射出半导体封装件100外。
如图1A所示，信号发射开口150a的宽度W决定截止频率（cutoff frequency）fc。截止频率是所有低频被数个导电元件150减弱的频率，且所有高频传播于数个导电元件150内。截止频率的公式如下式(1)。
如上式，c是于波导内的光速。
请参照图1B，其绘示图1A中沿方向1B-1B’的剖视图。接地层120形成于基板110的上表面110u且电性连接于一形成于基板110内的接地元件113。接地元件113电性连接于一印刷电路板（PCB）或一基板的一接地端（未绘示），使接地层120通过接地元件113电性连接于接地端。本实施例中，接地元件113是一导电孔（conductive via），其从上表面110u延伸至底面110b。另一实施例中，接地元件113是一图案化导电层。
如图1B所示，包覆体130具有数个贯孔或开口131，如封胶贯孔（throughmold via,TMV），其从包覆体130的上表面130u延伸至接地层120。导电元件150是以导电材料填入包覆体130的开口131而形成，导电材料如铜、铝、锡、镍、金或银。因此，导电元件可电性连接屏蔽层140与接地层120。导电元件150包括导电元件151，其连接馈入接点115与屏蔽层140。其它导电元件150连接于接地层120。由于导电元件151用于传输RF信号，其它导电元件150的一个可邻近导电元件151设置，而减少电磁干扰（EMI）。
请参照图1C，其绘示图1A的俯视图。半导体封装件100更包括一导电走线117，其连接芯片111与馈入接点115。例如，导电走线117用于传输来自于导电元件151的RF信号至芯片111，例如是基频芯片（baseband chip）。因此，一些导电元件150邻近芯片111及导电走线117设置，以避免导电走线117受到电磁干扰。此外，导电元件150包括二周边导电元件152从包覆体130及信号发射开口150a露出。另一例中，所有的导电元件150可被包覆体130覆盖。
如图1C所示，相邻二导电元件150的间距H从信号发射开口150a往馈入接点115方向渐缩，使数个导电元件150排列成一漏斗型。相邻二导电元件150的距离S1及相邻二导电元件150的间距H可由发射的无线信号的一等效波长决定。
请参照图2，其绘示依照本发明另一实施例的半导体封装件200的立体图。半导体封装件200包括基板110、馈入接点115、接地层120、包覆体130、屏蔽层140及数个导电元件150。
屏蔽层140具有开孔140a，其重迭于接地层120的一部分，使一RF信号从开孔140a往上发射。开孔140a邻近周边导电元件152设置。然而，这样的方位非用以限制本发明实施例。开孔140a的外形是一矩形。另一例中，开孔140a的外形可以是圆形、椭圆形或其它形式的多边形。
请参照图3，其绘示依照本发明另一实施例的半导体封装件300的立体图。半导体封装件300包括基板110、馈入接点115、接地层120、包覆体130、屏蔽层140及数个导电元件150。
屏蔽层140具有数个开孔140a，其重迭于接地层120的一部分，使一RF信号从开孔140a往上发射。至少一开孔140a是形成于屏蔽层140的矩形开口。另一例中，至少一开孔140a是一圆形开口、椭圆形开口或其它形式的多边形开口。本例中，数个开孔140a排列成线形。另一例中，数个开孔140a排列成矩阵形。
请参照图4A，其绘示依照本发明另一实施例的半导体封装件400的立体图。半导体封装件400包括基板110、馈入接点115、接地层120、包覆体130、屏蔽层140及一导电元件450。
导电元件450是一导电架，且导电元件450、接地层120与屏蔽层140共同形成一波导管天线。波导腔体150r及信号发射开口150a由导电元件450定义。在此情况下，一RF信号于波导腔体150r受到引导，然后从信号发射开口150a发射至半导体封装件400外。
如图4A所示，导电元件450包括第一分支451及第二分支452。第一分支451与第二分支452彼此分离，且波导腔体150r定义于第一分支451与第二分支452之间。第一分支451具有一第一端451e，第二分支452具有一第二端452e。屏蔽层140具有一开孔140a，其形成于屏蔽层140的侧部141。第一分支451及第二分支452从包覆体130及开孔140a露出。第一分支451与第二分支452的间距H从相对二第一分支451与第二分支452往馈入接点115方向渐缩，使导电元件450排列成漏斗型。一无线信号于波导腔体150r内受到引导，然后从信号发射开口150a发射至半导体封装件400外，其中信号发射开口150a从开孔140a露出。
请参照图4B，其绘示图4A中沿方向4B-4B’的剖视图。导电元件450设置于接地层120且通过接地层120电性连接于接地元件113。因此，导电元件450环绕馈入接点115及走线117，可避免馈入接点115及走线117受到电磁干扰。
请参照图5A，其绘示依照本发明另一实施例的半导体封装件500的立体图。半导体封装件500包括基板110、馈入接点115、接地层120、覆盖体530、屏蔽层140及数个导电元件150。
如图5A所示，芯片111及至少一被动元件112设置于基板110上，其中，芯片111例如是基频芯片及RF芯片。覆盖体530包括封装体531及包覆体130。封装体531覆盖芯片111、馈入接点115及走线117且具有一上表面531u。接地层120形成于封装体531的上表面531u，且包覆体130压在接地层120上。数个导电元件150形成于包覆体130。因此，芯片111及导电元件150重迭，如垂直方位所示。此外，接地层120的至少一部分与芯片111重迭，以避免芯片111受到电磁干扰。
请参照图5B，其绘示图5A中沿方向5B-5B’的剖视图。半导体封装件500包括基板110、馈入接点115、接地层120、包覆体130、屏蔽层140及一导电元件450。封装体531具有一馈入贯孔5311及一馈入元件551，其中馈入贯孔5311露出馈入接点115，而馈入元件551经由导电材料填入馈入贯孔5311而形成。馈入元件551被封装体531包覆，且电性连接于馈入接点115。包覆体130具有一贯孔131露出馈入元件551，且导电元件150经由填入导电材料于贯孔131而形成并电性连接于馈入元件551。
如图5B所示，封装体531具有一接地贯孔5312及一接地元件552，其中接地贯孔5312露出接地元件113，而接地元件552经由导电材料填入接地贯孔5312而形成并电性连接于接地元件113。包覆体130具有一露出接地元件552的贯孔131，且导电元件150经由导电材料填入贯孔131而形成并电性连接于接地元件552。
如图5B所示，包覆体130具有数个贯孔131及其它数个导电元件150，其中贯孔131露出接地层130的数个贯孔131，而其它导电元件150经由导电元件填入贯孔131而形成，并电性连接于接地层120及屏蔽层140。
请参照图6，其绘示依照本发明另一实施例的半导体封装件600的立体图。半导体封装件600包括基板110、馈入接点115、接地层120、覆盖体530、屏蔽层140及数个导电元件150。
屏蔽层140具有开孔140a，开孔140a与接地层120的一区域重迭，可使无线射频信号通过开孔140a朝上发射。本实施例中，开孔140a是屏蔽层140的一矩形开口。另一实施例中，开孔140a可形成圆形、椭圆形或不同的多边形；然而，本发明实施例不限于此。
请参照图7，其绘示依照本发明另一实施例的半导体封装件700的立体图。半导体封装件700包括基板110、馈入接点115、接地层120、覆盖体530、屏蔽层140及数个导电元件150。
屏蔽层140具有开孔140a，开孔140a与接地层120的一区域重迭，可使无线射频信号通过开孔140a朝上发射。此些开孔140a的至少一者是屏蔽层140的矩形开口。另一实施例中，此些开孔140a的至少一者可形成圆形、椭圆形或不同的多边形。本实施例中，数个开孔140a排列成直线。另一例中，数个开孔140a排列成矩阵形。
请参照图8A，其绘示依照本发明另一实施例的半导体封装件800的立体图。半导体封装件800包括基板110、馈入接点115(图8B)、接地层120、覆盖体530、屏蔽层140及数个导电元件450。
导电元件450是一导电架，且导电元件450、导电元件450与接地层120共同形成一波长天线。波导腔体150r及信号发射开口150a由导电元件450定义。无线射频信号于波导腔体150r内受到引导，然后经由信号发射开口150a从半导体封装件800发射。
请参照图8B，其绘示图8A中沿方向8B-8B’的剖视图。覆盖体530包括封装体531及包覆体130。导电元件450设置于包覆芯片111、馈入接点115及导电走线117的封装体531上方。接地层120形成于封装体531的上表面531u，且包覆体130形成于接地层120上。
如图8B所示，封装体531具有馈入贯孔5311及馈入元件551，其中馈入贯孔5311露出馈入接点115，而馈入元件551经由导电材料填入馈入贯孔5311而形成且电性连接于馈入接点115。包覆体130具有露出馈入元件551的贯孔131，而导电元件150经由导电材料填入贯孔131而形成且通过馈入元件551电性连接于馈入接点115。
封装体531具有一接地贯孔5312及一接地元件552。接地贯孔5312露出接地元件113，而接地元件552经由填入接地贯孔5312而形成且电性连接于接地层120。在此设计下，接地层120通过被封装体531包覆的接地元件552电性连接接地元件113。
封装体531具有一贯孔5313及一导电元件553。贯孔5313露出第一基板110的上表面110u，而导电元件553经由导电材料填入贯孔5313而形成，其中导电材料例如是以电镀，或涂布（apply）焊料贴（solder paste）或其它导电材料形成。此外，数个导电元件553可邻近馈入元件551及馈入接点115设置，以避免馈入元件551及馈入接点115受到电磁干扰。
请参照图9A，其绘示依照本发明另一实施例的半导体封装件900的立体图。半导体封装件900包括基板110、馈入接点115(图9B)、接地层120、覆盖体530、屏蔽层140及数个导电元件450。
覆盖体530包括封装体531及包覆体130。封装体531具有一上表面531u，接地层120形成于上表面531u上，而包覆体130形成于接地层120上。导电元件450设置于接地层120且包覆体130包覆导电元件450。为了有效率地使用包覆体130，上表面531u的一部分未受到包覆体130的覆盖，因而形成一凹槽531a。
请参照图9B，其绘示图9A中沿方向9B-9B’的剖视图。封装体531包覆芯片111、馈入接点115及导电走线117。凹槽531a让包覆体130的浪费减少，使包覆体130的成本降低。此外，凹槽531a可提供一空间去容置一可能会干涉到半导体封装件900的其它元件的元件。此外，凹槽531a可提供一空间去容纳一元件，例如是连接器、被动元件及一主动元件，以提升系统的设计弹性。
请参照图10A至10G，其绘示图1A的半导体封装件100的制造过程图。
如图10A所示，提供具有馈入接点115、导电走线117(图1C)及接地层120的基板110，其中芯片111设置于设置于基板110上。导电走线117连接馈入接点115及芯片111，且接地层120物理性地隔离且电性隔离于馈入接点115。
如图10B所示，形成包覆芯片111至少一部分及芯片111的包覆体130，其中包覆体130具有一上表面130u。
如图10C所示，采用适合的激光或刀具，形成数个贯孔131露出接地层120及馈入接点115。
如图10D所示，可采用溅镀、电镀、印刷、打线技术(wire-bonding technology)、表面黏贴技术(surface mount technology,SMT)、焊料贴合(solder paste)或其它涂布导电材料的技术，经由填入导电材料于贯孔131，形成数个定义一波导腔体150r(绘示于图1A)的导电元件150。导电元件150接触接地层120，且数个导电元件150的一导电元件151连接馈入接点115。另一实施例中，导电元件150可以是线路(wire)，其可于包覆体130形成前采用打线技术形成。
如图10E所示，可采用激光或刀具，形成数个切割道P经过包覆体130、导电元件150及基板110。切割道形成后，导电元件150的一侧面150s、包覆体130的一侧面130s与基板110的一侧面110s从切割道P露出。此外，在切割道形成前，基板110可贴合于载板190。切割道P可经过部分载板190，以切断整个基板110与包覆体130。
如图10F所示，贴合一贴片195于导电元件150露出的侧面150s，藉以定义屏蔽层的开孔140a(绘示于图1A及1B)。
如图10G所示，形成屏蔽层140覆盖上表面130u及包覆体130的侧面130s未受到贴片195覆盖的部分。移除贴片195后，形成如图1A所示的半导体封装件100。屏蔽层140可采用电镀/微影蚀刻工艺（etching photolithographic processes）形成。
请参照图11，其绘示图2的半导体封装件制造过程图。贴片195形成例如是矩形、圆形、椭圆形或其它合适外形，其贴合于重迭于接地层120的包覆体130的上表面130u，以定义屏蔽层140的开孔140a，如图2所示。贴片195邻近信号发射开口150a设置。制造方法相似于半导体封装件100，容此不再赘述。
请参照图12，其绘示图3的半导体封装件制造过程图。数个贴片195形成例如是矩形、圆形、椭圆形或其它合适外形，其贴合于重迭于接地层120的包覆体130的上表面130u，以定义屏蔽层140的数个开孔140a，如图3所示。制造方法相似于半导体封装件100，容此不再赘述
请参照图13A至13C，其绘示图4B的半导体封装件制造过程图。
如图13A所示，可采用例如是表面黏贴技术，设置导电元件450（图4A）于接地层120。
如图13B所示，形成包覆体130包覆导电元件450、基板110与芯片111，其中包覆体130具有上表面130u。
如图13B所示，可采用例如是激光或刀具，形成贯孔131，其中贯孔131从包覆体130的上表面130u延伸至馈入接点115。
如图13C所示，可采用电镀，或涂布焊料贴或其它合适导电材料，填入导电材料于数个贯孔131以形成数个导电元件151。导电元件151延伸至且电性连接于馈入接点115。制造过程相似于半导体封装件100，容此不再赘述。
请参照图14A至14G，其绘示图5B的半导体封装件制造过程图。
如图14A所示，提供具有馈入接点115、导电走线117、接地元件113与上表面110u的基板110，其中接地元件113设置于基板110内且从基板110的上表面110u延伸到下表面110b。芯片111设置于基板110的上表面110u，而导电走线117连接芯片111与馈入接点115。
如图14B所示，形成封装体531包覆基板110的至少一部分、芯片111、馈入接点115及其它导电走线117，其中封装体531具有上表面130u。封装体531的材料包含酚醛基树脂（Novolac-based resin）、环氧基树脂（epoxy-based resin）、硅基树脂（silicone-basedresin）或其他适当的包覆剂。封装体531可包括合适的粒子，例如是氧化硅粉末。可利用数种封装技术形成封装体531，例如是压缩成型（compression molding）、液态封装型（liquidencapsulation）、注射成型（injection molding）或转注成型（transfer molding）。
如图14B所示，可采用例如是适当的激光或刀具，于封装体531中形成馈入贯孔5311，其中馈入贯孔5311露出馈入接点115。此外，可采用例如是适当的激光或刀具，形成接地贯孔5312及贯孔5313，其中接地贯孔5312露出基板110的接地元件113，而贯孔5313露出基板110的上表面110u。
如图14C所示，经由填入导电材料于馈入贯孔5311而形成馈入元件551，其中导电材料例如是以电镀，或涂布（apply）焊料贴（solder paste）或其它导电材料形成。馈入元件551接触馈入接点115。此外，经由填入导电材料于接地贯孔5312而形成接地元件552，其中导电材料例如是以电镀，或涂布（apply）焊料贴（solder paste）或其它导电材料形成。接地元件552接触接地元件113。此外，经由填入导电材料于贯孔531而3形成导电元件553。
如图14C所示，可采用材料形成技术，形成接地层120于封装体531的上表面531u，其中接地层120重迭于芯片111。材料形成技术例如是化学气相沉积、无电镀法（electroless plating）、电解电镀（electrolytic plating）、印刷、旋涂、喷涂、溅镀（sputtering）或真空沉积法（vacuum deposition）。
如图14D所示，形成包覆体130包覆接地层120，其中包覆体130具有上表面130u。包覆体130及封装体531共同形成覆覆体530。
如图14D所示，可采用例如是适当的激光或刀具，从包覆体130的上表面130u，形成数个露出接地层120及馈入元件551的贯孔131。
如图14E所示，经由填入导电材料于贯孔131而形成数个导电元件150，其中导电材料例如是以电镀，或涂布（apply）焊料贴（solder paste）或其它导电材料形成。导电元件150接触接地层120与馈入元件551。
如图14F所示，可采用激光或刀具，形成数个切割道P经过包覆体130、封装体531、导电元件150及基板110。切割道P形成后，导电元件150的侧面150s、包覆体130的侧面130s、封装体531的侧面531s与基板110的侧面110s从切割道P露出。此外，切割道P形成前，基板110可设置于载板190。切割道P可经过载板190的一部分，以完全切断基板110、封装体531与包覆体130。
如图14G所示，贴片195贴合于露出的侧面150s，以定义屏蔽层140的开孔140a（绘示于图5B）。然后，形成屏蔽层140覆盖上表面130u及包覆体130的侧面130s未受到贴片195覆盖的部分。移除贴片195后，形成图5B的半导体封装件500。可采用电镀/蚀刻微影工艺（etching photolithographic processes）形成屏蔽层140。
请参照图15，其绘示图6的半导体封装件的制造过程图。贴片195贴合于重迭于接地层120的区域的包覆体130的上表面130u，以定义图6的屏蔽层140的开孔140a，其中贴片195例如是矩形或其它合适形状。制造过程相似于半导体封装件100，容此不再赘述。
请参照图16，其绘示图7的半导体封装件的制造过程图。贴片195贴合于重迭于接地层120的区域的包覆体130的上表面130u，以定义图7的屏蔽层140的数个开孔140a，其中贴片195例如是矩形或其它合适形状。制造过程相似于半导体封装件100，容此不再赘述。
请参照图17A至17C，其绘示图8B的半导体封装件的制造过程图。
如图17A所示，可采用例如是表面黏贴技术，设置图8B的导电元件450于接地层120上。馈入元件551物理性地分隔且电性隔离导电元件450，亦即，导电元件450未接触馈入元件551。
如图17B所示，形成包覆体130包覆导电元件450，其中包覆体130具有上表面130u。可采用适当激光或切割刀具，从包覆体130的上表面130u形成贯孔131露出馈入元件551。
如图17C所示，可采用例如是电镀，经由填入导电材料于贯孔131内而形成导电元件150，其中导电材料例如是以电镀，或涂布（apply）焊料贴（solder paste）或其它导电材料形成。导电元件150接触馈入接点115，以电性连接馈入接点115。制造过程相似于半导体封装件100，容此不再赘述。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。

Claims (20)

1.一种半导体封装件，其特征在于，包括：
一基板，包括一芯片；
一接地层，设置于该基板上；
一包覆体，覆盖该芯片及该接地层；
一导电孔，从该包覆体的一上表面延伸至该接地层；
一屏蔽层，设置于该包覆体，且电性连接于该导电孔；以及
至少一信号发射开口，位于该包覆体且露出一定义一波导部的腔体。
2.如权利要求1所述的半导体封装件，其特征在于，该接地层、该屏蔽层及一导电元件形成一天线。
3.如权利要求1所述的半导体封装件，其特征在于，该导电孔是可用于传输一无线射频信号。
4.如权利要求1所述的半导体封装件，其特征在于，该至少一信号发射开口包括一开口，该开口形成于该包覆体的一侧面。
5.如权利要求1所述的半导体封装件，其特征在于，该至少一信号发射开口包括数个开口，该些开口形成于该包覆体的该上表面。
6.如权利要求5所述的半导体封装件，其特征在于，该些开口实质上为矩形且排列成一线性形式。
7.如权利要求1所述的半导体封装件，其特征在于，更包括数个导电元件，该些导电元件沿该波导的数个侧壁排列。
8.如权利要求1所述的半导体封装件，其特征在于，更包括一位于该腔体内的导电架，该导电架从该导电孔向外延伸至该至少一信号发射开口。
9.如权利要求1所述的半导体封装件，其特征在于，该波导呈一漏斗形。
10.一种半导体封装件，其特征在于，包括：
一基板，包括一芯片；
一封装体，包覆该芯片；
一接地层，设置于该封装体的一上表面；
一包覆体，覆盖该封装体及该接地层；
一导电孔，从该包覆体的一上表面延伸至该接地层；
一屏蔽层，设置于该包覆体，且电性连接于该导电孔；以及
至少一信号发射开口，位于该包覆体且露出一定义一波导部的腔体。
11.如权利要求10所述的半导体封装件，其特征在于，该导电孔用于传输一无线射频信号。
12.如权利要求10所述的半导体封装件，其特征在于，该接地层、该屏蔽层及一导电元件形成一天线。
13.如权利要求10所述的半导体封装件，其特征在于，该波导部与该芯片重迭。
14.如权利要求10所述的半导体封装件，其特征在于，该波导部呈一漏斗形。
15.一种半导体封装件的制造方法，其特征在于，包括：
提供一基板，该基板包括一芯片；
形成一包覆体包覆该基板及该芯片，其中该包覆体具有一上表面；
形成一导电元件以定义一波导腔体，其中该导电元件设置于一接地层；以及
形成一屏蔽层于该包覆体的该上表面，其中该导电元件电性连接该屏蔽层且该屏蔽层具有一对应该波导腔体的开孔；
其中，该接地层、该屏蔽层与该导电元件形成一波导管天线。
16.如权利要求15所述的制造方法，其特征在于，形成该屏蔽层的步骤包括：
依据该开孔的位置，设置一贴片于该包覆体。
17.如权利要求15所述的制造方法，其特征在于，形成该包覆体的步骤包括：
形成一封装体包覆该芯片，其中该封装体具有一上表面；
形成该接地层于该封装体的该上表面；
形成该包覆体包覆该接地层。
18.如权利要求17所述的制造方法，其特征在于，形成该封装体的步骤包括：
形成一馈入贯孔于该封装体。
19.如权利要求15所述的制造方法，其特征在于，形成该导电元件以定义该波导腔体的步骤包括：
形成数个该导电元件环绕该波导腔体。
20.如权利要求15所述的制造方法，其特征在于，形成该导电元件以定义该波导腔体的步骤包括：形成该导电元件于一贯孔内，且更包括：
形成一贯孔于该包覆体，其中该贯孔从该包覆体的该上表面延伸至该接地层。
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