CN107068657B - 包含天线层的半导体封装件及其制造方法 - Google Patents
包含天线层的半导体封装件及其制造方法 Download PDFInfo
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Abstract
一种包含天线层的半导体封装件及其制造方法。半导体封装件包括基板、半导体芯片、封装体及天线层。半导体芯片设于基板。封装体包覆半导体芯片且包括上表面。天线层形成于封装体的上表面,天线层包括一馈入层与一辐射层,且辐射层透过一第一波导槽与馈入层隔离。
Description
本申请是2014年3月7日申请的,申请号为201410082789.X,发明名称为“包含天线层的半导体封装件及其制造方法”的中国发明专利申请的分案申请。
技术领域
本发明是有关于一种半导体封装件及其制造方法,且特别是有关于一种具有天线层的半导体封装件及其制造方法。
背景技术
无线通讯装置,例如是手机,一般包括天线以传输或接收无线射频(radiofrequency,RF)信号。传统上,无线通讯装置包括天线及通讯模块,各设于电路板的不同部位。在传统的实施例中,天线及通讯模块分别制造,并于设置在电路板后再电性连接彼此。如此将导致二个元件的制造成本,此外,也难以降低装置尺寸而达到产品的小型化。此外,天线与通讯模块之间的RF信号传输路径较长,而降低天线与通讯模块之间的信号传输品质。
发明内容
根据本发明一方面,提出一种半导体封装件。一实施例中,半导体封装件包括一基板、一半导体芯片、一封装体及一天线层。半导体芯片设于基板。封装体包覆半导体芯片且包括一上表面。天线层形成于封装体的上表面,天线层包括一馈入层与一辐射层,且辐射层透过一第一波导槽与馈入层隔离。
根据本发明另一方面,提出一种半导体封装件。一实施例中,半导体封装件包括一基板、一半导体芯片、一第一封装体、一第二封装体及一天线层。半导体芯片设于基板。第一封装体包覆半导体芯片。第二封装体覆盖第一封装体。天线层,形成于第二封装体上,天线层包括一馈入层与一辐射层,且辐射层透过一第一波导槽与馈入层隔离。
根据本发明另一方面,提出一种半导体封装件的制造方法。一实施例中,制造方法以下步骤。设置一半导体芯片于一基板;形成一封装体包覆半导体芯片;形成一天线层于半导体封装件的一上表面,其中天线层电性连接于半导体芯片;以及,形成二彼此连接的天线槽组于天线层,其中各天线槽组包括一馈入层与一辐射层,且辐射层透过一第一波导槽与馈入层隔离。
为了对本发明的上述及其他方面有更佳的了解,下文特举较佳实施例,并配合所附附图,作详细说明如下:
附图说明
图1A绘示依照本发明一实施例的半导体封装件的剖视图。
图1B绘示图1A的俯视图。
图2A绘示依照本发明另一实施例的半导体封装件的俯视图。
图2B绘示图2A中沿方向2B-2B’的剖视图。
图3绘示另一实施例的天线层的俯视图。
图4绘示图3的半导体封装件的天线层的E平面的场形图。
图5A绘示依照本发明另一实施例的半导体封装件的剖视图。
图5B绘示图5A的俯视图。
图6绘示依照本发明另一实施例的俯视图。
图7绘示依照本发明另一实施例的半导体封装件的俯视图。
图8绘示依照本发明另一实施例的半导体封装件的俯视图。
图9绘示依照本发明另一实施例的半导体封装件的俯视图。
图10绘示依照本发明另一实施例的半导体封装件的俯视图。
图11绘示依照本发明另一实施例的半导体封装件的俯视图。
图12A至12K绘示图1A的半导体封装件的制造过程图。
图13A至13F绘示图9的半导体封装件的制造过程图。
具体实施方式
整合天线部及无线通讯装置的通讯模块半导体封装件,具有例如是缩小封装件尺寸及减少无线射频(RF)信号传输路径的优点。以下实施例描述本发明揭露的半导体封装件。
图1A绘示依照本发明一实施例的半导体封装件100的剖视图。半导体封装件100包括基板110、半导体芯片120、封装体130、屏蔽层140、馈入元件150、数个导电柱160a、160b及天线层170。
基板110例如是多层有机基板或陶瓷基板。基板110包括相对的上表面110u与下表面110b及一邻设于基板110的边缘的侧面110s。侧面110s延伸于上表面110u与下表面110b且定义基板110的边界。基板110包括接地部111。如图1A所示,至少部分的接地部111从基板110的下表面110b往基板110的上表面110u方向延伸。第一种实施例中,整个接地部111从基板110的下表面110b延伸至基板110的上表面110u,或延伸超过上表面110u。第二种实施例中,部分接地部111从基板110的上表面110u延伸至基板110的下表面110b。
半导体芯片120及无源元件125设于基板110的上表面110u且电性连接于基板110。设于基板110的半导体芯片120例如,可包括一基频芯片。无源元件125例如是电阻、电感或电容。
封装体130包覆半导体芯片120。封装体130包括第一封装体131及第二封装体132,其中第一封装体131包覆半导体芯片120,且第二封装体132覆盖屏蔽层140。一实施例中,封装体130可包括酚醛基树脂(Novolac-based resin)、环氧基树脂(epoxy-based resin)、硅基树脂(silicone-based resin)或其他适当的包覆剂。封装体130也可包括适当的填充剂,例如是粉状的二氧化硅。可利用数种封装技术形成封装体130,例如是压缩成型(compression molding)、注射成型(injection molding)或转注成型(transfermolding)。
封装体130包括沿第一封装体131的边缘、第二封装体132及屏蔽层140延伸的侧面130s。
屏蔽层140形成于第一封装体131的上表面131u且被第二封装体132覆盖。屏蔽层140可以是单层或多层材料。一实施例中,屏蔽层140是三层结构,其中间层是铜层,而其它层是不锈钢层。另一实施例中,屏蔽层140是双层结构,其一层是铜层,而另一层是不锈钢层。
屏蔽层140包括馈入部141及屏蔽部142,其中馈入部141电性连接于馈入元件150,而屏蔽部142通过天线层170电性连接于接地部111。屏蔽部142与馈入部141隔离。屏蔽层140可以是铝、铜、铬、锡、金、银、镍、不锈钢或任何合适金属或合金。
馈入元件150包括第一馈入部151及第二馈入部152。第一馈入部151延伸穿过第一封装体131且电性连接于屏蔽层140。数条走线112形成于基板110的上表面110u,且电性连接第一馈入部151与半导体芯片120。如此,馈入元件150电性连接于半导体芯片120。第二馈入部152延伸穿过第二封装体132且电性连接于屏蔽层140。
一个或多个贯孔130h,例如是封胶穿孔(through molding via),其从天线层170延伸至屏蔽层140。导电柱160a藉由填入导电材料于封装体130的贯孔130h而形成。
一个或多个贯孔130j,例如是封胶穿孔,其从屏蔽层140延伸至走线112。导电柱160b藉由填入导电材料于封装体130的贯孔130j而形成。
天线层170形成于封装体130的上表面130u及侧面130s。天线层170包括馈入层172及辐射层173。辐射层173沿封装体130的侧面130s电性连接于接地部111。馈入元件150的第二馈入部152连接馈入层172与屏蔽层140的馈入部141。
屏蔽层140及天线层170共同形成一全覆盖屏蔽层(conformal shielding),以保护半导体芯片120避免过多的电磁干扰(EMI)不当地影响半导体封装件100的操作。
导电柱160a通过天线层170的辐射层173电性连接于接地部111。导电柱160b通过屏蔽层140电性连接于导电柱160a。因此,环绕馈入元件150的导电柱160a及160b可保护馈入元件150所传输的馈入信号免受电磁干扰。
图1B绘示图1A的俯视图。天线层170包括侧面170s,且更包括彼此连接的二天线槽组171及171a,其形成一槽孔天线(slot antenna)。二天线槽组171及171a对称,且为形成于天线层170的数条切痕(cut)或数个凹部(indentation)。馈入元件150位于天线槽组171与171a之间,以传输馈入信号至槽孔天线。
天线槽组171包括一波导槽1711及一辐射槽组1712。波导槽1711用以传输毫米波(millimeter wavelength,mmWave)信号。辐射槽组1712用以辐射毫米波信号。波导槽1711沿第一方向P1延伸,而辐射槽组1712沿第二方向P2延伸。辐射槽组1712连接于波导槽1711。辐射槽组1712绘示成包括至少二辐射槽1713,然此非用以限制本发明实施例。另一实施例中,辐射槽组1712的辐射槽1713的数量可以是一个或超过二个。图1B的实施例中,辐射槽1713未延伸至天线层170的侧面170s,然此非用以限制本发明实施例。另一实施例中,辐射槽1713可延伸至天线层170的侧面170s。
如图1B所示,辐射槽1713垂直地与波导槽1711连接。另一实施例中,为了辐射更多毫米波信号的能量,辐射槽1713可倾斜地与波导槽1711连接,以延长辐射槽1713长度。波导槽1711愈窄,毫米波信号的传输愈强。波导槽1711的宽度较佳地介于50至700微米。另一实施例中,波导槽1711约50微米宽。
辐射槽1713愈宽,毫米波信号的辐射愈强。如此,为了提升毫米波信号的辐射,辐射槽1713可设计得比波导槽1711更宽。辐射槽1713的宽度较佳地介于50至700微米。另一实施例中,辐射槽1713约100微米宽。
天线槽组171a近似天线槽组171的镜射影像(mirror image),因此,上述实施例的波导槽1711、辐射槽1712与辐射槽1713相似于波导槽1711a、辐射槽组1712a与辐射槽1713a。
位于二辐射槽1713a之间的波导槽1711a的部分,其长度L1决定毫米波信号的波长,而辐射槽1713a的长度L2约毫米波信号波长的一半。亦即,长度L2可接近长度L1的一半。
图1A的馈入层172可做为共平面波导(coplanar waveguide,CPW),以传输毫米波至辐射槽组1712与1712a。
图1A的辐射层173通过波导槽1711及1711a与馈入层172隔离,以避免不当地影响馈入元件150的馈入信号。
图2A绘示依照本发明另一实施例的半导体封装件200的俯视图。天线层170包括二天线槽组,天线槽组171与近似其的镜射影像通过阻抗匹配槽174连接。镜射影像的天线槽组的架构相似于天线槽组171的详细描述。
天线槽组171包括第一波导槽1711、第一辐射槽组1712、第二波导槽1711’、第二辐射槽组1712’与第三波导槽1711”。
第一波导槽1711沿第一方向P1延伸。第一辐射槽组1712连接于第一波导槽1711,且沿第二方向P2延伸。一实施例中,第一辐射槽组1712包括三个辐射槽1713。另一实施例中,第一辐射槽组1712的辐射槽1713的数量可以是单个、二个或超过三个。
第二波导槽1711’连接于第一辐射槽组1712,且沿第一方向P1延伸。
形成于天线层170的网格包含区域171m,网格是由第一波导槽1711、辐射槽1713与第二波导槽1711’定义。网格的数个长侧较佳地由第一波导槽1711或第二波导槽1711’形成。网格的数个短侧较佳地由辐射槽1713形成。
第二辐射槽组1712’连接于第二波导槽1711’,且沿第二方向P2延伸。第二辐射槽组1712’包括数个辐射槽1713’。第二辐射槽组1712’的辐射槽1713’的数量多于第一辐射槽组1712的辐射槽1713的数量。藉由控制辐射槽1713与辐射槽1713’的相对数量,可使由第一辐射槽组1712辐射的能量实质上等于由第二辐射槽组1712’辐射的能量。
第三波导槽1711’’沿第一方向P1延伸且连接于第二辐射槽组1712’。
形成于天线层170的网格包含区域171m’,网格由第二波导槽1711’、辐射槽1713’与第三波导槽1711’’定义。网格的数个长侧较佳地由第二波导槽1711’或第三波导槽1711”形成。网格的数个短侧较佳地由辐射槽1713’形成。
图2B绘示图2A中沿方向2B-2B’的剖视图。剖视图中,镜射影像的天线槽组的辐射槽相似于天线槽组171的辐射槽1713’。天线层170的网格在剖视图中绘示如区域171m’,因为其相似于天线槽组171的区域171m’。半导体封装件200的其他特征相似于图1A的半导体封装件100,容此不再赘述。
图3绘示另一实施例的天线层170的俯视图。天线层170包括二天线槽组171,其中天线槽组171及近似其的镜射影像通过阻抗匹配槽174连接。其中一槽组171已详细描述,其它槽组实质上是槽组171的镜射影像。天线槽组171包括第一波导槽1711、第一辐射槽组、第二波导槽1711’、第二辐射槽组1712’、第三波导槽1711’’、第三辐射槽组1712’’及第四波导槽1711’’’。
第一辐射槽组绘示成包括一个辐射槽1713,然而,此非用以限制本发明实施例。另一实施例中,第一辐射槽组可包括多个辐射槽1713。
第二波导槽1711’沿第一方向P1延伸,且连接于第一辐射槽1713。
第二辐射槽组1712’沿第二方向P2延伸,且连接于第二波导槽1711’。
第三波导槽1711”沿第一方向P1延伸,且连接于第二辐射槽组1712’。
第三辐射槽组1712”沿第二方向P2延伸,且连接于第三波导槽1711”。
第四波导槽1711”’沿第一方向P1延伸,且连接于第三辐射槽组1712”。另一实施例中,可省略第四波导槽1711”’。
为了更均匀地辐射,第二辐射槽组1712’的辐射槽1713’的数量多于第一辐射槽组的辐射槽1713的数量,且第三辐射槽组1712”的辐射槽1713”的数量多于第二辐射槽组1712’的辐射槽1713’的数量。
阻抗匹配槽174连接天线槽组171的第一波导槽1711。第一波导槽1711的长度加上阻抗匹配槽174的长度的总合可以例如是一毫米波信号的波长的一半。阻抗匹配槽174的长度提供天线层170一阻抗匹配功能。
图4绘示图3的半导体封装件的天线层170的E平面的场形图。从图3的天线层170辐射的RF频宽介于57至64GHz。以60GHz来说,由于多辐射槽组(例如,第一辐射槽组、第二辐射槽组1712’及第三辐射槽组1712”)增加天线层170的指向性,因此天线层170表现出优良指向性。
图5A绘示依照本发明另一实施例的半导体封装件300的剖视图。半导体封装件300包括基板110、半导体芯片120、封装体130、屏蔽层140、馈入元件150、导电柱160a、160b及天线层170。
半导体芯片120包括导通孔(via)121,其从半导体芯片120的上表面120u露出。
封装体130包括位于屏蔽层140下方的第一封装体131及位于屏蔽层140上方的第二封装体132。
屏蔽层140包括馈入部141及屏蔽部142。
馈入元件150包括第一馈入部151及第二馈入部152。第一馈入部151从馈入部141延伸至半导体芯片120的导通孔121,以电性连接半导体芯片120。第二馈入部152延伸经过第二封装体132且电性连接屏蔽层140与天线层170。另一实施例中,覆盖半导体芯片120的第一馈入部151的一部分可使用磨削方法移除,使屏蔽层140可直接形成于导通孔121,以电性连接半导体芯片120。如此一来,第一馈入部151可被省略,使第一封装体131的上表面131u实质上与半导体芯片120的上表面120u共面。
多个导电柱160a及160b可分别形成于贯孔130h及130j内,其中贯孔130h及130j形成于封装体130内并环绕馈入元件150,以保护馈入元件150免受电磁干扰。
图5B绘示图5A的俯视图。天线层170包括二彼此连接的天线槽组、天线槽组171及其镜射影像。二阻抗匹配槽174连接天线槽组171与其镜射影像。天线槽组171包括波导槽1711及辐射槽组1712。波导槽1711沿第一方向P1延伸。辐射槽组1712连接于波导槽1711且沿第二方向P2延伸。辐射槽组1712包括至少二辐射槽1713。如图所示,辐射槽1713未延伸至天线层170的侧面170s。然而,另一实施例中,辐射槽1713可延伸至天线层170的侧面170s。如图所示,辐射槽1713可垂直地连接于波导槽1711;或者,另一实施例中,辐射槽1713可倾斜地连接于波导槽1711。倾斜地连接方式可增长辐射槽1713,以辐射更多毫米波信号的能量。
如图5B所示,区域175形成于天线层170,且由波导槽1711、其镜射影像与二阻抗匹配槽174定义。馈入元件150位于天线层170的一中间部。具体来说,馈入元件150设于区域175的中心。
图6绘示依照本发明另一实施例的俯视图。天线层170包括二天线槽组、一天线槽组171与其实质上镜射的影像,且由二阻抗匹配槽174连接。天线槽组171包括第一波导槽1711、第一辐射槽组1712、第二波导槽1711’、第二辐射槽组1712’及第三波导槽1711”。由数个阻抗匹配槽174、第一波导槽1711及其镜射影像所定义的区域175形成于天线层170中心。馈入元件150位于区域175的中间部。
如图6所示,第一辐射槽组1712包括多个辐射槽1713。然而,另一实施例中,第一辐射槽组1712包括一个辐射槽1713。为了增强辐射,第二辐射槽组1712’的辐射槽1713’的数量多于第一辐射槽组1712的辐射槽1713的数量。
一些实施例中,第三波导槽1711”可省略。
图7绘示依照本发明另一实施例的半导体封装件的俯视图。天线层170包括二天线槽组,天线槽组171与其实质上镜射的影像由二阻抗匹配槽174连接。天线槽组171包括第一波导槽1711、第一辐射槽组、第二波导槽1711’及第二辐射槽组1712’。如图所示,第一辐射槽组包括一辐射槽1713。另一实施例中,第一辐射槽组包括数个辐射槽1713。为了更优良的辐射,第二辐射槽组1712’的辐射槽1713’的数量多于第一辐射槽组的辐射槽1713的数量。
如图7所示,区域175形成于天线层170的中心,且由第一波导槽1711、其镜射影像与二阻抗匹配槽174定义。馈入元件150位于区域175的中间部。
图8绘示依照本发明另一实施例的半导体封装件的俯视图。天线层170包括二天线槽组,天线槽组171与其实质上镜射的影像由二阻抗匹配槽174连接。天线槽组171包括第一波导槽1711、第一辐射槽组、第二波导槽1711’、第二辐射槽组1712’、第三波导槽1711’’、第三辐射槽组1712’’及第四波导槽1711’’’。
如图8所示,区域175形成于天线层170的中心,且由第一波导槽1711、其镜射影像与二阻抗匹配槽174定义。馈入元件150位于区域175的中间部。如图所示,第一辐射槽组包括一个辐射槽1713。其它实施例中,第一辐射槽组包括一个以上的辐射槽1713。为了增进辐射,第二辐射槽组1712’的辐射槽1713’的数量多于第一辐射槽组的辐射槽1713的数量,且第三辐射槽组1712”的辐射槽1713’’的数量多于第二辐射槽组1712’的辐射槽1713’的数量。
图9绘示依照本发明另一实施例的半导体封装件400的俯视图。半导体封装件400包括基板110、半导体芯片120、封装体130、屏蔽层140、馈入元件150、数个导电柱160及天线层170。
基板110包括相对的上表面110u与下表面110b,且更包括一接地部111。接地部111从基板110的上表面110u延伸。封装体130包括第一封装体131及第二封装体132。接地部111可从第一封装体131的侧面131s露出。
屏蔽层140形成于第一封装体131的上表面131u、第一封装体131的侧面131s,且露出接地部111,其中第一封装体131包覆半导体芯片120。屏蔽层140形成一全覆盖屏蔽层,以保护半导体芯片120免受电磁干扰。第二封装体132设于第一封装体131的上表面131u,且覆盖屏蔽层140的一部分与基板110的上表面110u的一部分。本实施例中,天线层170形成于封装体130的上表面130u,但未形成于封装体130的侧面130s。
图10绘示依照本发明另一实施例的半导体封装件500的俯视图。半导体封装件500包括基板110、半导体芯片120、封装体130、屏蔽层140、馈入元件150、数个导电柱160及天线层170。
馈入元件150形成封装体130且直接接触从半导体芯片120的上表面120u露出的导通孔121。导电柱160形成于封装体130的贯孔130h内且环绕馈入元件150以保护馈入元件150免受过多的电磁干扰。
图11绘示依照本发明另一实施例的半导体封装件600的俯视图。半导体封装件600包括基板110、半导体芯片120、无源元件125、封装体130、屏蔽层140、馈入元件150、数个导电柱160及天线层170。
贯孔130h例如是封胶穿孔,其形成于封装体130,且从天线层170延伸至屏蔽层140。导电柱160藉由填入导电材料于贯孔130h而形成。导电柱160通过天线层170电性连接于接地部111。因此,环绕馈入元件150的导电柱160可保护一从馈入元件150发射的馈入信号免受过多电磁干扰。
馈入元件150包括第一馈入部151及第二馈入部152。第一馈入部151延伸穿过封装体130的第一封装体131且电性连接屏蔽层140与无源元件125的接点1251。无源元件125设于基板110的上表面110u且可通过走线112电性连接半导体芯片120。如此一来,馈入元件150可电性连接半导体芯片120。第二馈入部152延伸穿过封装体130的第二封装体132,且电性连接屏蔽层140与天线层170。
图12A至12K绘示图1A的半导体封装件100的制造过程图。
如图12A所示,可采用表面粘贴技术(Surface Mounting Technology,SMT)设置半导体芯片120及无源元件125于基板110上。基板110包括接地部111及走线112。基板110是一包含数个封装单元区(package site)的长条(strip)。
如图12B所示,形成第一封装体131于基板110的上表面110u,以包覆半导体芯片120及无源元件125。第一封装体131包括一上表面131u。
如图12C所示,可采用图案化技术,形成贯孔130j从上表面131u延伸至基板110的走线112。形成贯孔130j的图案化技术例如是微影工艺(photolithography)、化学刻蚀(chemical etching)、激光钻孔(laser drilling)或机械钻孔(mechanical drilling)。
如图12D所示,第一馈入部151及导电柱160b可使用电镀或涂布焊料贴(solderpaste)的方式填入导电材料于贯孔130j内而形成。
如图12E所示,可采用电镀/微影刻蚀(etching photolithographic)工艺,形成屏蔽层140覆盖上表面131u。屏蔽层140包括馈入部141及屏蔽部142,其中馈入部141连接于第一馈入部151且与屏蔽部142隔离,而屏蔽部142连接于导电柱160b。
如图12F所示,形成第二封装体132覆盖屏蔽层140。第二封装体132包括上表面130u。
如图12G所示,可采用图案化技术形成贯孔130h从上表面130u延伸至屏蔽层140。形成贯孔130h的图案化技术例如是微影工艺(photolithography)、化学刻蚀(chemicaletching)、激光钻孔(laser drilling)或机械钻孔(mechanical drilling)。
如图12H所示,第二馈入部152及导电柱160a可使用例如是电镀或涂布焊料贴的方式填入导电材料于贯孔130h内而形成。第一馈入部151及第二馈入部152共同形成馈入元件150。
如图12I所示,形成数个切割道S1经过封装体130、屏蔽层140及接地部。切割道S1使用激光或另一切割刀具形成。基板110的侧面110s、封装体130的侧面130s及接地部111的侧面111s被形成,其中侧面110s、侧面130s与侧面111s实质上共面。例示的切割方法称为”全穿切(full-cut)”,即切割道S1实质上切穿基板110、接地部111与封装体130。
如图12J所示,可使用电镀/微影刻蚀工艺,形成天线层170覆盖封装体130的上表面130u、封装体130的侧面130s与接地部111的侧面111s。天线层170连接于导电柱160a及接地部111,使导电柱160a通过屏蔽层140及天线层170电性连接于接地部111。
如图12K所示,可采用例如是图案化技术,形成二天线槽组171于天线层170,以形成图1A所示的半导体封装件100。
图13A至13F绘示图9的半导体封装件400的制造过程图。图9的半导体封装件400的制造过程相似于图1A的半导体封装件100的制造过程,容此不再赘述。
如图13A所示,可采用例如是表面粘贴技术,设置半导体芯片120及无源元件125于基板110,其中基板110包括从基板110的上表面110u延伸的接地部111。第一馈入部151可使用例如是电镀或涂布焊料贴的方式填入导电材料于第一封装体131的贯孔130j内而形成。贯孔130j可采用图案化技术形成。基板110是包含数个封装单元区的长条。
可采用激光或另外切割刀具形成数个切割道S2经过第一封装体131。第一封装体131的侧面131s及接地部111的侧面111s由切割形成。图13A的切割称为”半穿切法(half-cut method)”,即切割道S2未完全切穿基板110。
如图13B所示,可采用电镀/微影刻蚀(etching photolithographic)工艺,形成屏蔽层140覆盖上表面131u。屏蔽层140包括馈入部141及屏蔽部142,其中馈入部141连接于第一馈入部151且与屏蔽部142隔离。
如图13C所示,形成第二封装体132覆盖屏蔽层140,其中第二封装体132包括上表面130u。
如图13D所示,可采用图案化技术形成贯孔130h从上表面130u延伸至屏蔽层140。形成贯孔130h的图案化技术例如是微影工艺(photolithography)、化学刻蚀(chemicaletching)、激光钻孔(laser drilling)或机械钻孔(mechanical drilling)。
第二馈入部152及导电柱160a可使用电镀或涂布焊料贴的方式填入导电材料于贯孔130h内而形成。第一馈入部151及第二馈入部152共同形成馈入元件150。
如图13E所示,可使用电镀/微影刻蚀工艺,形成天线层170覆盖封装体130的上表面130u。天线层170连接于导电柱160,使天线层170通过导电柱160及屏蔽层140电性连接于接地部111。
如图13F所示,形成数个切割道S3经过天线层170、第二封装体132与基板110,以形成图9的半导体封装件400。切割道S3是以激光或另外切割刀具形成。基板110的侧面110s及第二封装体132的侧面130s实质上共面。
图2B的半导体封装件200的制造方法、图5A的半导体封装件300的制造方法及图11的半导体封装件600的制造方法相似于图1A的半导体封装件100的制造方法,容此不再赘述。图10的半导体封装件500的制造方法相似于图9的半导体封装件400的制造方法,容此不再赘述。
综上所述,虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明。本发明所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作各种更动与润饰。因此,本发明的保护范围当视后附的权利要求所界定者为准。
【符号说明】
100、200、300、400、500、600:半导体封装件
110:基板
110b:下表面
110s、111s、130s、131s、170s:侧面
110u、120u、130u、131u:上表面
111:接地部
112:走线
120:半导体芯片
121:导通孔
125:无源元件
1251:接点
130:封装体
130h、130j:贯孔
131:第一封装体
132:第二封装体
140:屏蔽层
141:馈入部
142:屏蔽部
150:馈入元件
151:第一馈入部
152:第二馈入部
160、160a、160b:导电柱
170:天线层
171、171a:天线槽组
1711、1711a、1711'、1711”、1711”':波导槽
1712、1712a、1712'、1712”:辐射槽组
1713、1713a、1713'、1713”:辐射槽
171m、171m';175:区域
172:馈入层
173:辐射层
174:阻抗匹配槽
S1、S2、S3:切割道
L1:长度
P1:第一方向
P2:第二方向
Claims (20)
1.一种半导体封装件,包括:
一基板;
一半导体芯片,设于该基板上;
一封装体,包覆该半导体芯片且包括一上表面;以及
一天线层,形成于该封装体的该上表面,该天线层包括一馈入层与一辐射层,且该辐射层透过一第一波导槽与该馈入层隔离。
2.如权利要求1所述的半导体封装件,其特征在于,该第一波导槽沿一第一方向延伸,且与一沿一第二方向延伸的第一辐射槽组连接。
3.如权利要求2所述的半导体封装件,其特征在于,该天线层更包括一阻抗匹配槽,其与该第一波导槽连接且与该第一辐射槽组连接。
4.如权利要求2所述的半导体封装件,其特征在于,该天线层更包括:
一第二波导槽,沿该第一方向延伸,其中该第一辐射槽组连接于该第二波导槽;以及
一第二辐射槽组,连接于该第二波导槽且沿该第二方向延伸。
5.如权利要求1所述的半导体封装件,其特征在于,更包括:
一馈入元件,电性连接于该半导体芯片与该馈入层。
6.如权利要求5所述的半导体封装件,其特征在于,该基板包括一接地部,且该辐射层电性连接于该接地部且与该馈入层隔离。
7.如权利要求6所述的半导体封装件,其特征在于,该封装体包括多个贯孔,所述多个贯孔环绕该馈入元件,该半导体封装件更包括:
多个导电柱,形成于所述多个贯孔内且电性连接于该接地部与该辐射层。
8.如权利要求5所述的半导体封装件,其特征在于,该馈入元件与该半导体芯片的一导通孔电性连接。
9.如权利要求1所述的半导体封装件,其特征在于,该天线层延伸至该封装体的一侧面。
10.一种半导体封装件,包括:
一基板;
一半导体芯片,设于该基板上;
一第一封装体,包覆该半导体芯片;
一第二封装体,覆盖该第一封装体;以及
一天线层,形成于该第二封装体上,该天线层包括一馈入层与一辐射层,且该辐射层透过一第一波导槽与该馈入层隔离。
11.如权利要求10所述的半导体封装件,其特征在于,该第一封装体包括一上表面,该半导体封装件更包括:
一屏蔽层,形成于该第一封装体的该上表面,其中该屏蔽层被该第二封装体覆盖。
12.如权利要求11所述的半导体封装件,其特征在于,更包括:
一第一馈入元件,电性连接该屏蔽层与该半导体芯片;以及
一第二馈入元件,电性连接该屏蔽层与该天线层的该馈入层。
13.如权利要求10所述的半导体封装件,其特征在于,更包括:
一馈入元件;
多个贯孔,形成于该第二封装体,所述多个贯孔环绕该馈入元件;以及
多个导电柱,形成于所述多个贯孔内且电性连接于该天线层的该辐射层。
14.如权利要求10所述的半导体封装件,其特征在于,更包括:
一屏蔽层,形成于该第一封装体的一侧面。
15.如权利要求14所述的半导体封装件,其特征在于,更包括:
一第一馈入元件,通过该第一封装体电性连接于该半导体芯片;以及
一第二馈入元件,电性连接该屏蔽层与该天线层的该馈入层。
16.一种半导体封装件的制造方法,包括:
设置一半导体芯片于一基板上;
形成一封装体包覆该半导体芯片;
形成一天线层于该半导体封装件的一上表面,其中该天线层电性连接于该半导体芯片;
形成二彼此连接的天线槽组于该天线层,其中各该天线槽组包括一馈入层与一辐射层,且该辐射层透过一第一波导槽与该馈入层隔离。
17.如权利要求16所述的制造方法,其特征在于,该第一波导槽沿一第一方向延伸,且与一沿一第二方向延伸的第一辐射槽组连接。
18.如权利要求17所述的制造方法,其特征在于,更包括:
形成一阻抗匹配槽于该天线层,其中该阻抗匹配槽与该第一波导槽连接且与该第一辐射槽组连接。
19.如权利要求17所述的制造方法,其特征在于,更包括:
一第二波导槽,沿该第一方向延伸,其中该第一辐射槽组连接于该第二波导槽;以及
一第二辐射槽组,连接于该第二波导槽且沿该第二方向延伸。
20.如权利要求16所述的制造方法,其特征在于,更包括:
形成一馈入元件于该封装体,以电性连接该半导体芯片与该天线层的该馈入层。
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US9129954B2 (en) | 2015-09-08 |
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