CN103165566A - 基板结构、半导体封装件及半导体封装件的制造方法 - Google Patents

基板结构、半导体封装件及半导体封装件的制造方法 Download PDF

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CN103165566A
CN103165566A CN2012105896721A CN201210589672A CN103165566A CN 103165566 A CN103165566 A CN 103165566A CN 2012105896721 A CN2012105896721 A CN 2012105896721A CN 201210589672 A CN201210589672 A CN 201210589672A CN 103165566 A CN103165566 A CN 103165566A
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conductive layer
cabling
conductive
electrical components
packaging body
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CN103165566B (zh
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周辉星
林少雄
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Advanpack Solutions Pte Ltd
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Advanpack Solutions Pte Ltd
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Abstract

本发明公开一种基板结构、半导体封装件及半导体封装件的制造方法。基板结构包括导电结构、电性元件、封装体及一环状电性结构。导电结构包括第一导电层及第二导电层。第一导电层具有下表面。第二导电层及电性元件设于第一导电层的下表面上。封装体包覆导电结构及电性元件且具有上表面。环状电性结构环绕导电结构及电性元件而设于封装体的上表面的边缘并露出导电结构。

Description

基板结构、半导体封装件及半导体封装件的制造方法
技术领域
本发明涉及一种基板结构、半导体封装元件及其制造方法，且特别是涉及一种具有导电层的基板结构、半导体封装元件及其制造方法。 
背景技术
随着电子产业的蓬勃发展，半导体封装技术不断地进步。一般而言，半导体封装技术是利用导线架承载芯片，并以封胶密封导线架及基板，以避免芯片受潮或因碰撞而损坏。其中，芯片更通过导线架的接垫与外界电连接，以便于与印刷电路板电连接。 
然而，导线架的重量较重、体积较大，因此不符合电子产品追求「轻、薄、短、小」的潮流。 
发明内容
本发明的目的在于提供一种基板结构、半导体封装元件及其制造方法，可获得甚薄的导电层，以减小基板结构及半导体封装元件的体积。 
为达上述目的，本发明提出一种基板结构。基板结构包括一导电结构、一电性元件、一封装体及一环状电性结构。导电结构包括一第一导电层及一第二导电层。第一导电层具有一下表面。第二导电层设于第一导电层的下表面上。电性元件设于第一导电层的下表面上。封装体包覆导电结构及电性元件且具有一上表面。环状电性结构环绕导电结构及电性元件而设于封装体的上表面的边缘并露出导电结构。 
本发明还提出一种半导体封装件。半导体封装件包括一基板结构、一半导体芯片及一第二封装体。基板结构包括一导电结构、一电性元件、一封装体及一环状电性结构。导电结构包括一第一导电层及一第二导电层。第一导电层具有一下表面。第二导电层设于第一导电层的下表面上。电性元件设于第一导电层的下表面上。封装体包覆导电结构及电性元件且具有一上表面。 环状电性结构环绕导电结构及电性元件而设于封装体的上表面的边缘并露出导电结构。半导体芯片设于第一导电层的上表面上。第二封装体包覆半导体芯片。 
本发明还提出一种半导体封装件的制造方法。制造方法包括以下步骤。提供一电性载板，电性载板具有相对的一上表面与一下表面；形成一第一导电层于电性载板的下表面上，其中第一导电层具有一下表面；形成一第二导电层于第一导电层的下表面上，其中第二导电层及第一导电层构成一导电结构；设置一电性元件于第一导电层的下表面上；形成一第一封装体包覆第一导电层、第二导电层及电性元件但不覆盖电性载板的下表面的边缘；移除第一封装体的一部分，直到露出第二导电层；以及，移除电性载板的部分材料，使电性载板的保留部分形成一环状电性结构，其中环状电性结构保留于封装体的上表面上、环绕导电结构及该电性元件并露出导电结构的上表面。 
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附附图，作详细说明如下： 
附图说明
图1绘示依照本发明一实施例的基板结构的剖视图； 
图2绘示依照本发明另一实施例的基板结构的剖视图； 
图3A绘示依照本发明另一实施例的基板结构的剖视图； 
图3B绘示图3A的局部俯视图； 
图4A绘示依照本发明另一实施例的基板结构的俯视图； 
图4B绘示图4A中沿方向4B-4B’的剖视图； 
图5绘示依照本发明一实施例的半导体封装件的剖视图； 
图6绘示依照本发明一实施例的半导体封装件的剖视图； 
图7A至图7T绘示依照本发明一实施例的半导体封装件的制造流程图。 
主要元件符号说明 
10、20：半导体封装件 
12、22：半导体芯片 
14：第二封装体 
16：焊球 
17：底胶 
18、1121：导电柱 
19：焊料 
28：焊线 
100、200、300、400：基板结构 
110、310、510：导电结构 
110u、111u、130u、140u：上表面 
110b、111b、112b、130b、140b：下表面 
111：第一导电层 
1111、1111′、1111″、1111″′：走线 
112：第二导电层 
113：第一表面处理层 
114：第二表面处理层 
120、220、320：电性元件 
130′：热固性材料 
130：封装体 
131：第一凹陷部 
132：第二凹陷部 
140、440：环状电性结构 
140’：电性载板 
140a：开口 
140h：贯孔 
140s1：内侧壁 
140s2：外侧壁 
180：第一光致抗蚀剂层 
180a：第一开孔 
185：模具 
185a：膜穴 
190：第二光致抗蚀剂层 
190a：第二开孔 
195：第三光致抗蚀剂层 
195a1：第三开孔 
195a2：第四开孔 
221：第一垫高块 
222：第二垫高块 
223：连接件 
311：第三导电层 
320a：主动面 
441：肋条 
442：边框 
440R1：封装单元区 
440R2：元件区 
D1、D2、D3：剖面直径 
S：端点 
具体实施方式
请参照图1，其绘示依照本发明一实施例的基板结构的剖视图。基板结构100包括导电结构110、电性元件120、第一封装体130及环状电性结构140。 
导电结构110包括第一导电层111及第二导电层112，其中第一导电层111具有相对的上表面111u与下表面111b，而第二导电层112设于第一导电层111的下表面111b上。 
第一导电层111的材料可包括铜、镍、钯、金或其它导电材料，而第二导电层112的材质相似于第一导电层111。第一导电层111与第二导电层112可由完全相同或相异材料制成。 
第一导电层111包括至少一走线1111，而第二导电层112包括至少一导电柱1121，各导电柱1121设于对应的走线1111的下表面111b。导电结构110的下表面110b从第一封装体130的下表面130b露出，以电连接于一外部电路元件(未绘示)，如电路板。 
可通过微蚀刻方法，蚀刻第一导电层111，使其上表面111u相对第一封装体130的上表面130u往内凹陷，而形成一第一凹陷部131。相似地，可通过微蚀刻方法，蚀刻第二导电层112，使其下表面112b相对第一封装体130 的下表面130b往内凹陷，而形成一第二凹陷部132。 
导电结构110还包括第一表面处理层113，其形成于第一导电层111的上表面111u且位于第一凹陷部131内。第一表面处理层113的上表面相对第一封装体130的上表面130u往内凹陷，然也可实质上对齐，如齐平或凸出。较佳地，额外的接合垫可形成于第一导电层111的选择性位置上，以接合芯片。第一表面处理层113例如是以电镀、无电电镀(electroless)或浸液(immersion)方式形成。此外，导电结构110还包括第二表面处理层114，其形成于第二导电层112的下表面112b且位于第二凹陷部132内。第二表面处理层114的上表面相对第一封装体130的下表面130b往内凹陷，然也可实质上对齐，如齐平或凸出。第二表面处理层114的形成方法相似于第一表面处理层113。第一表面处理层113与第二表面处理层114可于同一制作工艺中一并形成或于于不同制作工艺中个别形成。此外，第一表面处理层113的材料是铜、镍、钯、金、银、锡或其它导电材料，而第二表面处理层114的材料相似于第一表面处理层113，且可完全相同或相异于第一表面处理层113。另一例中，也可省略第一表面处理层113及第二表面处理层114。 
电性元件120设于第一导电层111的下表面111b上，且跨接二走线1111，以电连接二走线1111。被电性元件120跨接的走线1111可以是相邻二走线1111。或者，电性元件120可形成于在单条走线1111上。本例中，电性元件120是被动元件，然本发明实施例不限制电性元件120的种类。 
第一封装体130包覆导电结构110及电性元件120且具有上表面130u。上述导电结构110及电性元件120埋设于第一封装体130中，而受到第一封装体130的保护。第一封装体130是介电材料或绝缘材料。第一封装体130例如是热固性(thermoset)聚合树脂，如环氧树脂。较佳地，第一封装体130是一封胶材料(molding compound material)，其包含二氧化硅填料(silicafiller)。 
环状电性结构140可作为基板结构100的手把，以方便抓取或搬运基板结构100。详细来说，若省略环状电性结构140，则在抓取或搬运基板结构100时会接触导电结构110或第一封装体130，而对基板结构100产生机械性损害。环状电性结构140环绕导电结构110及电性元件120而设于第一封装体130的上表面130u的边缘并露出导电结构110的上表面。详细来说，环状电性结构140具有开口140a及贯孔140h，开口140a露出导电结构110 的上表面110u及封装体130的上表面130u，而贯孔140h位于开口140a的内侧壁140s1与外侧壁140s2之间且未与第一封装体130上下重叠。贯孔140h可作为环状电性结构140的应力释放孔及/或定位孔。 
请参照图2，其绘示依照本发明另一实施例的基板结构的剖视图。基板结构200包括导电结构110、电性元件220、第一封装体130及环状电性结构140。 
本例中，走线1111包括彼此隔离的第一走线1111’、第二走线1111”与第三走线1111”’，其中第三走线1111”’位于第一走线1111’与第二走线1111”之间。电性元件220是电性支架。电性元件220包括第一垫高块221、第二垫高块222及连接件223，其中第一垫高决221设于第一走线1111’上，第二垫高块222设于第二走线1111”上，连接件223连接第一垫高块221与第二垫高块222并通过第一垫高块221及第二垫高块222与第三走线1111”’上下间隔一距离，而避免与第三走线1111”’电性短路。进一步地说，若在线路布局阶段难以对第一走线1111’与第二走线1111”设计成电连接，则可在后续制作工艺以电性元件220电连接第一走线1111’与第二走线1111”。 
此外，另一电性元件220’可为焊线，其可连接第一走线1111’与第二走线1111”，产生类似于电性元件220的效果。 
另一例中，电性元件220是主动装置(active device)，其连接件223是半导体芯片，而第一垫高块221及第二垫高块222是连接元件，其形成于半导体芯片而构成一倒装(flip-chip)。较佳地，第一垫高块221及第二垫高块222是焊块(solder bump)或铜导电柱，其设于走线1111以提供电连接功能。 
请参照图3A，其绘示依照本发明另一实施例的基板结构的剖视图。基板结构300包括导电结构110、电性元件320、第一封装体130及环状电性结构140。 
导电结构310包括第一导电层111、第二导电层112及第三导电层311，其中第三导电层311形成于第一导电层111与第二导电层112之间。第三导电层311形成于第一走线1111’及第二走线1111”上但未形成于第三走线1111”’上，电性元件320通过第三导电层311与第三走线1111”’上下间隔一距离，而避免与第三走线1111”’电性短路。电性元件320是主动芯片，且具有主动面320a。虽然主动面320a朝向第三走线1111”’，然通过第三导电层311使主动面320a不致与第三走线1111”’电性短路。较佳但非限定地，第三 导电层311形成微孔(Micro-via)，微孔完全嵌设于第一封装体130中，可增加第三导电层311与第一封装体130的结合性。较佳地，第三导电层311形成微柱(micro-stud)连接第一导电层111与第二导电层112。微柱的面积小于第一导电层111及第二导电层112的各别面积。特别一提，微柱的直径小于第一导电层111及第二导电层112的各别直径。 
请参照图3B，其绘示图3A的局部俯视图。第一导电层111、第二导电层112及第三导电层311的剖面例如是圆形，其中第二导电层112的剖面直径D2大于第三导电层311的剖面直径D3，一例中，第三导电层311的剖面直径D3例如是约20～100微米，而第二导电层112的剖面直径D2例如是约200～300微米。此外，第一导电层111的剖面直径D1大于第三导电层311的剖面直径D3，一例中，第一导电层111的剖面直径D1的剖面直径D3例如是约80～100微米。 
如图3B所示，若第一导电层111直接形成于第二导电层112上，则第三导电层311电连接端点S的面积等于第二导电层112的剖面面积，端点S的大面积使得如图3B所示的走线111’无法形成。相对地，本发明内容的实施例中，第一导电层111经由第三导电层311电连接于第二导电层112，使第一导电层111可不直接形成于第二导电层112上，且第二导电层112的剖面直径D2大于第三导电层311的剖面直径D3，此时第一导电层111接合于第三导电层311的部分(电连接端点)的面积可以缩小至等于或略大于第三导电层311的剖面面积，因此仍有足够的空间形成如图3B所示的走线111’，因此第一导电层111(走线)的电性端点之间(与第三导电层311电连接的部分)可以形成较多导线，因此可以提升导线密度，并提高导线设计的弹性。 
请参照图4A及图4B，图4A绘示依照本发明另一实施例的基板结构的俯视图，而图4B绘示图4A中沿方向4B-4B’的剖视图。基板结构400包括导电结构110、电性元件320、第一封装体130及环状电性结构440。 
本例中，环状电性结构440包括多个肋条441、边框442及多个开口140a，其中肋条441分隔相邻二开口140a。边框442是一封闭环形边框，燃也可为开放环形边框。肋条441连接于边框442，如此可提升环状电性结构440的整体强度，以避免过度翘曲或变形。另一例中，环状电性结构440也可省略肋条441而形成单一开口140a。此外，肋条441及开口140a的数量不受本发明实施例所限，另一例中，肋条441可为单个或超过二个，而开口140a 可以是二个或超过三个。 
单个开口140a对应单个封装单元区440R1，各封装单元区440R1定义多个元件区440R2。至少一个芯片可设于各元件区440R2，以形成半导体封装件。于切割制作工艺中，沿单个元件区440R2的边界可切割出单个半导体封装件。 
请参照图5，其绘示依照本发明一实施例的半导体封装件的剖视图。半导体封装件10包括基板结构100、半导体芯片12、第二封装体14及底胶17。半导体芯片12通过至少一连接结构电连接于导电结构110。本例中，半导体芯片12以主动面朝下的方位设于导电结构110上。较佳地，连接结构可包括焊球或导电柱18及焊料19。第二封装体14包覆半导体芯片12且覆盖基板结构100的导电结构110的上表面110u及基板结构100的第一封装体130的上表面130u。第二封装体14的材料可相似于第一封装体130，容此不再赘述。较佳地，焊球16可设于导电结构110的下表面110b，半导体封装件10通过焊球16设于且电连接于外部电路板(未绘示)。底胶17包覆导电柱18及焊料19。 
请参照图6，其绘示依照本发明一实施例的半导体封装件的剖视图。半导体封装件20包括基板结构100、半导体芯片22及第二封装体14。本例中，半导体芯片22以主动面朝上的方位设于导电结构110上，且通过至少一焊线28电连接于导电结构110。 
请参照图7A至图7T，其图绘示依照本发明一实施例的半导体封装件的制造流程图。 
如图7A所示，提供电性载板140’，其中电性载板140’具有相对的上表面140u与下表面140b。 
电性载板140’例如是铜层或具有铜外披覆层(Cu clad layer)的复合金属层。复合金属层包括内层和铜外披覆层，内层的厚度大于铜外披覆层的厚度。内层例如包括钢、或包括铁、碳、镁、磷、硫、铬及镍其中两种以上的合金。铜外披覆层的材质与内层的材质不相同，从而在后续制作工艺中，提供较佳的蚀刻阻隔，并且铜外披覆层使得电性载板140’可以被视作一个完整的铜层来操作应用，并且能够降低整体制作成本。此外，内层的热膨胀系数(CTE)接近用以包覆半导体芯片的封装材料的热膨胀系数，可以使得应用电性载板140’而制成的半导体封装元件的翘曲量减少，可容许电性载板140’的面积增 大，而能在电性载板140’上形成更多数量的半导体封装元件。 
如图7B所示，可采用例如是涂布方式，分别形成第一光致抗蚀剂层180覆盖电性载板140’的上表面140u及下表面140b。 
如图7C所示，可采用例如是蚀刻方式，图案化第一光致抗蚀剂层180，以形成数个第一开口180a，而露出电性载板140’的一部分。 
如图7D所示，可采用例如是电镀方式，形成第一导电材料于第一开口180a中，以形成第一导电层111。由于采用电镀方式，形成的第一导电层111的线宽(line width)与线距(line spacing)可以达到10微米等级。第一导电材料的材料例如是铜、镍、钯、金(Au)或其它导电材料。 
如图7E所示，可采用例如是涂布方式，形成第二光致抗蚀剂层190于覆盖第一导电层111。 
如图7F所示，可采用例如是蚀刻方式，形成数个第二开孔190a于第二光致抗蚀剂层190，以露出第一导电层111。 
如图7G所示，可采用例如是电镀方式，形成第二导电材料于第二开孔190a内，以形成第二导电层112，其中第二导电层112及第一导电层111共同构成导电结构110。第二导电材料的种类相似于第一导电材料。 
如图7H所示，可采用蚀刻显影方式，一次移除第一光致抗蚀剂层180及第二光致抗蚀剂层190，以露出第一导电层111、第二导电层112及电性载板140’。 
如图7I所示，可采用例如是表面粘贴技术(SMT)或热压接技术(Thermo-compression Bonding，TCB)，设置电性元件120于第一导电层111的下表面111b上。 
如图7J所示，设置导电结构110于模具185的膜穴185a中。 
如图7K所示，于高温高压的条件下注入液态的热固性材料130’于膜穴185a中并包覆第一导电层111、第二导电层112及电性元件120，但不覆盖电性载板140’的下表面140b的边缘。液态的热固性材料130’固化后便形成第一封装体130。 
一实施例中，注入热固性材料130’之前，更可对导电结构110(第一导电层111、第二导电层112及第三导电层311)的表面进行表面处理，例如是以化学方法或是等离子体，增进其表面与第一封装体130之间的结合力。 
相较于一般以热压(lamination)成型方式形成封装体，其操作压力容易对 精细的金属结构造成损害，本实施例中，经由此移转成型制作工艺(transfermolding process)，加热热固性材料130’使其液态化，接着在高温高压条件下以液态形式注入模具185的膜穴185a中，因此不会对第一导电层111、第二导电层112及第三导电层311的结构产生损害。再者，以液态形式注入模具185的膜穴185a中，液态的热固性材料130’可以完整包覆第一导电层111、第二导电层112及第三导电层311，并且液态的形式使得操作压力可以很高仍不会损害结构，因此可以利用高压防止气体产生，使得形成的第一封装体130与第一导电层111、第二导电层112及第三导电层311之间具有良好的结合性。此外，在高温高压下进行移转成型，使得第一封装体130与导电层111、112及311之间的密封性好，在后续蚀刻制作工艺中导电层111、112及311不会被破坏。 
如图7L所示，可采用例如是磨削方式，移除第一封装体130的一部分，直到露出第二导电层112。 
如图7M所示，可采用例如是涂布方式，形成第三光致抗蚀剂层195包覆电性载板140’、第一封装体130及导电结构110。 
如图7N所示，可采用例如是蚀刻方式，形成第三开孔195a1及第四开孔195a2于第三光致抗蚀剂层195，以露出电性载板140’的一部分。 
如图7O所示，可采用例如是蚀刻方式，分别通过第三开孔195a1及第四开孔195a2形成开口140a及贯孔140h于电性载板140’，使电性载板140’形成环状电性结构140。环状电性结构140保留于第一封装体130的上表面130u上、环绕导电结构110及电性元件120并露出导电结构110的上表面110u。详细来说，开口140a露出导电结构110的上表面110u，而贯孔140h位于开口140a的内侧壁140s1与外侧壁140s2之间且未与第一封装体130上下重叠。 
如图7P所示，可采用蚀刻方式，移除第三光致抗蚀剂层195。然后，可采用例如微蚀刻技术，移除部分第一导电层111，使第一导电层111的上表面111u相对第一封装体130的上表面130u凹陷(如图1所示)；相似地，可采用例如微蚀刻技术，移除部分第二导电层112，使第二导电层112的下表面112b相对第一封装体130的下表面130b凹陷。然后，可形成如图1所示的第一表面处理层113及第二表面处理层114，如此，便形成如图1所示的基板结构100。 
如图7Q所示，可采用例如是表面粘贴技术，设置至少一半导体芯片12于导电结构110的上表面110u上。半导体芯片12例如是倒装。然后，可形成底胶(underfill)17包覆半导体芯片12的焊料19及导电柱18。 
如图7R所示，可采用相似于第一封装体130的形成方法，形成第二封装体14包覆半导体芯片12。 
如图7S所示，形成至少一焊球16于导电结构110的下表面110b。 
如图7T所示，可采用激光或刀具，切割第一封装体130及第二封装体16，以形成至少一如图5所示的半导体封装件10。 
另一例中，可以半导体芯片22取代半导体芯片12，可形成图6所示的半导体封装件20。 
此外，基板结构200、300及400的形成方法相似于基板结构100，容此不再赘述。 
综上所述，虽然已结合以上实施例公开了本发明，然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应以附上的权利要求所界定的为准。 

Claims (29)

1.一种基板结构，包括：
导电结构，包括：
第一导电层，具有一下表面；
第二导电层，设于该第一导电层的该下表面上；
电性元件，设于该第一导电层的该下表面上；
封装体，包覆该导电结构及该电性元件且具有一上表面；以及
环状电性结构，环绕该导电结构及该电性元件而设于该封装体的该上表面的边缘并露出该导电结构。
2.如权利要求1所述的基板结构，其中该第一导电层包括多条走线，该电性元件跨接二该走线。
3.如权利要求1所述的基板结构，其中该电性元件是被动元件。
4.如权利要求1所述的基板结构，其中该电性元件是焊线。
5.如权利要求1所述的基板结构，其中该电性元件是电性支架。
6.如权利要求5所述的基板结构，其中该第一导电层包括相隔离的一第一走线、一第二走线与一第三走线，该第三走线位于该第一走线与该第二走线之间，该电性元件包括：
第一垫高块，设于该第一走线上；
第二垫高块，设于该第二走线上；以及
连接件，连接该第一垫高块与该第二垫高块，并通过该第一垫高块及该第二垫高块与该第三走线间隔一距离。
7.如权利要求6所述的基板结构，其中该电性元件是一主动装置，而该连接件是一半导体芯片，该第一垫高块及该第二垫高块形成于该半导体芯片上而构成一倒装；其中，该第一垫高块及该第二垫高块设于该第一走线及该第二走线，而提供电连接功能。
8.如权利要求1所述的基板结构，其中该电性元件是主动芯片。
9.如权利要求8所述的基板结构，其中该导电结构还包括一第三导电层形成于该第一导电层与该第二导电层之间，该第一导电层包括相隔离的一第一走线、一第二走线与一第三走线，该第三走线位于该第一走线与该第二走线之间，且该第三导电层形成于该第一走线及该第二走线上但未形成于该第三走线上，该电性元件通过该第三导电层与该第三走线间隔一距离。
10.如权利要求9所述的基板结构，其中该电性元件具有一主动面，该主动面朝向该第三走线。
11.如权利要求1所述的基板结构，其中该环状电性结构具有一开孔及一贯孔，该开孔露出该导电结构的上表面，而该贯孔位于该开孔的内侧壁与外侧壁之间，且未与该封装体上下重叠。
12.如权利要求1所述的基板结构，其中该第一导电层包括多条走线，而该第二导电层包括多个导电柱，各该导电柱设于对应的该走线。
13.一种半导体封装件，包括：
基板结构，包括：
导电结构，包括：
第一导电层，具有一下表面；
第二导电层，设于该第一导电层的该下表面上；
电性元件，设于该导电结构的该下表面上；及
第一封装体，包覆该导电结构及该电性元件且具有一上表面；
半导体芯片，设于该第一导电层的该上表面上；以及
第二封装体，包覆该半导体芯片。
14.一种半导体封装件的制造方法，包括：
提供一电性载板，该电性载板具有相对的一上表面与一下表面；
形成一第一导电层于该电性载板的该下表面上，其中该第一导电层具有一下表面；
形成一第二导电层于该第一导电层的该下表面上，其中该第二导电层及该第一导电层构成一导电结构；
设置一电性元件于该第一导电层的该下表面上；
形成一第一封装体包覆该第一导电层、该第二导电层及该电性元件但不覆盖该电性载板的该下表面的边缘；
移除该第一封装体的一部分，直到露出该第二导电层；以及
移除该电性载板的部分材料，使该电性载板的保留部分形成一环状电性结构，其中该环状电性结构保留于该封装体的上表面上、环绕该导电结构及该电性元件并露出该导电结构的该上表面。
15.如权利要求14所述的制造方法，其中该第一导电层包括多条走线；
在设置该性元件于该第一导电层的该下表面上的该步骤中，该电性元件跨接二该走线。
16.如权利要求14所述的基板结构，其中该电性元件是被动元件、主动芯片、焊线或电性支架。
17.如权利要求14所述的制造方法，其中该第一导电层包括相隔离的一第一走线、一第二走线与一第三走线，该第三走线位于该第一走线与该第二走线之间；
在设置该性元件于该第一导电层的该下表面上的该步骤中，该电性元件是电性支架且一第一垫高块、一第二垫高块及一连接件，该连接件，连接该第一垫高块与该第二垫高块，该电性元件是以该第一垫高块设于该第一走线及该第二垫高块设于该第二走线的方式设置，以通过该第一垫高块及该第二垫高块与该第三走线间隔一距离。
18.如权利要求14所述的制造方法，还包括：
形成一第三导电层于该第一导电层的该下表面上，其中该第一导电层包括相隔离的一第一走线、一第二走线与一第三走线，该第三走线位于该第一走线与该第二走线之间，该第三导电层形成于该第一走线及该第二走线上但未形成于该第三走线上；
形成该第二导电层于该第三导电层上；
在设置该性元件于该第一导电层的该下表面上的该步骤中，该电性元件是主动芯片且通过该第三导电层与该第三走线间隔一距离。
19.如权利要求18所述的制造方法，其中于设置该性元件于该第一导电层的该下表面上的该步骤中，该电性元件具有一主动面，该电性元件是以该主动面朝向该第三走线的方式设于该第三导电层上。
20.如权利要求14所述的制造方法，其中于移除该电性载板的部分材料的该步骤中包括：
形成一开孔及一贯孔于该电性载板，其中该开孔露出该导电结构的该上表面，而该贯孔位于该开孔的内侧壁与外侧壁之间且未与该封装体上下重叠。
21.如权利要求14所述的制造方法，其中该第一导电层包括多条走线，而该第二导电层包括多个导电柱，各该导电柱设于对应的该走线。
22.如权利要求14所述的制造方法，还包括：
设置一半导体芯片于该导线结构的该上表面；
形成一第二封装体包覆该半导体芯片；以及
切割该第二封装体及该第一封装体。
23.如权利要求14所述的制造方法，还包括：
切割该第一封装体。
24.如权利要求14所述的制造方法，还包括：
形成一第一光致抗蚀剂层覆盖该电性载板的该上表面及该下表面；
形成多个第一开孔于该第一光致抗蚀剂层，以露出该电性载板的一部分；
形成一第一导电材料于该第一开孔内，以形成该第一导电层；
形成一第二光致抗蚀剂层覆盖该第一导电层；
形成多个第二开孔于该第二光致抗蚀剂层，以露出该第一导电层；以及
形成一第二导电材料于该第二开孔内，以形成该第二导电层。
25.如权利要求14所述的制造方法，还包括：
一次移除该第一光致抗蚀剂层及该第二光致抗蚀剂层。
26.如权利要求14所述的制造方法，其中于形成该第一封装体的该步骤包括：
设置该导电结构于一模具的一膜穴中；
注入一液态的热固性材料于该膜腔中并包覆该导电结构；以及
固化该液态的热固性材料以形成该封装体。
27.如权利要求14所述的制造方法，还包括：
蚀刻该第一导电层的上表面，以形成一第一凹陷部；以及
形成一第一表面处理层于该第一凹陷部内。
28.如权利要求14所述的制造方法，还包括：
蚀刻该第二导电层的下表面，以形成一第二凹陷部；以及
形成一第二表面处理层于该第二凹陷部内。
29.如权利要求14所述的制造方法，其中该电性载板为一铜层或具有一铜外披覆层的复合金属层。
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