TW452903B - Thin semiconductor device and its manufacturing method - Google Patents

Thin semiconductor device and its manufacturing method Download PDF

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Publication number
TW452903B
TW452903B TW089116410A TW89116410A TW452903B TW 452903 B TW452903 B TW 452903B TW 089116410 A TW089116410 A TW 089116410A TW 89116410 A TW89116410 A TW 89116410A TW 452903 B TW452903 B TW 452903B
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Taiwan
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substrate
semiconductor device
item
conductive
patent application
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TW089116410A
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Chinese (zh)
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Jin-Chiuan Bai
Tzung-Je Tsai
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United Test Ct Inc
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Publication of TW452903B publication Critical patent/TW452903B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

A thin semiconductor device includes a substrate having at least one opening and composed of a base layer and a plurality of conductive traces. The base layer of the substrate is provided to be adhered to the active surface of a semiconductor chip. A plurality of first conductive devices pass through the opening and are electrically connected to the semiconductor chip and conductive traces. The end terminal of each conductive trace is formed with a second conductive device. The base layer of the substrate is also formed with a first glue body to encapsulate the semiconductor chip. A second glue body is formed on the conductive traces of the substrate to entirely cover the conductive traces, the first conductive devices, and the opening. Meanwhile, the second glue body is shaped to encapsulate the second conductive devices while the bottom terminal of the second conductive device is exposed out of the bottom surface of the second glue body, whereby the bottom terminal of the second conductive device is at the same level as the bottom surface of the second glue body.

Description

Λ62θ〇3 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（1 ) [發明領域] 本發明係關於一種半導體裝置，尤係關於一種半導體 晶片藉成陣列方式植佈於基板底面上之導電元件與外界電 性連接之半導體裝置。 [背景說明] 球柵陣列（BGA)半導體裝置（Ball Grid Array Semiconductor Device)近來已成封裝主流產品之一，其因 在於該種藉成陣列方式植佈於基板底& Jl Ball)供半導體晶月與如印刷電路板（PCB)等外界裝置電性 竊接之結構’相較於傳統之以導線架（Leadframe-Based)為 主之半導體裝置，前者於單位面積内得設有較多之作為輸 出/入連接端（I/O Connectoins)之銲球，且銲球間之距離 (Pitch)亦可有效縮減’使是種BGA半導體裝置之結構能符 合具較多之電子元件（Electronic Components)及電子電路 (Electrical Circuits)之半導體晶片的需求。 前述之習知BGA半導體裝置在以金線（Gold Wires)電 性連接半導體晶片與供該半導體晶片黏接之基板的銲線作 業（Wire Bond)時’銲線機係在半導體晶片之作用表面 (Active Surface，即形成有電子元件與電子電路之表面）的 銲墊（Bond Pad)上燒球後，將金線先上垃二·適當距離再向 外下拉至基板上之銲接處，使線弧（Wire Loop)之頂 半導體晶片之作用$面，而致用ϋ本奐艚與金線 之樹脂膠體（Resin Encapsulant)的頂面須高於該線弧之頂 —— —— 點’方能避β如此，封裝完成之半導體裝置的 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -I n n ·1 n J",J_ n n I n . < Ji _ I _ _ _ _ - 古°*11111 — — 111 — — — i I — 1 ^ I I I · 1 16083 A7 A7 而不利於半導體裝置之薄 五、發明說明（2 j 厚度即會受到線弧高度之限制 化0 為解決前述習知BGA半導體裝置在厚度上之缺點，遂 有-種薄型BGA半導體裝置因運而生，如苐卩圖所示。 是種薄型BGA半導體裝置i，係在供半導體晶片ι〇黏設 之基板11上形成一開孔i 10 ’以供電性連接該半導體晶片 與基板π上之導電跡線（conductlve Traces)lu的金線 Ϊ2自該開孔no通過；該金線12之銲接完成後，係以如 環氧樹脂（Epoxy)等之封裝樹脂（EncapsuUting Resin)將該 金線丨2與開孔lio包覆住而形成一下膠體13，由於該金 線12之線弧的部分高度為基板丨丨所吸收，使金線丨2之線 弧頂點120僅略高於基板η之底面，故得控制該下膠體 13外露出該基板11之底面的南度卜小於植接於該基板u 底面上之銲球1.4的高度Η»因而，用以包覆該半導體晶片 10之上躍體丨5形成後之高度毋須涵蓋線狐頂點至半導體 晶片之作用表面間之距離，故封裝完成後之半導體裝置的 厚度較前述之習知BGA半導體裝置為小。 該第12圖所示之半導體裝置1雖可有效降低整體厚度. 而達到薄化之目的，惟為避免基板1〖上之導電跡線Π 1 外露而與大氣接觸’須在該基板11之底面上敷設一拒銲劑 (Solder Mask)層1 12以完全覆蓋住導電跡線π丨，使基板 Π之製造成本及製程複雜度均為之增加：然而，拒銲劑層 丨U之使用將另產生吸漫性之顧慮，若欲將吸濕性之問題 有效解決，則會進一步增加基板】1之製造成本再而，該 )·Λ ； ----I I I I------------I * i I I ----I I (請先閱讀背面之注意事項再填寫本頁)Λ62θ〇3 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) [Field of the Invention] The present invention relates to a semiconductor device, and more particularly, to a semiconductor wafer planted on the bottom surface of the substrate by an array method A semiconductor device whose conductive elements are electrically connected to the outside. [Background] Ball grid array (BGA) semiconductor device (Ball Grid Array Semiconductor Device) has recently become one of the mainstream packaging products, because this kind of borrowed array method is implanted on the substrate bottom & Jl Ball) for semiconductor crystal Compared with the traditional lead frame-based semiconductor devices, the structure of the electrical stealing of external devices such as printed circuit boards (PCBs) can be provided more in a unit area. I / O Connectoins solder balls, and the pitch between the solder balls (Pitch) can also be effectively reduced, so that the structure of a BGA semiconductor device can meet the requirements of more Electronic Components and Demand for semiconductor wafers for electrical circuits. In the aforementioned conventional BGA semiconductor device, when a wire bonding operation (Wire Bond) is used to electrically connect a semiconductor wafer and a substrate to which the semiconductor wafer is bonded with Gold Wires, a wire bonding machine is attached to the active surface of the semiconductor wafer ( Active Surface, that is, the surface on which the electronic components and electronic circuits are formed, is burned on the bond pad, and then the gold wire is moved up to a proper distance and then pulled down to the soldering place on the substrate to make the wire arc. (Wire Loop) is the top surface of the semiconductor wafer, and the top surface of the resin colloid (Resin Encapsulant) that uses transcript and gold wire must be higher than the top of the line arc. In this way, the packaged semiconductor device (please read the precautions on the back before filling out this page) This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -I nn · 1 n J ", J_ nn I n. < Ji _ I _ _ _ _-ancient ° * 11111 — — 111 — — — i I — 1 ^ III · 1 16083 A7 A7 which is not good for semiconductor devices Will be limited by the arc height. Knowing the shortcomings of BGA semiconductor devices in terms of thickness, there are a variety of thin BGA semiconductor devices that emerged as shown in the figure. It is a thin BGA semiconductor device i, which is a substrate for semiconductor wafers. An opening i 10 ′ is formed on 11 to electrically connect the semiconductor wafer with conductive traces lu on the substrate π. A gold wire Ϊ 2 passes through the opening no. After the welding of the gold wire 12 is completed, The encapsulation resin (EncapsuUting Resin) such as epoxy resin (EncapsuUting Resin) is used to cover the gold wire 2 and the opening lio to form a colloid 13, because the height of the arc of the gold wire 12 is the substrate As a result of absorption, the vertex 120 of the line arc of the gold line 2 is only slightly higher than the bottom surface of the substrate η, so the south degree of the lower colloid 13 exposed to the bottom surface of the substrate 11 is controlled to be less than that implanted on the bottom surface of the substrate u The height of the solder ball 1.4 is therefore high enough to cover the jumper 5 on the semiconductor wafer 10 after the formation of the jumper 5 does not need to cover the distance between the fox apex and the active surface of the semiconductor wafer. Thicker than the conventional BGA The conductor device is small. Although the semiconductor device 1 shown in FIG. 12 can effectively reduce the overall thickness. The purpose of thinning is achieved, but in order to prevent the conductive trace Π 1 on the substrate 1 from being exposed and coming into contact with the atmosphere, it must be in A solder mask layer 1 12 is laid on the bottom surface of the substrate 11 to completely cover the conductive trace π 丨, which increases the manufacturing cost and process complexity of the substrate Π; however, the solder resist layer 丨 U The use will cause additional concerns about hygroscopicity. If the problem of hygroscopicity is to be effectively solved, it will further increase the manufacturing cost of the substrate] 1, and)) Λ; ---- III I ----- ------- I * i II ---- II (Please read the notes on the back before filling this page)

經'"部智慧財產局員工消費合泎."51 S 1608? Λ 5 2 9 〇 3 a： _____Β7 五、發明說明（3 ) 半導體裝置1由於厚度薄化，在其藉表面黏著技術（Surface Mounting Technology)等習知方式黏接至如印刷電路板等 外部裝置（External Devices)時，黏接作業進行中所產生之 高溫會作用於半導體裝置1具不同熱膨脹係數（CTE)之基 板11與上膠趙15’產生之熱應力效應往往易造成半導體 裝置1發生翹曲（Warpage)而導致半導體晶片1〇與基板η 間發生剥離（Delamination)現象以及棊板U本身脫層 爲„_象，並影響至半導體裝置1與外部裝置的電性連接品 質。若欲降低翹曲現象的發生機率，雖得增加基板丨丨之厚 度以抵抗熱應力之影響，惟此舉除會使基板之成本提高 外’尚將導致整體厚度的增加。同時，在封裝作業完成而 對半導體裝置1進行測試時，測試針頭（未圖示）上之多數 接觸尖端易因銲球14之底部乃呈球面狀，而會發生無法全 部觸接至銲球14之底部的狀況’當測試針頭之接觸尖端未 能俱皆觸接至測試對象時’測試結果將產生誤差。此外， 是種半導體裝置1均採用價昂之植球機進行銲球14之植 接’使植接銲球之成本成為整體封裝成本顯著之一環，而 不利於成本之降低；且銲球14植接至基板丨丨上後，各焊 球底端所構成之平面的平面的平面度（planarity)不易控 制，而會造成半導體裝置1與外部裝置間之黏接品質無法 有效提升。 [發明概述] 本發明之一目的即在提供一種整體厚度得有效降低之 薄型半導體裝置及其製法。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ί *1 n I - 16083 經濟部智慧財產局員工消費合作钍"裂 16083 Λ7 一 —________B7 五、發明說明（4 ) 本發明之另—目的在提供一種基板厚度得減少以降低 材料成本之薄型半導體裝置及其製法。 本發明之再一目的在提供一種基板毋須敷設拒銲劑而 得降低基板成本之薄型半導體裝置及其製法。 本發明之又一目的在提供一種在高溫環境下不會翹曲 而避免半導體晶片與基板間出現剝離現象及基板本身間發 生脫層之薄型半導體裝置及其製法。 本發明之再一目的在提供一種得提升測試準確度之薄 型半導體裝置及其製法 本發明之又一目的在提供一種不會產生習知銲球植接 後有銲球底端平面度不佳而影響至銲球與外部裝置黏接品 質之問題的薄型半導體裝置及其製法。 依據本發明上揭及其它目的所提供之薄型半導體裝 置，係包括：一基板，其具有至少一開孔，並為一基層及 多數導電跡線所構成；一半導體晶片，其具有一作用表面 及一相對之非作用表面，該半導體晶片並以其作用表面黏 接至基板之基層上；多數之第一導電元件，用以通經該開 孔而電性連接該半導體晶片與基板之導電跡線：多數成陣 列方式排列之第二導電元件，其係設於各導電跡線之終端 上’以供該半導鸯晶片藉之與外界電-性連接；—第一躍體， 其係形成於該基板之基層上以包覆該半導體晶片；以及一 第二膠體‘其係形成於該基板之導電跡線上以完全覆蓋住 該導電跡線、第一導電元件及開且該第二膠體成型後 係包覆住該第二導電元件但使該第二導電元件之底端外 裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 452903 A7 B7 五、發明說明（5 ) 露出該笫二勝體之底面，並令戈導電第 二膠體之底面位^於一平面0 該第二導電元件得為以锡為材料製成之銲球（Solder Bali)或銅、鋁、銅合金、鋁合金或錫/紹合金材料製成之& 塊（Lump)。當該第二導電元件為銲球型態時，其得以習用 之植球機植接至基板之導電跡線上；而當其為凸塊之型態 時’該凸塊則得以一般之印刷或電鍍方式設於該基板之導 電跡線上。 該半導體晶片得完全為該第一膠體所包覆或將該半導 體晶片之非作用表面外露出該第—膠體之頂面，同時，該 半導趙晶片之非作用表面上得接設有一散熱片，以提升本 發明半導體裝置之散熱效率。在不欲因散熱片之加設而使 本發明之半導體裝置之厚度增加的情形下，得將一導熱性 佳之金屬材料製成之散熱片黏設於基板之基層上，並使該 半導趙晶片容置於一該散熱片上開設之槽孔中，故該散熱 片之裝設方式不會造成半導體置之整體厚度的增加。 該基板於開設有一開孔時，所適用之半導體晶片為中 央銲墊式（Central Pad Type)者，使該半導體晶片之鲜整均 外露於基板之開孔中，以供如金線之第一導電元件穿經該 開孔與之銲接；當基板開設有二平行對置之開孔時，則適 用於具雙邊鋒整式（Double-Sided Pad Type)之半導體B 片’使半導體晶片相對側邊上之銲墊分別外露於基板之對 應開孔中；而當基板開設有四個呈矩形列置之開孔時，則 適用周邊銲墊式（Peripheral Pad Type)之半導體晶片，以 (請先閲讀背面之注意事項再填寫本I) 經濟部智慧財產局員工消費合作杜印製According to the "Consumption of Employees of the Ministry of Intellectual Property Bureau" 51 S 1608? Λ 5 2 9 〇3 a: _____ Β7 V. Description of the Invention (3) Due to the thin thickness of the semiconductor device 1, the semiconductor device 1 uses surface adhesion technology ( (Surface Mounting Technology) and other conventional methods such as printed circuit boards and other external devices (External Devices), the high temperature generated during the bonding operation will affect the semiconductor device 1 with different thermal expansion coefficient (CTE) of the substrate 11 and The thermal stress effect produced by the glue Zhao 15 'tends to cause warpage of the semiconductor device 1 and cause the phenomenon of delamination between the semiconductor wafer 10 and the substrate η and the delamination of the fascia board U itself. It also affects the quality of the electrical connection between the semiconductor device 1 and the external device. If you want to reduce the occurrence of warping, although the thickness of the substrate must be increased to resist the effects of thermal stress, this will increase the cost of the substrate. The “outside” will still increase the overall thickness. At the same time, when the semiconductor device 1 is tested after the packaging operation is completed, most of the test pins (not shown) contact the tip Because the bottom of the solder ball 14 is spherical, there may be a situation where the bottom of the solder ball 14 cannot be fully touched. "When the contact tips of the test needle are not all touching the test object," the test results will produce errors. In addition, this type of semiconductor device 1 uses an expensive ball-planting machine for the implantation of the solder balls 14 so that the cost of the implanted solder balls becomes a significant part of the overall packaging cost, which is not conducive to reducing the cost; After being connected to the substrate, the planarity of the plane formed by the bottom end of each solder ball is not easy to control, and the quality of the adhesion between the semiconductor device 1 and the external device cannot be effectively improved. [Overview of the Invention] It is an object of the present invention to provide a thin semiconductor device and a method for manufacturing the same that have a reduced overall thickness. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (please read the precautions on the back first) (Fill in this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * 1 n I-16083 Consumption Cooperation of the Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs 裂 16083 Λ7 1 — ________B7 5 4. Description of the invention (4) Another object of the present invention is to provide a thin semiconductor device with a reduced substrate thickness to reduce material costs and a method for manufacturing the same. Yet another object of the present invention is to provide a substrate without reducing the cost of the substrate without the need for a solder resist. It is another object of the present invention to provide a thin semiconductor device that does not warp in a high-temperature environment, avoids peeling between a semiconductor wafer and a substrate, and delamination between the substrate itself, and a method for manufacturing the same. Yet another object of the present invention is to provide a thin semiconductor device capable of improving test accuracy and a method for manufacturing the same. Another object of the present invention is to provide a flatness of the bottom end of the solder ball which is not good after conventional solder ball implantation. A thin semiconductor device that affects the problem of the bonding quality between the solder ball and an external device, and a manufacturing method thereof. A thin semiconductor device provided according to the invention disclosed above and other purposes includes: a substrate having at least one opening and consisting of a base layer and a plurality of conductive traces; a semiconductor wafer having an active surface and A relatively non-active surface, the semiconductor wafer is adhered to the base layer of the substrate with its active surface; most first conductive elements are used to electrically connect the conductive traces of the semiconductor wafer and the substrate through the opening. : Most of the second conductive elements arranged in an array are arranged on the terminals of the conductive traces, so that the semiconductor chip can be electrically-connected to the outside by the semiconductor;-the first jumper, which is formed at The base layer of the substrate is used to cover the semiconductor wafer; and a second colloid is formed on the conductive trace of the substrate to completely cover the conductive trace, the first conductive element, and the second colloid. It covers the second conductive element but makes the bottom end of the second conductive element externally -------- order --------- (Please read the precautions on the back before filling (This page) 452903 A7 B7 V. Hair Explanation (5) The bottom surface of the second body is exposed, and the bottom surface of the conductive second gel is placed on a plane. The second conductive element may be a solder ball (Solder Bali) or copper made of tin. &Amp; Lump made of aluminum, copper alloy, aluminum alloy or tin / sauer alloy material. When the second conductive element is in the form of a solder ball, it can be implanted on the conductive traces of the substrate using a conventional ball planter; and when it is in the form of a bump, the bump can be printed or plated in general. The mode is set on the conductive trace of the substrate. The semiconductor wafer may be completely covered by the first colloid or the non-active surface of the semiconductor wafer may be exposed to the top surface of the first colloid. At the same time, a non-active surface of the semiconductor wafer may be provided with a heat sink. To improve the heat dissipation efficiency of the semiconductor device of the present invention. In the case that the thickness of the semiconductor device of the present invention is not increased due to the addition of a heat sink, a heat sink made of a metal material with good thermal conductivity may be adhered to the base layer of the substrate, and the semiconductor chip The chip is accommodated in a slot formed on the heat sink, so the mounting method of the heat sink does not cause the overall thickness of the semiconductor chip to increase. When the substrate is provided with an opening, the applicable semiconductor wafer is a Central Pad Type, so that the freshness of the semiconductor wafer is exposed in the opening of the substrate for the first place like a gold wire The conductive element passes through the opening and is soldered to it; when the substrate is provided with two parallel opposite openings, it is suitable for a semiconductor B chip with a Double-Sided Pad Type to make the semiconductor wafer on the opposite side The solder pads are respectively exposed in the corresponding openings of the substrate; when the substrate is provided with four rectangular rows of openings, a peripheral pad type semiconductor wafer is applicable. (Please read the back first For the matters needing attention, please fill out this I) Duplicate printing of employee cooperation in the Intellectual Property Bureau of the Ministry of Economic Affairs

本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公茇 5 16083 經濟部智慧財產局員工消費合咋社^ ¾ A7 B7 五、發明說明（6 ) 半導體晶片上各邊之銲墊外露於基板對應之開孔中。 [圖式簡單說明] 以下茲以較佳具體例配合所附圖式進一步詳述本發明 之特點及功效。 第1圖係本發明第一實施例之薄型半導體裝置之剖視 TS] 4 圓 ， 第2圖係本發明第一實施例之薄型半導體裝置之上視 rm · 圍， 第3A至3H圖係顯示本發明第一實施例之薄型半導體 裝置之製程示意圖； 第4A至4B圖係顯示本發明第一實施例之薄型半導體 裝置之另一製程示意圖； 第3圖係本發明第二實施例之薄型半導體裝置之剖視This paper size is in accordance with Chinese National Standard (CNS) A4 specifications (210 X 297 Gong 5 16083 Consumers' Union of Intellectual Property Bureau of the Ministry of Economic Affairs ^ ¾ A7 B7 5. Description of the invention (6) Exposed pads on each side of the semiconductor wafer In the corresponding holes of the substrate. [Brief description of the drawings] The following is a detailed description of the features and effects of the present invention with better specific examples and the accompanying drawings. Figure 1 is a thin semiconductor device according to the first embodiment of the present invention. Sectional cut TS] 4 circles, FIG. 2 is a top view of the thin semiconductor device according to the first embodiment of the present invention as viewed from the top, and FIGS. 3A to 3H are schematic diagrams showing the manufacturing process of the thin semiconductor device according to the first embodiment of the present invention; 4A to 4B are schematic diagrams showing another process of the thin semiconductor device according to the first embodiment of the present invention; and FIG. 3 is a sectional view of the thin semiconductor device according to the second embodiment of the present invention.

SJ 圍， 第6圖係本發明第三實施例之薄型半導體裝置之剖視FIG. 6 is a cross-sectional view of a thin semiconductor device according to a third embodiment of the present invention.

IS 團， 圖係本發明第四實施例之薄型半導體裝置之剖視 圖： 第 8 (¾ _ 保本發明第五實施例之薄型半導體裝置之剖視 圖； 第圖係本發明第五實施例之薄型半導體裝置之上 圖 第丨0圈格丄 係'本發明第六實施例之薄型半導體裝置 視圖： .?、.λ m 適用 b -------------裝---------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 452903 五、發明說明（7 ; 第11圖係本發明第六實施例之薄型半導體裝置之上 視圖；以及 (請先閲讀背面之注意事項再填寫本頁) 第12圖係習知半導體裝置之剖視圖。 [發明詳細說明] 施例 苐I圖所示者為本發明第一實施例之薄型半導趙裝置 的剖視圖。如圖所示，第一實施例之半導體裝置2，係包 括有一半導體晶片20’供該半導體晶片2〇黏接用之基板 21 ’用以電性連接該半導體晶片20與基板21之金線22， 形成於該基板21上方之上膠體23,植佈於該基板21下方 且成陣列方式（Arrayed)排列之多數鲜球24，以及形成於該 基板21下方上之下膠體25« 經濟部智慧財產局員工消費合作社印製 該半導鍾晶片20具有一作用表面200及一相對之非作 用表面201 ’於該作用表面2 00中央之位置上設有二排平 行並列之多數銲墊202。該半導體晶片20係以作用表面2〇〇 朝下之方式藉如銀膠之膠黏劑或聚亞醯胺膠片（p〇1yijnide Tape)等習知黏著介質黏接至該基板21上之預設位置。為 降低後續製程之溫度循環中產生於半導體晶片20與基板 21間之接面應力’所使用之膠黏劑或膠片宜由熱塑性 (Thermoplastic)或熱彈性（Thermoelastic)樹脂材料製成。 該基板21係由一基層210及一佈設於該基層210底面 上之多數導電跡線211所構成》適用於該基層210之材料 為如環氧樹脂、聚亞醯胺樹脂、二順丁婦二醞胺三嗪 (Bismaleimidetriaxine)樹脂、FR4樹脂、環氧樹脂玻璃、 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 7 16083 經濟部智慧財產局員工消费合作.吐印s 1608 3 A7 ___B7______ 五、發明說明（8 ) 陶瓷材料或耐高溫紙材等，該半導體晶片2 0即藉膠黏劑或 膠片黏著至該基層210上。該導電跡線211 —般係由銅猪 所形成者，各導電跡線211之終端设有供輝球24植接之銲 墊2lla，而其始端亦形成有供金線22銲接之銲塾2Ub。 該基板21之導電跡線211由於係完全為下膠體25所覆蓋 而與外界氣密隔離，故毋須於基板21之底面上敷設一拒鲜 劑層，並得降低基板21之製造成本；同時，該基板21之 頂面及底面分別形成有上膠體23及下膠體25，將其爽設 於上膠體23及下膠體25間，由於上膠體23與下移體25 係呈上下對應之關係，會使後續封裝製程之溫度循環中產生 之熱應力效應大幅降低，而有效避免封裝完成之製成品發 生翹曲現象，並得進而有效降低基板21與半導體晶片2〇 間出現剝離的機率，故能提高製成品之良率。此外，由於 基板21係夹設於上膠體23與下膠體25間，且此一結構能 有效避免翹曲之發生而毋須藉基板21之厚度來增強製成 品之機械強度，所以’該基板2 1得予以薄化而較習用者之 厚度為薄’故除能降低基板21之製造成本，復使製成品之 整體厚度能進一步減少。 該基板2 1復於中央部位開設有一開孔2丨2 ’供該半導 體晶片20黏接至該基板21之基層210上後，該半導體晶 片20之作用表面200上之銲墊202得外露於該開孔212 中’俾利金線2 2得穿經該開孔2 1 2而分別端接於該丰導體 晶片20之録墊202及導電跡線2〖1之銲墊2 1 lb間，以藉 之電性運接該半導體晶片20與導電跡線2 1丨^ τ —1 Ire---Hi i n ^^1 I i HI i n i _: n -EP n I 一、I t * _ , * I (請先閱讀背面之沒意事項再填窵本頁) 經濟部智慧財產局員工消費合作社印製 Λ5290 3 A7 _____B7 五、發明說明（9 ) 該上膠體23及下膠體25係由如環氧樹脂等封裝材料 形成者。該下膠體25於基板21之底面上形成後，係完全 包覆該導電跡線211、金線22及開孔212,使該導電跡線 21卜金線22及半導體晶片20之作用表面2 00均與外界氣 密隔離；同時’該下膠體25之形成方式係令該銲球24之 底端240外露出該下膠體25之底面250,如第2圖所示， 且使該銲球24之底端240與該下膠體25之底面2 50位於 同一平面上。此一設計在使銲球24之底端240之平面度得 以保持，俾利半導體裝置與如印刷電路板之外部裝置電性 連接時之作業品質；且因各銲球24之底端240係呈平面狀 而非習用者之球面狀，於測試時，測試針頭上之接觸尖端 即能俱皆觸接至銲球24之底端240,故不致因觸接不完全 而產生測試誤差；再者，該下膠體25包覆該銲球24後， 兩者黏結成為一體’故可藉研磨或其它適用之方式處理本 發明半導體裝置之底面，一方面使下膠鱧25之底面250 及銲球24之底端240所在之平面形成良好之平面度，另一 方面則使該下膠體25之厚度薄化到足以避免金線22之線 弧頂點220不致外露出下膠體25之程度，亦即，該輝球 24之底端240僅須略高於金線22之線弧頂點220即可， 所以，本發明之銲球24高度得遠低於習用者，而使本發明 之半導體裝置的整體厚度得小於習知之BGA半導體裝 置’並達到薄型化之需求。此外，該銲球24係以陣列方式 植接於導電跡線211之終端’故能提供該半導體晶片20 足夠之I/O連接端。 m n n n I ^ · n 1 I 一 · n I- I i I n (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 497公爱） 9 16083The IS group is a cross-sectional view of a thin semiconductor device according to a fourth embodiment of the present invention: The eighth (¾__) cross-sectional view of a thin semiconductor device that guarantees a fifth embodiment of the present invention; FIG. The circle number 0 in the figure above is a view of the thin semiconductor device of the sixth embodiment of the present invention:.?, .Λ m for b ------------- installation ------ --- Order --------- Line (Please read the precautions on the back before filling out this page) 452903 V. Description of the invention (7; Figure 11 shows the thin semiconductor device of the sixth embodiment of the present invention Top view; and (Please read the precautions on the back before filling out this page) Figure 12 is a cross-sectional view of a conventional semiconductor device. [Detailed description of the invention] The embodiment shown in Figure 1 is a thin type of the first embodiment of the present invention A cross-sectional view of a semiconductor device. As shown in the figure, the semiconductor device 2 of the first embodiment includes a semiconductor wafer 20 ′ for bonding the semiconductor wafer 20 to a substrate 21 ′ for electrically connecting the semiconductor wafer 20. The gold wire 22 with the substrate 21 is formed on the substrate 21 above the colloid 23, and is planted in the cloth. Most of the fresh balls 24 arranged in an array (Arrayed) below the substrate 21, and colloids 25 formed above and below the substrate 21 «printed by the consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the semiconductor chip 20 has a working surface 200 and an opposite non-acting surface 201 'are provided at the center of the active surface 2 00 with two rows of parallel most pads 202. The semiconductor wafer 20 is borrowed silver with the active surface 200 facing downward. Adhesives such as glue or polyimide tape (p〇1yijnide Tape) are used to adhere to a predetermined position on the substrate 21. In order to reduce the temperature cycle of subsequent processes, the semiconductor wafer 20 and the substrate 21 are generated. The adhesive or film used for the intermolecular stress should be made of thermoplastic or thermoelastic resin material. The substrate 21 is composed of a base layer 210 and a majority disposed on the bottom surface of the base layer 210 "Conducting traces 211" The materials suitable for the base layer 210 are, for example, epoxy resin, polyimide resin, bisbutylimide triaxine resin, FR4 resin, epoxy resin The dimensions of glass and paper are applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 7 16083 Consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs. Print 1608 3 A7 ___B7______ 5. Description of invention (8) Ceramic material or resistant High-temperature paper, etc., the semiconductor wafer 20 is adhered to the base layer 210 by an adhesive or a film. The conductive traces 211 are generally formed of copper pigs, and the ends of each conductive trace 211 are provided with glow. The welding pad 2111 of the ball 24 is planted, and a welding pad 2Ub for welding the gold wire 22 is formed at the beginning. Since the conductive traces 211 of the substrate 21 are completely covered by the lower colloid 25 and are air-tightly isolated from the outside, it is not necessary to lay a freshener layer on the bottom surface of the substrate 21 and reduce the manufacturing cost of the substrate 21; The upper colloid 23 and the lower colloid 25 are formed on the top surface and the bottom surface of the substrate 21, respectively. The upper colloid 23 and the lower colloid 25 are placed between the upper colloid 23 and the lower colloid 25. The thermal stress effect generated in the temperature cycle of the subsequent packaging process is greatly reduced, and the warped phenomenon of the finished product can be effectively avoided, and the probability of peeling between the substrate 21 and the semiconductor wafer 20 can be effectively reduced, which can improve the Yield of finished products. In addition, since the substrate 21 is sandwiched between the upper colloid 23 and the lower colloid 25, and this structure can effectively avoid the occurrence of warping without relying on the thickness of the substrate 21 to enhance the mechanical strength of the finished product, so 'the substrate 2 1 It can be thinned and the thickness is thinner than conventional users, so in addition to reducing the manufacturing cost of the substrate 21, the overall thickness of the finished product can be further reduced. The substrate 21 is provided with an opening 2 ′ 2 ′ at the central portion for the semiconductor wafer 20 to be adhered to the base layer 210 of the substrate 21, and the pads 202 on the active surface 200 of the semiconductor wafer 20 are exposed to the surface. In the opening 212, the “俾 利 金 线 2 2” must pass through the opening 2 1 2 and be terminated at the recording pad 202 and the conductive trace 2 〖1 of the bonding pad 2 1 1 lb respectively. The semiconductor wafer 20 and the conductive trace 2 are electrically connected by this. 1 1 ^ τ -1 Ire --- Hi in ^^ 1 I i HI ini _: n -EP n I I, I t * _, * I (Please read the unintentional matter on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ5290 3 A7 _____B7 V. Description of the invention (9) The upper colloid 23 and lower colloid 25 are made of epoxy resin And other packaging materials. After the lower colloid 25 is formed on the bottom surface of the substrate 21, the conductive trace 211, the gold wire 22, and the opening 212 are completely covered, so that the conductive trace 21, the gold wire 22, and the active surface of the semiconductor wafer 20 are 00 Both are hermetically isolated from the outside; at the same time, the formation method of the lower colloid 25 is such that the bottom end 240 of the solder ball 24 is exposed to the bottom surface 250 of the lower colloid 25, as shown in FIG. 2, and the solder ball 24 is The bottom end 240 is located on the same plane as the bottom surface 2 50 of the lower colloid 25. This design maintains the flatness of the bottom end 240 of the solder ball 24, and facilitates the operation quality of the semiconductor device when it is electrically connected to an external device such as a printed circuit board; and because the bottom end 240 of each solder ball 24 is Flat shape instead of the spherical shape of the user. During the test, the contact tip on the test needle can all contact the bottom end 240 of the solder ball 24, so no test error will occur due to incomplete contact; After the lower gel 25 covers the solder ball 24, the two are bonded together to form a single body. Therefore, the bottom surface of the semiconductor device of the present invention can be processed by grinding or other suitable methods. On the one hand, the bottom 250 of the lower gel 25 and the solder ball 24 The plane on which the bottom end 240 is located forms a good flatness, on the other hand, the thickness of the lower colloid 25 is thinned enough to prevent the vertex 220 of the line arc of the gold wire 22 from being exposed to the lower colloid 25, that is, the glow The bottom end 240 of the ball 24 only needs to be slightly higher than the vertex 220 of the arc of the gold wire 22. Therefore, the height of the solder ball 24 of the present invention is much lower than that of a user, so that the overall thickness of the semiconductor device of the present invention is less than Known BGA semiconductor devices' and reach The type of demand. In addition, the solder balls 24 are implanted at the terminals of the conductive traces 211 in an array manner, so they can provide sufficient I / O connection terminals of the semiconductor wafer 20. m n n n I ^ · n 1 I · n I- I i I n (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 497 public love) 9 16083

經濟部智慧財產局員工消費合作吐印S A7 B7 五、發明說明（1()) 第3A至3H圖係本發明第一實施例之薄型半導體裝置 之製程示意圖。 如第3A圖所示，準備該具一基層210及多數導電跡 線2 Π並開設有一開孔2 1 2之基板2 1。 如第3B圖所示’將半導體晶片20以作用表面2 00朝 下（Face Down)之方式藉銀膠或聚亞醯胺膠片黏接至該基 板21之預定位置上’黏接後，該半導體晶片2〇上之銲墊 202將外露於該基板21之開孔212中。 如第3C圖所示’進行銲線作業以將金線22穿經該基板 21之開孔212分別端接至該銲墊202及導電跡線211之銲塾 211b上’而電性連接該半導體晶片20及導電跡線211。 如第3D圊所示，銲線作業完成後，即以習用之點膠 (Glob Top)方式將封裝樹脂25a填注至該開孔212中，迄 該金線22為該封裝樹脂2 5a完全覆蓋為止。 如第3E圖所示，將完成第3D圖所示步驟之結構體置 入封裝模具（Encapsulating Mold，未圖示）中以進行模壓作 業（Transfer Molding)，使熔融之封裝樹脂於基板21之頂 面上固化成型為該上膠體23而將該半導體晶片20包覆。 當然，該模壓方式亦可採其它習知之射出模壓（Injection Molding)或灌注模壓（pour Molding)等方式。 如第3F圖所示，上膠體23形成後，即在該基板21 之導電跡線211之銲墊2〗la上植接銲球24，由於植球作 業為習知者.故在此不另贅述： 如第3 G圖呀示·植球作業完成後_便藉前述之棋壓 16083 --------------裝--------訂---------線 {請先閱讀背面之注意事項再填寫本頁) A7Consumption cooperation of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs S A7 B7 V. Description of the Invention (1 ()) Figures 3A to 3H are schematic diagrams of the manufacturing process of the thin semiconductor device according to the first embodiment of the present invention. As shown in FIG. 3A, the substrate 2 1 having a base layer 210 and a plurality of conductive traces 2 Π and having an opening 2 1 2 is prepared. As shown in FIG. 3B, “the semiconductor wafer 20 is adhered to a predetermined position on the substrate 21 with silver glue or polyurethane film in a way that the action surface is face down”, and the semiconductor The bonding pad 202 on the wafer 20 will be exposed in the opening 212 of the substrate 21. As shown in FIG. 3C, a “wire bonding operation is performed to pass the gold wire 22 through the opening 212 of the substrate 21 to the pad 202 and the pad 211b of the conductive trace 211, respectively” to electrically connect the semiconductor Wafer 20 and conductive traces 211. As shown in 3D 圊, after the wire bonding operation is completed, the encapsulating resin 25a is filled into the opening 212 by the conventional Glob Top method. So far, the gold wire 22 has completely covered the encapsulating resin 25a. until. As shown in FIG. 3E, the structure that has completed the steps shown in FIG. 3D is placed in an encapsulating mold (not shown) to perform transfer molding, so that the molten encapsulating resin is placed on top of the substrate 21. The surface is cured and formed into the upper colloid 23 to cover the semiconductor wafer 20. Of course, the molding method may also adopt other conventional methods such as injection molding or pour molding. As shown in FIG. 3F, after the upper colloid 23 is formed, the solder ball 24 is planted on the pad 2a of the conductive trace 211 of the substrate 21. Since the ball implantation operation is known, it is not another here. To repeat: As shown in Figure 3G · After the ball planting operation is completed, we will use the aforementioned chess to press 16083 -------------- install -------- order-- ------ Line (Please read the notes on the back before filling this page) A7

五、發明說明（11 ) 452903 方式於該基板21之底面上形成該下膠體25，使該下膠體 Μ完全蓋覆該導電跡線211及金線22，並亦將該銲球“ 包覆其中而使兩者黏結為一體。該下膠體25之形成亦得採 用印刷技術、塗佈方式或點膠等其它方式為之，並無特定 限制。 最後’如第3H圖所示’以習用之研磨機p自該下膠 趙25的底面朝基板21之方向磨除下膠體25及銲球24， 直迄該下膠體25之厚度及銲球24之高度減少至一預定值 為止，而使.該銲球24之底端240呈平面狀，並使其與下膠 體25之底面250位在同一平面上，且該下膠體25之厚度 仍足以蓋覆該金線22而使金線22不致外露，故而使完成 封裝製程之半導體裝置2(如苐1圖所示）之整體厚度為之 降低。 此外’如第3D圖所示之將金線22預以封裝樹脂25a 覆蓋之步驟得予略除’而直接於金線22銲接後即直接進入 第3E圖所示之上膠體23模壓成型的步驟，如此，將能簡 化本發明半導體裝置之製程。 第4A至4B圈係顯示本發明第一實施例之薄型半導體 裝置之另一封裝製程示意圖。該封裝製程於植球作業前之 步驟均與前述之第3A至3E圖所示者相同，故在本文中不 予贅述亦不另繪示’而係自上膠體23形成後之步驟開始說 明。此外，與前述封裝製程中所示之元件相同者係沿用同 樣之標示符號。 如第4A圖所示’上膠體23形成於基板21之頂面上 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -111 — —— ·1111111« I, -I I — — — — — I f j ! I- I----— — — — It 本紙張尺度適用中關家標^(CNS)A4規格⑽χ挪公爱) 11 16083 A7 B7 五、發明說明（12 ) 後，即以網版印刷技術於導電跡線2 11之銲墊2 1 1 a上塗設 以錫/鉛合金形成之凸塊24…由於該凸塊24'與銲墊2Ua 之接置係藉印刷（或電鍍）方式為之，故可準確地控制凸塊 24'形成後之高度至僅略高於金線22之線弧頂點220，並 使該凸塊24’成型後之底端240'為平面狀者。因該凸塊24ι 得以印刷或電鍍方式形成，毋須價昂之植球機植佈銲球， 故以凸塊24'取代銲球24得大幅降低製造成本。 如第4B圖所示’凸塊2 4,接設完成後，即得以模壓方 式形成完全覆蓋住該導電跡線2U、金線22及開孔212之 下膠體25’該下膠體25並與各凸塊24'黏結為一體而使該 凸塊24'之底端240,外露出下膠體25之底面250,且相同 地令該ώ塊24,之底端240ι與下膠體25之底面25〇位於同 一平面上。同時，由於該凸塊24,之高度係控制在略高於 金線22之線弧頂點220，故該下膠體25之厚度足以蓋覆 住該金線22而使金線22不致外露，遂使下膠體25成型後 赉須研磨以降低其厚度，即能使封裝完成之半導體裝置） 之整體厚度小於習知之BGA半導體裝置之厚度。 第5圖所不者為本發明第二實施例之薄型半導體裝置 之剖視圖。該第二實施例之半導體裝置3之結構大致同於 前述之第一實施例’不同處在於其上膠體33於基板31之 丁黃面上成型後，係使半導體晶片3〇之非作用表面3〇1外露 出該上膠體33之頂面33();此種外露之結構除能使丰導體 晶片30所產生之熱量得直接由其非作用表面3()1逸散至大 氣而提升散熱致率外.並因上膠體33未包覆該半導體晶片 -------------裝--------訂i n* nv HI I— Ifl n I (請先閲讀背面之注意事項再填寫本頁} 1608? 452903 A7 五、發明說明（13 ) 30之非作用表面3〇1，而使半導體裝置3之整體厚度得小 於第一實施例所揭示者。此外，為進一步提升散熱效率’ 得直接於該外露之非作用表面3〇1上外接一散熱片如 第5圖中虛線繪示者）。 第6圖所示者為本發明第三實施例之薄型半導體裝置 之剖視圖。該第三實施例之半導體裝置4之結構大致同於 前述之第一實施例，不同處在於其半導體晶片4〇之非作用 表面401上得在接黏接一散熱片44，使該上膠體43成型 於基板41之頂面上後，該散熱片46得為上膠體43包覆但 使其頂面460外露出上膠體43之頂面43〇，以供該半導髏 aa片40產生之熱量傳遞至該散熱片46後得由該散熱片 46直接逸散至大氣中。當然，該散熱片4ό亦得為上朦體 43所完全包覆。 第7圖所示者為本發明第四實施例之薄型半導體裝置 之剖視圖。該第四實施例之半導體裝置5之結構大致同前 述第一實施例，不同處在於其基板51之基層51〇上復黏設 有一散熱片56。該散熱片56具有一槽孔560,以供該半導 體晶片50通經該槽孔56〇而黏接至基板51之基槽51〇上。 該散熱片56與基板51黏結之方式將使封裝完成之半導體 裝置5的整體厚度與第一實施例所述者相同不致導致厚 度之增加。 第8圈所示者為本發明第五實施例之薄型半導體裝置 之剖視圖。該第五實施例之半導體裝置6之結構大玫同於 —實施例’不同處在於其半導體晶片60係雙邊銲墊 表紙張尺度適用中關家標準（CNS)A4規格（21Q χ 297公餐）- {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 I n n n »1 . 16083 經濟部智慧財產局—工消费合泎钍印製 五、發明說明（14 式者。為配合雙包銲塾式半導體晶片60之使用該基板 61須開設有兩平行對置之開孔612，使該半導體晶“〇 黏接至該基板6丨之基層61〇上後，各邊之銲墊6〇2得外露 出基板61之對應開孔612中’以供金線62分別穿經對應 之開孔612而電性連接該半導體晶片4〇與導電跡線61卜 當然，該半導體晶片6〇之非作用表面得於上膠體Μ成型 後外露出其頂面，由於是種結構得由第5圖所示者輕易推 及’在此將不另重覆㈣1半導體裝置6於完成封裝完 成後各凸塊64之底端640即以陣列方式外露出下膠艘 65之底面650’如第9圖所示。 第10圖所示者為本發明第六實施例之薄型半導體裝 置之剖視圖。該第六實施例之半導趙裝置7之結構大致同 於前述之第一實施例，不同處在於其半導體晶片7〇為周邊 銲墊式者。為配合周邊銲墊式半導體晶片7〇之使用，該基 板71須開設有四道呈矩形列置之 12 7。黏接至該基板71之基層7】。上後，各邊之輝塾導：： 外露於基板7·1之對應開孔712中，以供金線72分別穿經 對應之開孔7 12而電性連接該半導體晶片7〇與導電跡線 。相同地，該半導體晶片7〇之非作用表面亦得外露出 該上膠们U頂面，復得於外露之非作用表面上外接一散 熱片以提升散熱效率，目是種結構得由第5圖所示者輕易 推及 '故亦不予資述。該丰導體裝置，於完成封裝時各 塊’ 4之底端/ 4 〇即以帛丨」圖所示之方式外露出下膠體 75之底面750、 · --------^--------- (請先閱讀背面之注意事項再填寫本頁) 16083V. Description of the invention (11) 452903 The lower colloid 25 is formed on the bottom surface of the substrate 21, so that the lower colloid M completely covers the conductive traces 211 and gold wires 22, and the solder ball is "covered" And the two are bonded together. The formation of the lower colloid 25 can also be achieved by printing, coating or dispensing, and there are no specific restrictions. Finally, as shown in Figure 3H, conventional grinding is used. The machine p grinds the lower colloid 25 and the solder ball 24 from the bottom surface of the lower gel Zhao 25 toward the substrate 21 until the thickness of the lower colloid 25 and the height of the solder ball 24 are reduced to a predetermined value. The bottom end 240 of the solder ball 24 is planar and is on the same plane as the bottom surface 250 of the lower colloid 25, and the thickness of the lower colloid 25 is still sufficient to cover the gold wire 22 so that the gold wire 22 is not exposed. Therefore, the overall thickness of the semiconductor device 2 (as shown in Fig. 1) that has completed the packaging process is reduced. In addition, 'the step of pre-covering the gold wire 22 with the encapsulating resin 25a as shown in Fig. 3D is omitted' And directly after the gold wire 22 is welded, it directly enters the upper colloid 23 as shown in Figure 3E. The molding steps can thus simplify the manufacturing process of the semiconductor device of the present invention. Circles 4A to 4B are schematic diagrams showing another packaging process of the thin semiconductor device according to the first embodiment of the present invention. The packaging process is a step before the ball-planting operation Both are the same as those shown in the aforementioned 3A to 3E, so they will not be described in this article and will not be shown separately, but will be explained from the steps after the formation of the colloid 23. In addition, the same as shown in the aforementioned packaging process The same symbols are used for the same components. As shown in Figure 4A, the upper colloid 23 is formed on the top surface of the substrate 21 (please read the precautions on the back before filling this page). -111 — —— · 1111111 «I, -II — — — — — I fj! I- I ---- — — — — It This paper size is applicable to the Zhongguanjia standard ^ (CNS) A4 specification (⑽χ 挪 公公 爱) 11 16083 A7 B7 V. After the description of the invention (12), the solder pad 2 1 1 a of the conductive trace 2 11 is coated with a bump 24 made of tin / lead alloy by screen printing technology ... 'The connection to the pad 2Ua is by printing (or plating) Therefore, it is possible to accurately control the height of the bump 24 ′ after it is formed to be slightly higher than the vertex 220 of the line arc of the gold wire 22, and make the bottom end 240 ′ of the bump 24 ′ formed into a flat shape. Because the bump 24ι can be formed by printing or electroplating, no expensive ball planting machine is needed to plant the solder balls. Therefore, replacing the solder balls 24 with the bumps 24 'can greatly reduce the manufacturing cost. As shown in FIG. 4B, the bumps 2 4. After the connection is completed, a gel 25 'covering the conductive trace 2U, the gold wire 22, and the opening 212 can be formed in a molding manner, and the lower gel 25 can be bonded to each of the bumps 24' to form a unit. The bottom end 240 of the convex block 24 'exposes the bottom surface 250 of the lower colloid 25, and the bottom end 240m of the free block 24 is located on the same plane as the bottom surface 25 of the lower colloid 25. At the same time, since the height of the bump 24 is controlled to be slightly higher than the vertex 220 of the arc of the gold wire 22, the thickness of the lower colloid 25 is sufficient to cover the gold wire 22 so that the gold wire 22 is not exposed. After the lower colloid 25 is formed, it must be ground to reduce its thickness, that is, the overall thickness of the packaged semiconductor device can be smaller than the thickness of the conventional BGA semiconductor device. 5 is a cross-sectional view of a thin semiconductor device according to a second embodiment of the present invention. The structure of the semiconductor device 3 of this second embodiment is substantially the same as that of the aforementioned first embodiment, except that the colloid 33 is formed on the yellow surface of the substrate 31, and the non-active surface 3 of the semiconductor wafer 30 is formed. 〇1 The top surface 33 () of the upper colloid 33 is exposed; in addition to this exposed structure, the heat generated by the abundant conductor chip 30 can be directly dissipated from the non-active surface 3 () 1 to the atmosphere to improve heat dissipation. Rate. And because the colloid 33 is not coated with the semiconductor wafer ------------------------- order in * nv HI I— Ifl n I (Please read first Note on the back page please fill in this page again} 1608? 452903 A7 V. Description of the invention (13) 30 non-active surface 301, so that the overall thickness of the semiconductor device 3 is smaller than that disclosed in the first embodiment. To further improve heat dissipation efficiency, an external heat sink must be directly attached to the exposed non-active surface 3101 (as shown by the dashed line in Figure 5). Fig. 6 is a sectional view of a thin semiconductor device according to a third embodiment of the present invention. The structure of the semiconductor device 4 of the third embodiment is substantially the same as that of the first embodiment described above, except that a non-active surface 401 of the semiconductor wafer 40 must be adhered to a heat sink 44 to make the upper body 43 After being formed on the top surface of the substrate 41, the heat sink 46 must be covered by the upper colloid 43 but its top surface 460 is exposed to the top surface 43 of the upper colloid 43 for the heat generated by the semiconducting cross section aa sheet 40. After being transferred to the heat sink 46, the heat sink 46 can escape directly into the atmosphere. Of course, the heat sink 4th must be completely covered by the upper body 43. Fig. 7 is a cross-sectional view of a thin semiconductor device according to a fourth embodiment of the present invention. The structure of the semiconductor device 5 according to the fourth embodiment is substantially the same as that of the first embodiment described above, except that a heat sink 56 is adhered to the base layer 51 of the substrate 51. The heat sink 56 has a slot 560 for the semiconductor wafer 50 to pass through the slot 56 and adhere to the base slot 51 of the substrate 51. The manner in which the heat sink 56 is bonded to the substrate 51 will make the overall thickness of the packaged semiconductor device 5 the same as that described in the first embodiment without causing an increase in thickness. The eighth circle is a cross-sectional view of a thin semiconductor device according to a fifth embodiment of the present invention. The structure of the semiconductor device 6 of the fifth embodiment is the same as that of the embodiment. The difference is that the semiconductor wafer 60 is a double-sided pad table paper with a standard of CNS A4 (21Q x 297 meals). -{Please read the notes on the back before filling out this page) Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs I nnn» 1. 16083 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs-Combination of Industry and Consumers In order to cooperate with the use of the double-package soldering type semiconductor wafer 60, the substrate 61 must be provided with two parallel opposite openings 612, so that the semiconductor crystal "0 is adhered to the base layer 61 of the substrate 6", each The side pads 602 can be exposed in the corresponding openings 612 of the substrate 61 to allow the gold wires 62 to pass through the corresponding openings 612 to electrically connect the semiconductor wafer 40 and the conductive trace 61. Of course, the The non-active surface of the semiconductor wafer 60 can be exposed on the top surface of the colloidal M after molding. Because it is a structure, it can be easily pushed by the person shown in FIG. 5 'I will not repeat the semiconductor device 6 here. After the package is completed, the bottom end 640 of each bump 64 starts with The bottom surface 650 'of the lower rubber boat 65 is exposed in a row manner as shown in FIG. 9. The figure 10 is a cross-sectional view of a thin semiconductor device according to a sixth embodiment of the present invention. The semiconductor device 7 of the sixth embodiment The structure is substantially the same as the first embodiment described above, except that the semiconductor wafer 70 is a peripheral pad type. In order to cooperate with the use of the peripheral pad type semiconductor wafer 70, the substrate 71 must be provided with four rectangular shapes. Column 12 is placed 7. Base layer 7 bonded to the substrate 71]. After that, the guides on each side are exposed: exposed in the corresponding openings 712 of the substrate 7.1 for the gold wires 72 to pass through the corresponding The opening 7 12 is electrically connected to the semiconductor wafer 70 and the conductive traces. Similarly, the non-active surface of the semiconductor wafer 70 must be exposed from the top surface of the sizing U, so as to recover the exposed non-action A heat sink is externally connected on the surface to improve the heat dissipation efficiency. The purpose is a structure that can be easily pushed to the 'shown in Figure 5', so it will not be described. The abundance of the conductor device, the bottom of each block when the package is completed / 4 〇 That is, the bottom surface 750 of the lower colloid 75 is exposed as shown in the figure. · ^ -------- --------- (Please read the notes and then fill in the back of this page) 16083

Claims (1)

45290 3 έΐ ____§_ 六、申請專利範圍 1. 一種薄型半導體裝置，係包括： 一基板，其具有至少一開孔，並為一基層及多數之 導電跡線所構成； 一半導體晶片’其具有一作用表面及·一相對之非作 用表面’該半導體晶片係以其作用表面黏接至該基板之 基層上； 多數之第一導電元件，用以通經該基板之開孔而電 性連接該半導體晶片與基板之導電跡線； 多數之第二導電元件，其係設於各該導電跡線之终 端上’以供該半導體晶片藉之與外界電性連結； 一第一膠體，其係形成於該基板之基層上以包覆該 半導體晶片；以及 一第二膠體，其係形成在該基板之導電跡線上以完 全覆蓋住該導電跡線、第一導電元件及開口，且該第二 膠艘係與第二導電元件黏結為一體，而使該第二導電元 件之底端外露出該第二膠體之底面，並令該第二導電元 件之底端與第二膠體之底面位於同—平面。 2_如申請專利範圍第1項之薄型半導體裝置，其中，該第 一導電元件係金線a 3，如申請專利範圍第1項之薄型半導體裝置，其中，該第 一導電元件係辉球。 4.如申請專利範圍第3項之薄型半導體裝置’其中，該銲 球之底端係呈平面狀者，以與該下膠體之底面共平面。 5‘如申請專利範圍第1項之薄型半導體 ，其中，該第 本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公楚 f請先閱讀背面之注意事項再填窝本頁) 訂---------線· 經濟部智慧財產局員工消費合作社印製 15 16083 8 88 29 ABCD 經濟^智慧財產局員工消費合-^^¾ t、申請專利範圍 二導電元件係凸塊。 6. 如申請專利範圍第5項之薄型半導體裝置，其中，該凸 塊係以印刷方式接設至該導電跡線之終端上。 7. 如申請專利範圍第5項之薄型半導體裝置，其中，該凸 塊係以電鍍方式接設至該導電跡線之終端上。 8. 如申請專利範圍第5項之薄型半導體裝置，其中，製成 該凸塊之材料係選自由銅、鋁、銅合金、鋁合金及錫/ 鉛合金所組成之組群之一者。 9. 如申請專利範圍第5項之薄型半導體裝置，其中，該凸 塊之底端係呈平面狀者，以與該下膠體之底面共平面。 10. 如申請專利範圍第1項之薄型半導體裝置，其中，該半 導體晶片之非作用表面係外露出該上膠體之頂面。 Π.如申請專利範圍第1項之薄型半導體裝置，其中，該半 導體晶片之非作用表面係為該上膠體所覆蓋。 12. 如申請專利範圍第1項之薄型半導體裝置，其中，該基 板具有兩平行對置之開孔。 13. 如申請專利範圍第1項之薄型半導體裝置，其中，該基 板具有四道成矩形列置之開孔。 14. 如申請專利範圍第1項之薄型半導體裝置，復包括一與 該半導體晶片之非作用表面接設之散熱片。 15如申請專利範圍第】項之薄型半導體裝置復包括一該 基板之基層黏接之散熱片，其中1該散熱片具有一槽孔 以供該半導體晶片穿經該槽孔而黏接至該基板之基層 [-Λ -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁)45290 3 έΐ ____ §_ VI. Patent application scope 1. A thin semiconductor device comprising: a substrate having at least one opening, which is composed of a base layer and a plurality of conductive traces; a semiconductor wafer 'which has An active surface and an opposite non-active surface. The semiconductor wafer is adhered to the base layer of the substrate with its active surface; most of the first conductive elements are used to electrically connect to the substrate through openings in the substrate. The conductive traces of the semiconductor wafer and the substrate; most of the second conductive elements are provided on the terminals of each of the conductive traces so as to allow the semiconductor wafer to be electrically connected to the outside world; a first colloid, which is formed Covering the semiconductor wafer on the base layer of the substrate; and a second colloid formed on the conductive trace of the substrate to completely cover the conductive trace, the first conductive element and the opening, and the second adhesive The boat is bonded to the second conductive element as a whole, so that the bottom end of the second conductive element is exposed to the bottom surface of the second colloid, and the bottom end of the second conductive element and the first conductive element are bonded together. The bottom surface of the colloid in the same - plane. 2_ If the thin semiconductor device according to item 1 of the patent application scope, wherein the first conductive element is a gold wire a 3, if the thin semiconductor device according to item 1 of the patent application scope, wherein the first conductive element is a glow ball. 4. The thin semiconductor device according to item 3 of the patent application, wherein the bottom end of the solder ball is flat, so as to be coplanar with the bottom surface of the lower colloid. 5 'If you apply for a thin semiconductor in item 1 of the scope of patent application, where the first paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297), please read the precautions on the back before filling this page) Order --------- Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 15 16083 8 88 29 ABCD Piece. 6. For a thin semiconductor device according to item 5 of the application, wherein the bump is connected to the terminal of the conductive trace by printing. 7. For a thin semiconductor device according to item 5 of the application, wherein the bump is connected to the terminal of the conductive trace by electroplating. 8. The thin semiconductor device according to item 5 of the patent application, wherein the material of which the bump is made is selected from one of the group consisting of copper, aluminum, copper alloy, aluminum alloy, and tin / lead alloy. 9. For a thin semiconductor device according to item 5 of the patent application, wherein the bottom end of the bump is planar, so as to be coplanar with the bottom surface of the lower colloid. 10. The thin semiconductor device according to item 1 of the application, wherein the non-active surface of the semiconductor wafer is exposed to the top surface of the upper colloid. Π. The thin semiconductor device according to item 1 of the application, wherein the non-active surface of the semiconductor wafer is covered by the colloid. 12. The thin semiconductor device according to item 1 of the patent application, wherein the substrate has two parallel openings. 13. The thin semiconductor device according to item 1 of the patent application scope, wherein the substrate has four openings arranged in a rectangular array. 14. If the thin semiconductor device according to item 1 of the patent application scope includes a heat sink connected to the non-active surface of the semiconductor wafer. 15 The thin semiconductor device according to item [Scope of the patent application] includes a substrate-attached heat sink, wherein 1 the heat sink has a slot for the semiconductor wafer to pass through the slot to be bonded to the substrate The base layer of [-Λ ------------- installation -------- order --------- line (please read the precautions on the back before filling this page) ) 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 16. 如申請專利範圍第i項之薄型半導鳢裝置，其中適用於 該基層之材料係選自由環氧樹脂，聚亞醯胺樹脂，二順 丁稀—酿胺三嗪樹脂（Bismaleimidetriazine Resin)，FR 4 樹脂、環氧樹脂玻璃、陶瓷材料及抗熱性紙材所組成之 組群之一者。 17. —種薄型半導體裝置之製法，係包括下列步驟： 準備一基板’該基板為一基層及多數導電跡線構 成，並開設有至少一開孔； 黏接一半導艘晶片至該基板之基層的預設位置 上； 以多數第一導電元件穿經該基板之開孔電性連接 該半導體晶片與基板之導電跡線； 於該基板之基房上形成一第一應體以包覆該半導 趙晶片； 於該基板之導電跡線之终端上設置多數成陣列方 式排列之第二導電元件； 於該基板之導電跡線上形成一第二膠體以完全包 覆該導電跡線、第一導電元件及開孔，並使該第二導電 元件與該第二膠體連結為一體，而讓該第二導電元件之 底端外露出第二膠艎之底面，及使該第二導電元件之底 端與該第二膠體之底面位於同一平面。 1 8 _如申請專利範圍第17項之製法，復在形成該第二膠體 之步驟後，予以該第二膠體與第二導電元件減低高度之 處理，以薄化該製成之半導體裝置。 16083 (請先閱讀背面之注意事項再填寫本頁} ^ rlllm — I I ----I ] I - I h I . I 17 Α8 Β8 C3 D8 τ、申請專利範圍 19.如申請專利範圍第17項之製法，其中，該第二導電元 件係銲球。 2 0.如申請專利範圍第19項之製法，其中’該銲球係以植 球機植接至該基板上。 21. 如申請專利範圍第17項之製法，其中，該第二導電元 件係凸塊者。 22. 如申請專利範圍第21項之製法，其中，該凸塊係以印 刷方式接設至該基板上。 23. 如申請專利範圍第21項之製法，其中，該凸塊係以電 鏟方式形成於該基板上。 24. 如申請專利範圍第18項之製法，其中，該減低第二膠 體與第二導電元件高度之處理係以研磨方式為之。 25. 如申請專利範圍第17項之製法，復在該第一導電元件 電性連接該半導體晶片與基板之導電跡線之步驟後，以 封裝樹脂預包覆該第一導電元件而將該第一導電元件 與外界氣密隔離。 ----------------------訂.---Η----I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合咋社印製 1608?Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 6. Scope of patent application. For example, the thin semiconductor device in the scope of application for item i. The material suitable for the base layer is selected from epoxy resin, polyurethane resin. , Bismaleimide triazine resin (Bismaleimidetriazine Resin), FR 4 resin, epoxy glass, ceramic materials and heat-resistant paper is one of the group. 17. —A method for manufacturing a thin semiconductor device, which includes the following steps: preparing a substrate 'the substrate is composed of a base layer and a plurality of conductive traces, and is provided with at least one opening; and a half of the pilot wafer is bonded to the base layer of the substrate At a predetermined position; electrically connecting the semiconductor wafer with the conductive traces of the substrate through a plurality of first conductive elements passing through the openings of the substrate; forming a first responder on the base room of the substrate to cover the half Guide the wafer; set a plurality of second conductive elements arranged in an array on the terminals of the conductive traces of the substrate; form a second gel on the conductive traces of the substrate to completely cover the conductive traces, the first conductive Element and opening, and the second conductive element and the second gel are connected as a whole, so that the bottom end of the second conductive element is exposed to the bottom surface of the second rubber capsule, and the bottom end of the second conductive element It is located on the same plane as the bottom surface of the second colloid. 1 8 _ If the method of applying for the scope of patent application No. 17 is repeated after the step of forming the second colloid, the second colloid and the second conductive element are reduced in height to thin the fabricated semiconductor device. 16083 (Please read the notes on the back before filling out this page} ^ rlllm — II ---- I] I-I h I. I 17 Α8 Β8 C3 D8 τ, scope of patent application 19. If item 17 of scope of patent application The manufacturing method, wherein the second conductive element is a solder ball. 20. The manufacturing method according to item 19 of the patent application scope, wherein 'the solder ball is planted on the substrate by a ball planter. 21. If the patent scope is applied The manufacturing method according to item 17, wherein the second conductive element is a bump. 22. The manufacturing method according to item 21 of the patent application scope, wherein the bump is connected to the substrate by printing. 23. If applying The manufacturing method of item 21 of the patent, wherein the bump is formed on the substrate by a power shovel. 24. The manufacturing method of item 18 of the application, wherein the height of the second colloid and the second conductive element is reduced. The processing is performed by grinding. 25. If the manufacturing method of the 17th scope of the patent application is applied, after the step of electrically connecting the first conductive element to the semiconductor wafer and the conductive traces of the substrate, the resin is pre-coated with the encapsulation resin. First conductive element The items are hermetically isolated from the outside world. ---------------------- Order .--- Η ---- I (Please read the notes on the back before filling (This page) Printed by the Consumer Goods Corporation of the Intellectual Property Bureau of the Ministry of Economic Affairs, 1608?
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165566A (en) * 2011-12-19 2013-06-19 先进封装技术私人有限公司 Substrate structure, semiconductor package device, and manufacturing method of semiconductor package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165566A (en) * 2011-12-19 2013-06-19 先进封装技术私人有限公司 Substrate structure, semiconductor package device, and manufacturing method of semiconductor package
CN103165566B (en) * 2011-12-19 2016-02-24 先进封装技术私人有限公司 The manufacture method of board structure, semiconductor package part and semiconductor package part
US9723717B2 (en) 2011-12-19 2017-08-01 Advanpack Solutions Pte Ltd. Substrate structure, semiconductor package device, and manufacturing method of semiconductor package
US10154588B2 (en) 2011-12-19 2018-12-11 Advanpack Solutions Pte Ltd. Manufacturing method of semiconductor package

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