CN1168139C - Thin semiconductor device and its preparing process - Google Patents
Thin semiconductor device and its preparing process Download PDFInfo
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- CN1168139C CN1168139C CNB001234102A CN00123410A CN1168139C CN 1168139 C CN1168139 C CN 1168139C CN B001234102 A CNB001234102 A CN B001234102A CN 00123410 A CN00123410 A CN 00123410A CN 1168139 C CN1168139 C CN 1168139C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to a thin semiconductor device. The present invention comprises a base plate with openings, the base plate is composed of a base layer and a plurality of conductive traces, the base layer is used for gluing the acting surface of a semiconductor wafer, a plurality of first conductive elements are electrically connected with the semiconductor wafer and the conduct traces through the openings, and second conductive elements are arranged on the terminal of each conductive trace; a first colloid is formed on the base layer, and a second colloid is formed on the conductive traces of the base plate; after being formed, the second colloid covers the second conductive element; the bottom of the second conductive element is exposed out of the bottom surface of the second colloid, so the bottom of the second conductive element is positioned in the same plane with the bottom surface of the second colloid.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly a kind of semiconductor chip is by becoming the conducting element of array way planting on substrate bottom surface and the extraneous semiconductor device that is electrically connected.
Background technology
Ball grid array (BGA) semiconductor device (Ball Grid Array Semiconductor Device) has become to encapsulate one of main product recently, its reason is the structure of this kind by becoming the soldered ball (Solder Ball) of array way planting on substrate bottom surface to connect for semiconductor chip and for example printed circuit board (PCB) electric lotus roots of external device such as (PCB), with respect to traditional semiconductor device based on lead frame (Leadframe-Based), the former needs to be provided with the soldered ball that link (I/O wed Connectoins) was exported/gone in more conduct in unit are, and the distance between soldered ball (Pitch) also can effectively be reduced, and the structure of this BGA semiconductor device can be met have more electronic component the demand of the semiconductor chip of (Electronic Components) and electronic circuit (Electrical Circuits).
Above-mentioned known BGA semiconductor device is when being electrically connected the bonding wire operation (Wire Bond) of the semiconductor chip substrate bonding with supplying this semiconductor chip with plain conductor (Gold Wires), bonding equipment is action face (the Active Surface at semiconductor chip, promptly be formed with the surface of electronic component and electronic circuit) weld pad (Bond Pad) go up to burn ball after, plain conductor is drawn one suitably apart from the weld that outwards is pulled down to again on the substrate earlier, make the summit of bank (Wire Loop) exceed the action face of semiconductor chip, and the summit that causes must being higher than in order to the end face of the resin colloid (ResinErcapsulant) that coats semiconductor chip and plain conductor this bank can avoid plain conductor to expose.Like this, the thickness of the semiconductor device that encapsulation is finished promptly can be subjected to the restriction of bank height, and is unfavorable for the slimming of semiconductor device.
For solving the shortcoming of above-mentioned known BGA semiconductor device on thickness, just there is a kind of slim BGA semiconductor device to give birth to, as shown in figure 12 because of fortune.This slim BGA semiconductor device 1, be on for the semiconductor chip 10 sticking substrates of establishing 11, to form a perforate 110, pass through from this perforate 110 for the plain conductor 12 that is electrically connected the conductive trace (Conductive Traces) 111 on this semiconductor chip 10 and the substrate 11; After the welding of this plain conductor 12 is finished, be that potting resin (Encapsulating Resin) with for example epoxy resin (Epoxy) etc. envelopes this plain conductor 12 and forms colloid 13 with perforate 110, because the part of the bank of this plain conductor 12 is highly absorbed by substrate 11, the bank summit 120 that makes plain conductor 12 is only a little more than the bottom surface of substrate 11, exposed outside the height h of bottom surface of this substrate 11 less than planting the height H that is connected to the soldered ball 14 on these substrate 11 bottom surfaces so control this time colloid 13.Thereby, need not contain the bank summit to the distance between the action face of semiconductor chip in order to the height after last colloid 15 formation that coat this semiconductor chip 10, so the more above-mentioned known BGA semiconductor device of thickness of the semiconductor device after encapsulation is finished is changed to little.
Though above-mentioned semiconductor device shown in Figure 12 1 can effectively reduce integral thickness and reach purpose of thinness, but contact for avoiding conductive trace 111 on the substrate 11 to expose with atmosphere, must on the bottom surface of this substrate 11, lay one and refuse solder flux (Solder Mask) layer 112, the manufacturing cost of substrate 11 and the complexity of manufacturing process are all increased thereupon to cover conductive trace 111 fully; Yet the use of refusing welding flux layer 112 produces hygroscopic misgivings with other, if desire effectively solves hygroscopic problem, can further increase the manufacturing cost of substrate 11.Again and, this semiconductor device 1 is because the thickness slimming, when it for example is bonded to external device (ED) (External Devices) such as printed circuit board (PCB) by surface adhering technology known manner such as (Surface Mounting Technology), the high temperature that bonding process is produced in carrying out can act on the substrate 11 and last colloid 15 of semiconductor device 1 tool different heat expansion coefficient (CTE), the thermal stress effects that produces often easily causes semiconductor device 1 that warpage (Warpage) takes place and causes semiconductor chip 10 and 11 of substrates to peel off delamination between (Delamination) phenomenon and substrate 11 itself, and has influence on the quality that is electrically connected of semiconductor device 1 and external device (ED).If wish to reduce the generation probability of warping phenomenon, must increase of the influence of the thickness of substrate 11, but this measure except making the cost raising of substrate, meeting also will cause the increase of integral thickness with the opposing thermal stress.Simultaneously, when packaging operation is finished and semiconductor device 1 is tested, several contact tips in test syringe needle (not shown) are easily because of the dome shape that the bottom is of soldered ball 14, and the situation of the bottom of soldered ball 14 can take place all to touch, when the contact tip of test syringe needle fails all to touch tested object, test result will produce error.In addition, this semiconductor device 1 all adopts expensive ball attachment machine to carry out planting of soldered ball 14 and connects, and makes to plant the cost that connects soldered ball and become the significant ring of overall package cost, and is unfavorable for the reduction of cost; And after soldered ball 14 was planted and is connected on the substrate 11, the flatness (Planarity) on the plane that each soldered ball bottom is constituted was wayward, and can cause the bonding quality between semiconductor device 1 and the external device (ED) effectively to improve.
Summary of the invention
The object of the present invention is to provide thin semiconductor device that a pair of integral thickness can effectively reduce and preparation method thereof.
Another object of the present invention is to provide a kind of substrate thickness can reduce thin semiconductor device to reduce material cost and preparation method thereof.
A further object of the present invention is to provide a kind of substrate to lay to refuse solder flux and can reduces thin semiconductor device of substrate cost and preparation method thereof.
Another purpose of the present invention be to provide a kind of can warpage under hot environment and avoid occurring between semiconductor chip and substrate peeling off thin semiconductor device that delamination takes place between phenomenon and substrate itself and preparation method thereof.
A further object of the present invention is to provide a kind of can improve thin semiconductor device of test accuracy and preparation method thereof.
Another purpose of the present invention is to provide a kind of and can produce known soldered ball and plant and do not have after connecing soldered ball bottom flatness good and have influence on the thin semiconductor device and preparation method thereof of the problem of soldered ball and the bonding quality of external device (ED).
Above-mentioned purpose of the present invention realizes that in the following manner a kind of thin semiconductor device comprises: a substrate, and it has at least one perforate, and is made of a basic unit and several conductive traces; The semiconductor chip, it has an action face and a relative non-action face, and this semiconductor chip also is bonded to its action face in the basic unit of substrate; Several first conducting elements are electrically connected the conductive trace of this semiconductor chip and substrate in order to stimulate the menstrual flow this perforate; Second conducting element that several become array way to arrange, it is arranged on the terminal of each conductive trace, is electrically connected by itself and the external world for this semiconductor chip; One first colloid, it is formed in the basic unit of this substrate to coat this semiconductor chip; And one second colloid, it is formed on the conductive trace of this substrate to cover this conductive trace, first conducting element and opening fully, and envelope this second conducting element after this second colloid moulding, but the bottom that makes this second conducting element exposes outside the bottom surface of this second colloid, and makes the bottom of this second conducting element and the bottom surface of second colloid be positioned at same plane.
This second conducting element must be to be the projection (Lump) that the soldered ball (Solder Ball) made of material or copper, aluminium, copper alloy, aluminium alloy or tin/lead alloy material are made with tin.When this second conducting element was the soldered ball kenel, it can be planted on the conductive trace of receiving substrate with general ball attachment machine; And when it was the kenel of projection, this projection then can be arranged on the conductive trace of this substrate with general printing or plating mode.
This semiconductor chip can be entirely this first colloid and coat the end face that maybe the non-action face of this semiconductor chip is exposed outside this first colloid, simultaneously, can be equipped with a fin on the non-action face of this semiconductor chip, to improve the radiating efficiency of semiconductor device of the present invention.Under the situation that the thickness of not wishing to make because of adding of fin semiconductor device of the present invention increases, the fin of can the metal material that a thermal conductivity is good making is sticking to be located in the basic unit of substrate, and this semiconductor chip is placed in the slotted eye of offering on this fin, so the installing mode of this fin can not cause the increase of the integral thickness that semiconductor puts.
This substrate is when offering a perforate, the semiconductor chip that is suitable for is the semiconductor chip of central welding pad formula (CentralPad Type), the weld pad of this semiconductor chip is all exposed in the perforate of substrate, pass this perforate for first conducting element of for example plain conductor and weld with it; When substrate offers the perforate of two parallel opposed, then be applicable to the semiconductor chip of the bilateral weld pad formula of tool (Double-Sided Pad Type), the weld pad on the semiconductor chip relative side is exposed to respectively in the corresponding perforate of substrate; And when substrate offers the perforate that four rectangular row put, then be suitable for the semiconductor chip of peripheral weld pad formula (Peripheral PadType), so that the weld pad on each limit exposes in the perforate of substrate correspondence on the semiconductor chip.
The present invention also provides a kind of preparation method of thin semiconductor device, it is characterized in that comprising the following steps: to be ready to a substrate, and this substrate is made of a basic unit and several conductive traces, and offers at least one perforate; Bonding semiconductor chip is to the predeterminated position of the basic unit of this substrate; The perforate that passes this substrate with several first conducting elements is electrically connected the conductive trace of this semiconductor chip and substrate; In the basic unit of this substrate, form one first colloid to coat this semiconductor chip; Second conducting element that several become array way to arrange is set on the terminal of the conductive trace of this substrate; On the conductive trace of this substrate, form one second colloid to coat this conductive trace, first conducting element and perforate fully, and make this second conducting element and the binding of this second colloid be one, and allow the bottom of this second conducting element expose outside the bottom surface of second colloid, and make the bottom of this second conducting element and the bottom surface of this second colloid be positioned at same plane.
Below in conjunction with accompanying drawing shown in the specific embodiment, characteristics of the present invention and effect are described in further detail.
Description of drawings
Fig. 1 is the cutaway view of the thin semiconductor device of first embodiment of the invention;
Fig. 2 is the upward view of the thin semiconductor device of first embodiment of the invention;
Fig. 3 A-Fig. 3 H is the manufacturing process schematic diagram of the thin semiconductor device of demonstration first embodiment of the invention;
Fig. 4 A-Fig. 4 B is another manufacturing process schematic diagram of the thin semiconductor device of demonstration first embodiment of the invention;
Fig. 5 is the cutaway view of the thin semiconductor device of second embodiment of the invention;
Fig. 6 is the cutaway view of the thin semiconductor device of third embodiment of the invention;
Fig. 7 is the cutaway view of the thin semiconductor device of fourth embodiment of the invention;
Fig. 8 is the cutaway view of the thin semiconductor device of fifth embodiment of the invention;
Fig. 9 is the upward view of the thin semiconductor device of fifth embodiment of the invention;
Figure 10 is the cutaway view of the thin semiconductor device of sixth embodiment of the invention;
Figure 11 is the upward view of the thin semiconductor device of sixth embodiment of the invention; And
Figure 12 is the cutaway view of known semiconductor device.
Embodiment
First embodiment
Shown in Figure 1 is the cutaway view of the thin semiconductor device of first embodiment of the invention.As shown in the figure, the semiconductor device 2 of first embodiment, include semiconductor chip 20, substrate 21 for these semiconductor chip 20 bonding usefulness, in order to be electrically connected the plain conductor 22 of this semiconductor chip 20 and substrate 21, be formed at the last colloid 23 of these substrate 21 tops, planting is in these substrate 21 belows and several soldered balls 24 that become array way (Arrayed) to arrange, and is formed at the following colloid 25 on these substrate 21 belows.
This semiconductor chip 20 has an action face 200 and a relative non-action face 201, is provided with parallel several weld pads 202 arranged side by side of two rows on the position of these action face 200 central authorities.This semiconductor chip 20 is by be bonded to the predeterminated position on this substrate 21 as the adhesive of elargol or polyimides film known adhesion media such as (Polyimide Tape) in action face 200 mode down.For resulting from the contact stress of 21 of semiconductor chip 20 and substrates in the temperature cycles that reduces follow-up manufacturing process, employed adhesive or film should be made by thermoplasticity (Thermoplastic) or thermoelasticity (Thermoelastic) resin material.
This substrate 21 is made of several conductive traces 211 that a basic unit 210 and is laid on these basic unit 210 bottom surfaces.The material that is applicable to this basic unit 210 is that this semiconductor chip 20 promptly adheres in this basic unit 210 by adhesive or film as epoxy resin, polyimide resin, two maleamide triazine (Bismaleimidetriaxine) resins, FR4 resin, glass epoxy, ceramic material or high temperature resistant paper wood etc.This conductive trace 211 is formed by Copper Foil, and the terminal of each conductive trace 211 is provided with for soldered ball 24 plants the weld pad 211a that connects, and its top also is formed with the weld pad 211b for plain conductor 22 welding.The conductive trace 211 of this substrate 21 since be entirely down that colloid 25 covers and with the airtight isolation in the external world, refuse welding flux layer so need not on the bottom surface of substrate 21, lay one, and can reduce the manufacturing cost of substrate 21; Simultaneously, the end face of this substrate 21 and bottom surface are formed with colloid 23 respectively and reach colloid 25 down, it is located in colloid 23 reaches 25 in following colloid, because last colloid 23 is to be corresponding relation up and down with following colloid 25, the thermal stress effects that produces in the temperature cycles of follow-up encapsulation manufacturing process is significantly reduced, and effectively avoid encapsulating the manufactured goods generation warping phenomenon of finishing, and can and then effectively reduce substrate 21 and 20 probability that occur peeling off of semiconductor chip, so can improve the acceptance rate of manufactured goods.In addition, because substrate 21 is to be located in 25 in colloid 23 and following colloid, and this structure can effectively be avoided the generation of warpage and need not strengthen the mechanical strength of manufactured goods by the thickness of substrate 21, so, this substrate 21 can give slimming and than the thickness of existing product for thin, so except the manufacturing cost that can reduce substrate 21, also make the integral thickness of manufactured goods further to reduce.
This substrate 21 also offers a perforate 212 at central part, after being bonded in the basic unit 210 of this substrate 21 for this semiconductor chip 20, weld pad 202 on the action face 200 of this semiconductor chip 20 can expose in this perforate 212, be beneficial to plain conductor 22 and can pass this perforate 212 and be terminated at respectively between the weld pad 211b of the weld pad 202 of this semiconductor chip 20 and conductive trace 211, to be electrically connected this semiconductor chip 20 and conductive trace 211 by it.
Fig. 3 A-Fig. 3 H is the manufacturing process schematic diagram of the thin semiconductor device of first embodiment of the invention.
As shown in Figure 3A, the substrate 21 that is ready to have a basic unit 210 and several conductive traces 211 and offers a perforate 212.
Shown in Fig. 3 B, with semiconductor chip 20 with action face 200 down the mode of (Face Down) bond on the precalculated position of this substrate 21 by elargol or polyimides film, after bonding, the weld pad 202 on this semiconductor chip 20 will expose in the perforate 212 of this substrate 21.
Shown in Fig. 3 C, carry out the bonding wire operation so that the perforate 212 that plain conductor 22 is passed this substrate 21 is connected to respectively on the weld pad 211b of this weld pad 202 and conductive trace 211, thereby be electrically connected this semiconductor chip 20 and conductive trace 211.
Shown in Fig. 3 D, after the bonding wire operation is finished, promptly potting resin 25a is filled in to this perforate 212, till this plain conductor 22 is covered fully by this potting resin 25a in general some glue (Glob Top) mode.
Shown in Fig. 3 E, the structure of finishing step shown in Fig. 3 D is inserted encapsulating mould (Encapsulating Mold, not shown) in to carry out operations for forming (Transfer Molding), the potting resin that makes fusion curing molding on the end face of substrate 21 for this on colloid 23 this semiconductor chip 20 is coated.Certainly, this molding mode also can be adopted other known injection mo(u)lding (Injection Molding) or cast molding modes such as (Pour Molding).
Shown in Fig. 3 F, after last colloid 23 forms, promptly on the weld pad 211a of the conductive trace 211 of this substrate 21, plant and connect soldered ball 24, be known technology owing to plant the ball operation, so do not give unnecessary details in addition at this.
Shown in Fig. 3 G, plant after the ball operation finishes, just on the bottom surface of this substrate 21, form this time colloid 25 by aforesaid molding mode, this time colloid 25 is covered fully cover this conductive trace 211 and plain conductor 22, and also wherein both are bonded as one these soldered ball 24 coatings.The formation of this time colloid 25 also can adopt alternate manners such as printing technology, coating method or some glue to realize, there is no specific limited.
At last, shown in Fig. 3 H, with general grinder P from the bottom surface of this time colloid 25 towards the direction of substrate 21 worn colloid 25 and soldered ball 24 down, till the height of the thickness of this time colloid 25 and soldered ball 24 is reduced to a predetermined value, and make the bottom 240 of this soldered ball 24 be plane, and make 250 of itself and the bottom surfaces of following colloid 25 at grade, and the thickness of this time colloid 25 still is enough to lid and covers this plain conductor 22 and make plain conductor 22 unlikely exposing, so the integral thickness of the semiconductor device 2 (as shown in Figure 1) of finishing encapsulation manufacturing process is decreased.
In addition, the step that plain conductor 22 is covered with potting resin 25a in advance shown in Fig. 3 D can be given omission, and the direct step that promptly directly enters last colloid 23 compression moldings shown in Fig. 3 E after plain conductor 22 welding so, can be simplified the manufacturing process of semiconductor device of the present invention.
Fig. 4 A-Fig. 4 B is another encapsulation manufacturing process schematic diagram of the thin semiconductor device of demonstration first embodiment of the invention.The step of this encapsulation manufacturing process before planting the ball operation is all identical with aforesaid 3A to 3E figure those shown, do not illustrate in addition so will not give unnecessary details also in this article, and the step that goes up certainly after colloid 23 forms begins explanation.In addition, still continue to use same sign symbol with the identical person of element shown in the aforementioned encapsulation manufacturing process.
Shown in Fig. 4 A, after last colloid 23 is formed on the end face of substrate 21, promptly on the weld pad 211a of conductive trace 211, be coated with the projection 24 ' that forms with tin/lead alloy with screen printing technology, because this projection 24 ' is realized with contacting by printing (or plating) mode of weld pad 211a, so can control exactly height after projection 24 ' forms to only a little more than the bank summit 220 of plain conductor 22, and make bottom 240 ' after this projection 24 ' moulding for plane.Because of this projection 24 ' can form with printing or plating mode, need not expensive ball attachment machine planting soldered ball, so can significantly reduce manufacturing cost with projection 24 ' replacement soldered ball 24.
Shown in Fig. 4 B, projection 24 ' connect establish finish after, promptly can form the following colloid 25 that covers this conductive trace 211, plain conductor 22 and perforate 212 fully with molding mode, this time colloid 25 also is bonded as one with each projection 24 ' and makes the bottom 240 ' of this projection 24 ' expose outside down the bottom surface 250 of colloid 25, and makes the bottom 240 ' of this projection 24 ' in the same plane with the bottom surface 250 of following colloid 25 in the same manner.Simultaneously, because the height of this projection 24 ' is the bank summit 220 that is controlled at a little more than plain conductor 22, cover this plain conductor 22 and make plain conductor 22 unlikely exposing so the thickness of this time colloid 25 is enough to lid, institute be so that need not grind to reduce its thickness after colloid 25 moulding down, just can make the integral thickness that encapsulates the semiconductor device of finishing 2 thickness less than known BGA semiconductor device.
Shown in Figure 5 is the cutaway view of the thin semiconductor device of second embodiment of the invention.The structure of the semiconductor device 3 of this second embodiment is approximately identical to the first above-mentioned embodiment, and difference is on it colloid 33 after moulding on the end face of substrate 31, makes the non-action face 301 of semiconductor chip 30 expose outside the end face 330 of colloid 33 on this.The heat that the structure decapacitation that this kind exposes produces semiconductor chip 30 can directly be improved outside the radiating efficiency to atmosphere by its non-action face 301 loss, also do not coat the non-action face 301 of this semiconductor chip 30 because of last colloid 33, and the product that the integral thickness of semiconductor device 3 can be disclosed less than first embodiment.In addition, for further improving radiating efficiency, directly an external fin 36 (dotted line illustrates in as Fig. 5) on the non-action face 301 that this exposes.
Shown in Figure 6 is the cutaway view of the thin semiconductor device of third embodiment of the invention.The structure of the semiconductor device 4 of the 3rd embodiment is approximately identical to the first above-mentioned embodiment, difference is on the non-action face 401 of its semiconductor chip 40 can a bonding again fin 46, after making colloid 43 on this take shape on the end face of substrate 41, this fin 46 can be coated by last colloid 43 but make its end face 460 expose outside the end face 430 of colloid 43, the heat transferred that produces for this semiconductor chip 40 can be by these fin 46 direct loss to atmosphere to this fin 46.Certainly, this fin 46 also can be coated fully by 43 in last colloid.
Shown in Figure 7 is the cutaway view of the thin semiconductor device of fourth embodiment of the invention.The structure of the semiconductor device 5 of the 4th embodiment is approximately identical to above-mentioned first embodiment, and difference is the also sticking fin 56 that is provided with in the basic unit 510 of its substrate 51.This fin 56 has a slotted eye 560, is bonded in the basic unit 510 of substrate 51 for this semiconductor chip 50 stimulates the menstrual flow this slotted eye 560.This fin 56 will make the integral thickness that encapsulates the semiconductor device of finishing 5 identical with the described product of first embodiment with the mode of substrate 51 bondings, the unlikely increase that causes thickness.
The 8th figure is depicted as the cutaway view of the thin semiconductor device of fifth embodiment of the invention.The structure of the semiconductor device 6 of the 5th embodiment is approximately identical to the first above-mentioned embodiment, and difference is that its semiconductor chip 60 is bilateral weld pad formula.For cooperating the use of bilateral weld pad formula semiconductor chip 60, this substrate 61 must offer the perforate 612 of two parallel opposed, after making this semiconductor chip 60 be bonded in the basic unit 610 of this substrate 61, the weld pad 602 on each limit can expose outside in the corresponding perforate 612 of substrate 61, is electrically connected this semiconductor chip 40 and conductive trace 611 for plain conductor 62 passes corresponding perforate 612 respectively.Certainly, the non-action face of this semiconductor chip 60 can expose outside its end face after last colloid 63 moulding, because this structure can be spreaded to easily by product shown in Figure 5, will not repeat in addition to illustrate at this.This semiconductor device 6 is after finishing encapsulation, and the bottom 640 of each projection 64 promptly exposes outside down the bottom surface 650 of colloid 65 with array way, as shown in Figure 9.
Shown in Figure 10 is the cutaway view of the thin semiconductor device of sixth embodiment of the invention.The structure of the semiconductor device 7 of the 6th embodiment is approximately identical to the first above-mentioned embodiment, and difference is that its semiconductor chip 70 is peripheral weld pad formula person.For cooperating the use of peripheral weld pad formula semiconductor chip 70, this substrate 71 must offer the perforate 712 that the rectangular row in four roads are put, after making semiconductor chip 70 be bonded in the basic unit 710 of this substrate 71, the weld pad 702 on each limit can expose in the corresponding perforate 712 of substrate 71, is electrically connected this semiconductor chip 70 and conductive trace 711 for plain conductor 72 passes corresponding perforate 712 respectively.In like manner, the non-action face of this semiconductor chip 70 also can expose outside the end face of colloid 73 on this, can also be on the non-action face that exposes an external fin to improve radiating efficiency, because of this structure can be spreaded to easily by product shown in Figure 5, so also will not give unnecessary details.This semiconductor device 7 is when finishing encapsulation, and the bottom 740 of each projection 74 promptly exposes outside down the bottom surface 750 of colloid 75 in mode shown in Figure 11.
Claims (24)
1, a kind of thin semiconductor device is characterized in that comprising:
One substrate, it has at least one perforate, and is made of a basic unit and several conductive traces;
The semiconductor chip, it has an action face and a relative non-action face, and this semiconductor chip is to be bonded in the basic unit of this substrate with its action face;
Several first conducting elements are electrically connected the conductive trace of this semiconductor chip and substrate in order to stimulate the menstrual flow this perforate;
Several second conducting elements, it is arranged on the terminal of each conductive trace, is electrically connected by itself and the external world for this semiconductor chip;
One first colloid, it is formed in the basic unit of this substrate to coat this semiconductor chip; And
One second colloid, it is formed on the conductive trace of this substrate to cover this conductive trace, first conducting element and opening fully, and this second colloid and second conducting element are bonded as one, and the bottom that makes this second conducting element exposes outside the bottom surface of this second colloid, and makes the bottom of this second conducting element and the bottom surface of second colloid be positioned at same plane.
2, thin semiconductor device as claimed in claim 1 is characterized in that, this first conducting element is a plain conductor.
3, thin semiconductor device as claimed in claim 1 is characterized in that, this second conducting element is a soldered ball.
4, thin semiconductor device as claimed in claim 3 is characterized in that, the bottom of this soldered ball is plane, in order to the bottom surface copline of this time colloid.
5, thin semiconductor device as claimed in claim 1 is characterized in that, this second conducting element is a projection.
6, thin semiconductor device as claimed in claim 5 is characterized in that, this projection is to connect with mode of printing to establish to the terminal of this conductive trace.
7, thin semiconductor device as claimed in claim 5 is characterized in that, this projection is to connect with plating mode to establish to the terminal of this conductive trace.
8, thin semiconductor device as claimed in claim 5 is characterized in that, the material of making this projection is to select from the cohort that copper, aluminium, copper alloy, aluminium alloy and tin/lead alloy are formed.
9, thin semiconductor device as claimed in claim 5 is characterized in that, the bottom of this projection is plane, in order to the bottom surface copline of this time colloid.
10, thin semiconductor device as claimed in claim 1 is characterized in that, the non-action face of this semiconductor chip is the end face that exposes outside colloid on this.
11, thin semiconductor device as claimed in claim 1 is characterized in that, the non-action face of this semiconductor chip is covered by colloid on this.
12, thin semiconductor device as claimed in claim 1 is characterized in that, this substrate has the perforate of two parallel opposed.
13, thin semiconductor device as claimed in claim 1 is characterized in that, this substrate has the perforate that four roads become the rectangle row to put.
14, thin semiconductor device as claimed in claim 1 is characterized in that, comprises that also one connects the fin of establishing with the non-action face of this semiconductor chip.
15, thin semiconductor device as claimed in claim 1 is characterized in that, also comprise one with the fin of the base adhesive of this substrate, this fin has a slotted eye, is bonded in the basic unit of this substrate for this semiconductor chip passes this slotted eye.
16, thin semiconductor device as claimed in claim 1 is characterized in that being applicable to that the material of this basic unit is to select from the cohort that epoxy resin, polyimide resin, two maleamide cyanate resins, FR4 resin, glass epoxy, ceramic material and heat resistance paper wood are formed.
17, a kind of preparation method of thin semiconductor device is characterized in that comprising the following steps:
Be ready to a substrate, this substrate is made of a basic unit and several conductive traces, and offers at least one perforate;
Bonding semiconductor chip is to the predeterminated position of the basic unit of this substrate;
The perforate that passes this substrate with several first conducting elements is electrically connected the conductive trace of this semiconductor chip and substrate;
In the basic unit of this substrate, form one first colloid to coat this semiconductor chip;
Second conducting element that several become array way to arrange is set on the terminal of the conductive trace of this substrate;
On the conductive trace of this substrate, form one second colloid to coat this conductive trace, first conducting element and perforate fully, and make this second conducting element and the binding of this second colloid be one, and allow the bottom of this second conducting element expose outside the bottom surface of second colloid, and make the bottom of this second conducting element and the bottom surface of this second colloid be positioned at same plane.
18, the preparation method of thin semiconductor device as claimed in claim 17, it is characterized in that, after the step that forms this second colloid, give this second colloid and second conducting element attenuating processing highly, this semiconductor device made from thinning with lapping mode.
19, the preparation method of thin semiconductor device as claimed in claim 17 is characterized in that, this second conducting element is a soldered ball.
20, the preparation method of thin semiconductor device as claimed in claim 19 is characterized in that, this soldered ball is to plant with ball attachment machine to be connected on this substrate.
21, the preparation method of thin semiconductor device as claimed in claim 17 is characterized in that, this second conducting element is a projection.
22, the preparation method of thin semiconductor device as claimed in claim 21 is characterized in that, this projection is to connect with mode of printing to be located on this substrate.
23, the preparation method of thin semiconductor device as claimed in claim 21 is characterized in that, this projection is to be formed on this substrate with plating mode.
24, the preparation method of thin semiconductor device as claimed in claim 17, it is characterized in that, be electrically connected the step of conductive trace of this semiconductor chip and substrate at this first conducting element after, coat this first conducting element in advance and with this first conducting element and extraneous airtight isolation with potting resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001234102A CN1168139C (en) | 2000-08-15 | 2000-08-15 | Thin semiconductor device and its preparing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001234102A CN1168139C (en) | 2000-08-15 | 2000-08-15 | Thin semiconductor device and its preparing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1338777A CN1338777A (en) | 2002-03-06 |
| CN1168139C true CN1168139C (en) | 2004-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001234102A Expired - Fee Related CN1168139C (en) | 2000-08-15 | 2000-08-15 | Thin semiconductor device and its preparing process |
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| Country | Link |
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| CN (1) | CN1168139C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8358002B2 (en) * | 2009-12-23 | 2013-01-22 | Marvell World Trade Ltd. | Window ball grid array (BGA) semiconductor packages |
| CN102403242B (en) * | 2010-09-17 | 2013-06-26 | 中芯国际集成电路制造(上海)有限公司 | Method for protecting chip to be detected from damage during re-bonding |
| CN107808872B (en) * | 2017-11-01 | 2019-09-13 | 无锡中微高科电子有限公司 | A kind of ball grid array Plastic Package preparation method that cavity is downward |
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2000
- 2000-08-15 CN CNB001234102A patent/CN1168139C/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN1338777A (en) | 2002-03-06 |
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