CN106601636B - 一种贴装预包封金属导通三维封装结构的工艺方法 - Google Patents

一种贴装预包封金属导通三维封装结构的工艺方法 Download PDF

Info

Publication number
CN106601636B
CN106601636B CN201611191648.7A CN201611191648A CN106601636B CN 106601636 B CN106601636 B CN 106601636B CN 201611191648 A CN201611191648 A CN 201611191648A CN 106601636 B CN106601636 B CN 106601636B
Authority
CN
China
Prior art keywords
metal column
plastic packaging
substrate
conducting
column frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201611191648.7A
Other languages
English (en)
Other versions
CN106601636A (zh
Inventor
孔海申
林煜斌
沈锦新
梁新夫
周青云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201611191648.7A priority Critical patent/CN106601636B/zh
Publication of CN106601636A publication Critical patent/CN106601636A/zh
Priority to PCT/CN2017/116051 priority patent/WO2018113574A1/zh
Priority to US16/472,160 priority patent/US10763128B2/en
Application granted granted Critical
Publication of CN106601636B publication Critical patent/CN106601636B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839Assembly of a flat lead with an insulating support, e.g. for TAB
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/76Apparatus for connecting with build-up interconnects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16251Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及一种贴装预包封金属导通三维封装结构的工艺方法,它包括以下步骤:步骤一、取金属板;步骤二、金属板冲切或蚀刻;步骤三,将导通金属柱框架包封;步骤四,开窗开槽;步骤五、取一基板,上面贴装有芯片;步骤六,贴合导通金属柱框架;步骤七,包封研磨;步骤八,无源器件贴装;步骤九,塑封植球;步骤十,切割。本发明能够埋入元器件提升整个封装功能集成度,此工艺方法使用预包封的整片金属柱框架或者单颗预包封金属柱作为层间导通,可以提高产品的可靠性能。

Description

一种贴装预包封金属导通三维封装结构的工艺方法
技术领域
本发明涉及一种贴装预包封金属导通三维封装结构的工艺方法,属于半导体封装技术领域。
背景技术
针对半导体封装轻薄短小的要求,现在的金属引线框或者有机基板的封装都在朝两个方向努力:1、降低封装尺寸;2、功能集成。对于降低封装尺寸部分,可以改善的空间有限,所以封装行业内集中于提高功能集成度,就是将部分功能元器件或者其他电子器件以埋入的方式集成于基板内部,以扩大整个封装体的功能集成度,而由于埋入元器件之后的基板层间材料更加复杂多样,并且不同材料的热膨胀系数差异很大,导致整个基板的翘曲问题严重、分层加剧,甚至引起爆板的问题。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种贴装预包封金属导通三维封装结构的工艺方法,它能够埋入元器件提升整个封装功能集成度,此工艺方法使用预包封的整片金属柱框架或者单颗预包封金属柱作为层间导通,可以提高产品的可靠性能。
本发明解决上述问题所采用的技术方案为:一种贴装预包封金属导通三维封装结构的工艺方法,所述方法包括以下步骤:
步骤一、取金属板
步骤二、金属板冲切或蚀刻
将金属板通过冲切或蚀刻形成导通金属柱框架,以便后续进行层间的导通;
步骤三,将导通金属柱框架包封
将导通金属柱框架中间镂空部分进行塑封,将金属柱周围用塑封料进行保护;
步骤四,开窗开槽
将塑封好的导通金属柱框架所需要的部分进行开窗;
步骤五、取一基板,上面贴装有芯片
步骤六,贴合导通金属柱框架
将导通金属柱框架用锡膏印刷或者导电胶贴合在基板上,和基板部分电性连接,开窗部分正好容置基板上的芯片;
步骤七,包封研磨
将基板正面采用塑封料进行塑封,并研磨露出导通金属柱框架表面;
步骤八,无源器件贴装
在研磨后的导通金属柱框架贴装无源器件;
步骤九,塑封植球
将完成无源器件贴装的基板表面进行塑封,在基板下表面植球;
步骤十,切割
将塑封好的基板切割成单颗产品。
一种贴装预包封金属导通三维封装结构的工艺方法,所述方法包括以下步骤:
步骤一、取金属板
步骤二、金属板冲切或蚀刻
将金属板通过冲切或蚀刻形成导通金属柱框架,以便后续进行层间的导通;
步骤三,将导通金属柱框架包封
将导通金属柱框架进行塑封,将金属柱周围以及上表面用塑封料进行保护;
步骤四,开窗开槽
将塑封好的导通金属柱框架所需要的部分进行开窗;
步骤五、贴合导通金属柱框架
取一基板,上面贴装有芯片,将导通金属柱框架用锡膏印刷或者导电胶贴合在基板上,和基板部分电性连接,开窗部分正好容置基板上的芯片;
步骤六,包封研磨
将基板正面采用塑封料进行塑封,并研磨露出导通金属柱框架表面;
步骤七,无源器件贴装 ,包封植球
在研磨后的金属柱板表面贴装无源器件,将完成无源器件贴装的基板表面进行塑封,在基板下表面植球;
步骤八,切割
将塑封好的基板切割成单颗产品。
一种贴装预包封金属导通三维封装结构的工艺方法,所述方法包括以下步骤:
步骤一、取金属板
步骤二、金属板表面电镀形成金属柱线路层
在金属板表面通过电镀的方式形成线路层,并且在线路层上方电镀形成导通铜柱;
步骤三,将金属柱线路层塑封
将金属板表面的金属柱线路层用塑封料进行保护;
步骤四,开窗
在塑封好的金属柱线路层所需要的部分进行开窗;
步骤五,去除金属板
步骤六、贴合金属柱线路层,塑封
取一基板,上面贴装有芯片,将金属柱线路层用锡膏印刷或者导电胶贴合在基板上,与基板部分电性连接,开窗部分正好容置基板上的芯片,将露出的芯片部分进行塑封保护,并研磨暴露出金属柱线路层的上表面;
步骤七,无源器件贴装 ,包封植球
在金属柱线路层的上表面贴装无源器件,将完成无源器件贴装的基板表面进行塑封,在基板下表面植球;
步骤八,切割
将塑封好的基板切割成单颗产品。
所述基板上贴装有单颗芯片、被动元器件或散热器件或多颗组合。
所述塑封方式采用模具灌胶方式、压缩灌胶、喷涂方式或是用贴膜方式。
与现有技术相比,本发明的优点在于:
1、本发明的三维封装结构的工艺流程,在基板中间的夹层制作过程中埋入对象,可以根据系统或功能需要在需要的位置或是区域埋入主动或被动元器件,封装整合的系统功能多,从而同样功能的元器件模块在PCB板上占用的空间比较少,从而降低成本又提升了封装的集成度;
2、本发明的工艺流程,通过预包封金属柱框架进行层间的导通,可以增加金属柱与塑封料的结合性,在后续制程中包封的时候预包封的塑封料可起到缓冲的作用,可以避免由于金属和塑封料的收缩率不同而引起的分层、垂直性裂缝等缺陷;
3、本发明的三维系统封装结构,使用预包封的金属柱框架,该框架设计的自由度比较高,可根据不同封装要求设计层间导通的线路,适用性极广。
附图说明
图1~图10为本发明一种贴装预包封金属导通三维封装结构的工艺方法实施例1的各工序示意图。
图11~图18为本发明一种贴装预包封金属导通三维封装结构的工艺方法实施例2的各工序示意图。
图19~图26为本发明一种贴装预包封金属导通三维封装结构的工艺方法实施例3的各工序示意图。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
实施例1:
本发明一种贴装预包封金属导通三维封装结构的工艺方法,它包括如下工艺步骤:
步骤一、取金属板
参见图1,取一片厚度合适的金属板;
步骤二、金属板冲切或蚀刻
参见图2,将金属板通过冲切或蚀刻形成导通金属柱框架,以便后续进行层间的导通,冲切和蚀刻的形状可以多样化,可以形成金属柱或者其他不规则形状,也可形成简单的线路形状;
步骤三,将导通金属柱框架包封
参见图3,将导通金属柱框架中间镂空部分进行塑封,将金属柱周围用塑封料进行保护,金属柱上下表面不用塑封;
步骤四,开窗开槽
参见图4,将塑封好的导通金属柱框架所需要的部分进行开窗;
步骤五、取一基板,上面贴装有芯片
参见图5,取一基板,上面贴装有芯片、被动元器件或散热器件等单颗或多颗组合;
步骤六,贴合导通金属柱框架
参见图6,将导通金属柱框架用锡膏印刷或者导电胶贴合在基板上,和基板部分电性连接,开窗部分正好容置基板上的芯片;
步骤七,包封研磨
参见图7,将基板正面采用塑封料进行塑封,塑封方式可以采用模具灌胶方式、压缩灌胶、喷涂方式或是用贴膜方式,所述可以采用有填料物质或是无填料物质的环氧树脂,并研磨露出导通金属柱框架表面。此步骤可省略。
步骤八,无源器件贴装
参见图8,在研磨后的导通金属柱框架贴装无源器件,当然不局限于无源器件,可贴装所需功能芯片或者整个封装体;
步骤九,塑封植球
参见图9,将完成无源器件贴装的基板表面进行塑封,在基板下表面植球;
步骤十,切割
参见图10,将塑封好的基板切割成单颗产品。
实施例2:
本发明一种贴装预包封金属导通三维封装结构的工艺方法,它包括如下工艺步骤:
步骤一、取金属板
参见图11,取一片厚度合适的金属板;
步骤二、金属板冲切或蚀刻
参见图12,将金属板通过冲切或蚀刻形成导通金属柱框架,以便后续进行层间的导通,冲切和蚀刻的形状可以多样化,可以形成金属柱或者其他不规则形状,也可形成简单的线路形状;
步骤三,将导通金属柱框架包封
参见图13,将导通金属柱框架进行塑封,将金属柱周围以及上表面用塑封料进行保护,此塑封方式简单,用常规的塑封模具即可实现;
步骤四,开窗开槽
参见图14,将塑封好的导通金属柱框架所需要的部分进行开窗;
步骤五、贴合导通金属柱框架
参见图15,取一基板,上面贴装有芯片、被动元器件或散热器件等单颗或多颗组合,将导通金属柱框架用锡膏印刷或者导电胶贴合在基板上,和基板部分电性连接,开窗部分正好容置基板上的芯片;
步骤六,包封研磨
参见图16,将基板正面采用塑封料进行塑封,塑封方式可以采用模具灌胶方式、压缩灌胶、喷涂方式或是用贴膜方式,所述可以采用有填料物质或是无填料物质的环氧树脂,并研磨露出导通金属柱框架表面。此步骤可省略;
步骤七,无源器件贴装 ,包封植球
参见图17,在研磨后的金属柱板表面贴装无源器件,当然不局限于无源器件,可贴装所需功能芯片或者整个封装体,将完成无源器件贴装的基板表面进行塑封,在基板下表面植球。
步骤八,切割
参见图18,将塑封好的基板切割成单颗产品。
实施例3:
步骤一、取金属板
参见图19,取一片厚度合适的金属板;
步骤二、金属板表面电镀形成金属柱线路层
参见图20,在金属板表面通过电镀的方式形成线路层,并且在线路层上方电镀形成导通铜柱;
步骤三,将金属柱线路层塑封
参见图21,将金属板表面的金属柱线路层用塑封料进行保护;
步骤四,开窗
参见图22,在塑封好的金属柱线路层所需要的部分进行开窗;
步骤五,去除金属板
参见图23,将金属板去除,余下的金属柱线路层依旧是整体框架形状;
步骤六、贴合金属柱线路层,塑封
参见图24,取一基板,上面贴装有芯片、被动元器件或散热器件等单颗或多颗组合,将金属柱线路层用锡膏印刷或者导电胶贴合在基板上,与基板部分电性连接,开窗部分正好容置基板上的芯片,将露出的芯片部分进行塑封保护,并研磨暴露出金属柱线路层的上表面;
步骤七,无源器件贴装 ,包封植球
参见图17,在金属柱线路层的上表面贴装无源器件,当然不局限于无源器件,可贴装所需功能芯片或者整个封装体,将完成无源器件贴装的基板表面进行塑封,在基板下表面植球;
步骤八,切割
参见图18,将塑封好的基板切割成单颗产品。
除上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。

Claims (5)

1.一种贴装预包封金属导通三维封装结构的工艺方法,其特征在于所述方法包括以下步骤:
步骤一、取金属板
步骤二、金属板冲切或蚀刻
将金属板通过冲切或蚀刻形成导通金属柱框架,以便后续进行层间的导通;
步骤三,将导通金属柱框架包封
将导通金属柱框架中间镂空部分进行塑封,将金属柱周围用塑封料进行保护;
步骤四,开窗开槽
将塑封好的导通金属柱框架所需要的部分进行开窗;
步骤五、取一基板,上面贴装有芯片
步骤六,贴合导通金属柱框架
将导通金属柱框架用锡膏印刷或者导电胶贴合在基板上,和基板部分电性连接,开窗部分正好容置基板上的芯片;
步骤七,包封研磨
将基板正面采用塑封料进行塑封,并研磨露出导通金属柱框架表面;
步骤八,无源器件贴装
在研磨后的导通金属柱框架贴装无源器件;
步骤九,塑封植球
将完成无源器件贴装的基板表面进行塑封,在基板下表面植球;
步骤十,切割
将塑封好的基板切割成单颗产品。
2.一种贴装预包封金属导通三维封装结构的工艺方法,其特征在于所述方法包括以下步骤:
步骤一、取金属板
步骤二、金属板冲切或蚀刻
将金属板通过冲切或蚀刻形成导通金属柱框架,以便后续进行层间的导通;
步骤三,将导通金属柱框架包封
将导通金属柱框架进行塑封,将金属柱周围以及上表面用塑封料进行保护;
步骤四,开窗开槽
将塑封好的导通金属柱框架所需要的部分进行开窗;
步骤五、贴合导通金属柱框架
取一基板,上面贴装有芯片,将导通金属柱框架用锡膏印刷或者导电胶贴合在基板上,和基板部分电性连接,开窗部分正好容置基板上的芯片;
步骤六,包封研磨
将基板正面采用塑封料进行塑封,并研磨露出导通金属柱框架表面;
步骤七,无源器件贴装,包封植球
在研磨后的导通金属柱框架表面贴装无源器件,将完成无源器件贴装的基板表面进行塑封,在基板下表面植球;
步骤八,切割
将塑封好的基板切割成单颗产品。
3.一种贴装预包封金属导通三维封装结构的工艺方法,其特征在于所述方法包括以下步骤:
步骤一、取金属板
步骤二、金属板表面电镀形成金属柱线路层
在金属板表面通过电镀的方式形成线路层,并且在线路层上方电镀形成导通铜柱;
步骤三,将金属柱线路层塑封
将金属板表面的金属柱线路层用塑封料进行保护;
步骤四,开窗
在塑封好的金属柱线路层所需要的部分进行开窗;
步骤五,去除金属板
步骤六、贴合金属柱线路层,塑封
取一基板,上面贴装有芯片,将金属柱线路层用锡膏印刷或者导电胶贴合在基板上,与基板部分电性连接,开窗部分正好容置基板上的芯片,将露出的芯片部分进行塑封保护,并研磨暴露出金属柱线路层的上表面;
步骤七,无源器件贴装,包封植球
在金属柱线路层的上表面贴装无源器件,将完成无源器件贴装的基板表面进行塑封,在基板下表面植球;
步骤八,切割
将塑封好的基板切割成单颗产品。
4.根据权利要求1或2或3所述的一种贴装预包封金属导通三维封装结构的工艺方法,其特征在于:所述基板上贴装有芯片、被动元器件或散热器件单颗或多颗组合 。
5.根据权利要求1或2或3所述的一种贴装预包封金属导通三维封装结构的工艺方法,其特征在于:所述塑封方式采用模具灌胶方式、压缩灌胶、喷涂方式或是用贴膜方式。
CN201611191648.7A 2016-12-21 2016-12-21 一种贴装预包封金属导通三维封装结构的工艺方法 Active CN106601636B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201611191648.7A CN106601636B (zh) 2016-12-21 2016-12-21 一种贴装预包封金属导通三维封装结构的工艺方法
PCT/CN2017/116051 WO2018113574A1 (zh) 2016-12-21 2017-12-14 一种贴装预包封金属导通三维封装结构的工艺方法
US16/472,160 US10763128B2 (en) 2016-12-21 2017-12-14 Process of surface-mounting three-dimensional package structure electrically connected by prepackaged metal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611191648.7A CN106601636B (zh) 2016-12-21 2016-12-21 一种贴装预包封金属导通三维封装结构的工艺方法

Publications (2)

Publication Number Publication Date
CN106601636A CN106601636A (zh) 2017-04-26
CN106601636B true CN106601636B (zh) 2018-11-09

Family

ID=58600292

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611191648.7A Active CN106601636B (zh) 2016-12-21 2016-12-21 一种贴装预包封金属导通三维封装结构的工艺方法

Country Status (3)

Country Link
US (1) US10763128B2 (zh)
CN (1) CN106601636B (zh)
WO (1) WO2018113574A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106601636B (zh) * 2016-12-21 2018-11-09 江苏长电科技股份有限公司 一种贴装预包封金属导通三维封装结构的工艺方法
CN107123602B (zh) * 2017-06-12 2019-06-21 江阴长电先进封装有限公司 一种指纹识别芯片的封装结构及其制造方法
US11139268B2 (en) * 2019-08-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1542932A (zh) * 2003-05-02 2004-11-03 精工爱普生株式会社 半导体装置的制造方法和电子设备的制造方法
CN101335218A (zh) * 2008-07-30 2008-12-31 江苏长电科技股份有限公司 金属平板式新型半导体封装方法
CN103681580A (zh) * 2013-12-05 2014-03-26 江苏长电科技股份有限公司 一次先蚀后镀金属框减法埋芯片倒装凸点结构及工艺方法
CN104051443A (zh) * 2014-06-30 2014-09-17 江苏长电科技股份有限公司 新型高密度可堆叠封装结构及制作方法
CN104659004A (zh) * 2014-12-30 2015-05-27 华天科技(西安)有限公司 一种PoP封装结构及其制造方法
CN106129016A (zh) * 2016-08-10 2016-11-16 江阴芯智联电子科技有限公司 双向集成埋入式芯片重布线pop封装结构及其制作方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734534B1 (en) * 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
JP2003023134A (ja) 2001-07-09 2003-01-24 Hitachi Ltd 半導体装置およびその製造方法
CN101807533B (zh) * 2005-06-30 2016-03-09 费查尔德半导体有限公司 半导体管芯封装及其制作方法
JP4730400B2 (ja) * 2007-10-09 2011-07-20 住友化学株式会社 光触媒体分散液
JP5082950B2 (ja) * 2008-03-13 2012-11-28 住友化学株式会社 揮発性芳香族化合物の分解方法
US20100110656A1 (en) * 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
CN102376628A (zh) * 2010-08-17 2012-03-14 环旭电子股份有限公司 系统封装模块的制造方法及其封装结构
JP5412002B1 (ja) * 2013-09-12 2014-02-12 太陽誘電株式会社 部品内蔵基板
TWI548011B (zh) * 2014-05-13 2016-09-01 矽品精密工業股份有限公司 封裝基板及其製法
CN105575832A (zh) * 2015-12-22 2016-05-11 华进半导体封装先导技术研发中心有限公司 一种多层堆叠扇出型封装结构及制备方法
CN106601636B (zh) 2016-12-21 2018-11-09 江苏长电科技股份有限公司 一种贴装预包封金属导通三维封装结构的工艺方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1542932A (zh) * 2003-05-02 2004-11-03 精工爱普生株式会社 半导体装置的制造方法和电子设备的制造方法
CN101335218A (zh) * 2008-07-30 2008-12-31 江苏长电科技股份有限公司 金属平板式新型半导体封装方法
CN103681580A (zh) * 2013-12-05 2014-03-26 江苏长电科技股份有限公司 一次先蚀后镀金属框减法埋芯片倒装凸点结构及工艺方法
CN104051443A (zh) * 2014-06-30 2014-09-17 江苏长电科技股份有限公司 新型高密度可堆叠封装结构及制作方法
CN104659004A (zh) * 2014-12-30 2015-05-27 华天科技(西安)有限公司 一种PoP封装结构及其制造方法
CN106129016A (zh) * 2016-08-10 2016-11-16 江阴芯智联电子科技有限公司 双向集成埋入式芯片重布线pop封装结构及其制作方法

Also Published As

Publication number Publication date
US20190333780A1 (en) 2019-10-31
WO2018113574A1 (zh) 2018-06-28
US10763128B2 (en) 2020-09-01
CN106601636A (zh) 2017-04-26

Similar Documents

Publication Publication Date Title
KR100809693B1 (ko) 하부 반도체 칩에 대한 신뢰도가 개선된 수직 적층형멀티칩 패키지 및 그 제조방법
CN215220710U (zh) 半导体设备
US10879197B2 (en) Package structure and method of fabricating package structure
CN102891123B (zh) 堆叠式管芯半导体封装体
CN106601636B (zh) 一种贴装预包封金属导通三维封装结构的工艺方法
EP2287898A2 (en) Shrink Package on Board
US8945989B2 (en) Stiffened semiconductor die package
CN112786541A (zh) 空腔器件组的封装结构及封装方法
US11004776B2 (en) Semiconductor device with frame having arms and related methods
US20180053713A1 (en) Semiconductor device and corresponding method
US10804172B2 (en) Semiconductor package device with thermal conducting material for heat dissipation
US7659608B2 (en) Stacked die semiconductor device having circuit tape
US7339797B2 (en) Chip mount, methods of making same and methods for mounting chips thereon
US8951841B2 (en) Clip frame semiconductor packages and methods of formation thereof
US7033517B1 (en) Method of fabricating a leadless plastic chip carrier
CN105321867A (zh) 一种互联载板的制作方法
US9230874B1 (en) Integrated circuit package with a heat conductor
CN103824820A (zh) 引线框区域阵列封装技术
US9093438B2 (en) Semiconductor device package with cap element
JP3398580B2 (ja) 半導体装置の製造方法及び基板フレーム
CN204375727U (zh) 一种高散热芯片嵌入式重布线封装结构
CN102832183B (zh) 一种采用弹性装置的无外引脚扁平半导体封装结构
CN203339147U (zh) 金属板多层线路基板芯片直放封装结构
CN106981430B (zh) 一种贴装金属导通三维系统级线路板的工艺方法
JP2009289926A (ja) 電子部品装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant