CN1542932A - 半导体装置的制造方法和电子设备的制造方法 - Google Patents
半导体装置的制造方法和电子设备的制造方法 Download PDFInfo
- Publication number
- CN1542932A CN1542932A CNA2004100386304A CN200410038630A CN1542932A CN 1542932 A CN1542932 A CN 1542932A CN A2004100386304 A CNA2004100386304 A CN A2004100386304A CN 200410038630 A CN200410038630 A CN 200410038630A CN 1542932 A CN1542932 A CN 1542932A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- resin
- semiconductor packages
- semiconductor chip
- packages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
- H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Acoustics & Sound (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
不恶化半导体封装的配置精度,容易调整半导体封装之间的树脂的配置位置。在隔着突出电极13电连接半导体封装PK1和半导体封装PK2之前,半导体芯片3的至少一部分露出,在半导体芯片3上配置树脂15,在半导体芯片3上配置的树脂15维持在A阶段状态或B阶段状态,并且隔着突出电极13电连接半导体封装PK1和半导体封装PK2。
Description
技术领域
本发明涉及半导体装置的制造方法和电子设备的制造方法,尤其适用于半导体封装的层叠结构的制造方法。
背景技术
以往的半导体封装中,例如像专利文献1所公开的那样,通过隔着焊锡球层叠半导体封装,实现空间节省。这里,在层叠的半导体封装之间填充树脂。
【专利文献1】
特开2002-170906号公报
但是以往的半导体封装中,隔着焊锡球层叠的半导体封装之间的整个空隙中填充树脂。因此,固化半导体封装之间填充的树脂时,树脂中包含的水分不能充分去除,半导体封装之间填充的树脂中仍残留水分。这样,存在层叠的半导体封装二次安装时的回流时,半导体封装之间填充的树脂中包含的水分气化而膨胀,半导体封装之间产生剥离的问题。
以往的半导体封装中,隔着焊锡球固定半导体封装后,半导体封装之间填充树脂。因此,存在半导体封装之间的间隙狭窄的情况下,难以限定在半导体封装之间的特定位置上填充树脂,树脂与焊锡球接触,对树脂产生热损坏,或不能考虑对半导体封装之间施加的应力来配置树脂。
另一方面,隔着焊锡球固定半导体封装之前用树脂固定半导体封装之间时,焊锡球的回流时半导体封装变得不能动弹。因此,存在由于焊锡球熔融时的表面张力引起的半导体封装的自对齐被阻碍,恶化半导体封装的配置精度。
因此,本发明的目的是提供一种不恶化半导体封装的配置精度,能够容易调整半导体封装之间的树脂的配置位置的半导体装置的制造方法和电子设备的制造方法。
发明内容
为解决上述问题,根据本发明的一个形式的半导体装置的制造方法,其特征在于包括: 向第一半导体封装上的至少一部分区域供给树脂的工序;上述树脂维持流动性的状态下,将第二半导体封装电连接在上述第一半导体封装上的工序。
由此,在第一半导体封装上配置树脂后,能够在第一半导体封装上配置第二半导体封装,并能够容易调整第一半导体封装和第二半导体封装之间的树脂的配置位置。这样,第一半导体封装和第二半导体封装之间的间隙狭窄的情况下,也能够避开焊锡材料在第一半导体封装和第二半导体封装之间配置树脂,或确保用于使树脂中包含的水分逃离的路径,并且在第一半导体封装和第二半导体封装之间设置树脂。其结果,抑制树脂的热损坏,并且抑制第一半导体封装和第二半导体封装之间的剥离,同时能够用树脂固定第一半导体封装和第二半导体封装,二次安装时进行回流处理的情况下也能够防止第一半导体封装和第二半导体封装之间的位置偏离。
另外,即使在第一半导体封装上配置第二半导体封装之前,将树脂配置在第一半导体封装上的情况下,在第一半导体封装上电连接第二半导体封装时,也能够维持第一半导体封装和第二半导体封装之间设置的树脂的流动性。因此,在第一半导体封装上电连接第二半导体封装时使用焊锡材料的情况下,也能够灵活运用焊锡熔融时的表面张力引起的自对齐,能够在第一半导体封装上精确配置第二半导体封装。
根据本发明的一个形式的半导体装置的制造方法,其特征在于包括:向装载在第一半导体封装上的第一半导体芯片的至少一部分区域供给树脂的工序;上述树脂维持流动性的状态下,将装载第二半导体芯片的第二半导体封装电连接在上述第一半导体封装上的工序。
由此,第一半导体封装和第二半导体封装之间的间隙狭窄的情况下,也能够避开焊锡材料,在第一半导体封装和第二半导体封装之间配置树脂,同时确保用于使树脂中包含的水分逃离的路径,并且在第一半导体封装和第二半导体封装之间设置树脂。其结果是抑制树脂的热损坏,并且抑制第一半导体封装和第二半导体封装之间的剥离,同时能够用树脂固定第一半导体封装和第二半导体封装,二次安装时进行回流处理的情况下,也能够防止第一半导体封装和第二半导体封装之间的位置偏离。
在第一半导体封装上电连接第二半导体封装时使用焊锡材料的情况下,也能够在第一半导体封装上移动第二半导体封装,灵活运用焊锡熔融时的表面张力引起的自对齐。
根据本发明的一个形式的半导体装置的制造方法,其特征在于包括:向装载第一半导体芯片的第一半导体封装上的至少一部分区域供给树脂的工序;维持上述树脂的流动性,并配置在上述第一半导体芯片上的形态,将装载了第二半导体芯片的第二半导体封装电连接在上述第一半导体封装上的工序。
由此,第一半导体封装和第二半导体封装种类不同的情况下,也能够防止层叠的半导体封装的二次安装时的位置偏离,并且,能够抑制第一半导体封装和第二半导体封装之间的剥离,同时在第一半导体封装上高精度地配置第二半导体封装,能够节省空间,并且能够提高第一半导体封装和第二半导体封装之间的连接可靠性。
根据本发明的一个形式的半导体装置的制造方法,其特征在于包括:向装载第一半导体芯片的第一半导体封装上的至少一部分区域供给树脂的工序;维持上述树脂的流动性并使端部配置在上述第一半导体芯片上的形态,将装载了第二半导体芯片的第二半导体封装电连接在上述第一半导体封装上的工序。
由此能够在同一的第一半导体芯片上配置多个半导体封装,并且在第一半导体封装上高精度地配置第二半导体封装,同时防止层叠的半导体封装的二次安装时的位置偏离,并且能够抑制第一半导体封装和第二半导体封装之间的剥离,进一步缩小安装面积,而且提高第一半导体封装和第二半导体封装之间的连接可靠性。
根据本发明的一个形式的半导体装置的制造方法,其特征在于:上述第一半导体封装和上述第二半导体封装隔着焊锡球电连接。
由此,通过进行回流处理,能够电连接第一半导体封装和第二半导体封装,在第一半导体封装上有效地安装第二半导体封装。
根据本发明的一个形式的半导体装置的制造方法,其特征在于:上述树脂维持流动性的状态是A阶段状态或B阶段状态。
由此,能够在常温下维持树脂的流动性、或通过加热向树脂附加流动性,不损坏焊锡熔融时的表面张力引起的自对齐,能够在第一半导体封装上电连接第二半导体封装。
根据本发明的一个形式的半导体装置的制造方法,其特征在于还包括:上述第二半导体封装电连接于上述第一半导体封装上后,将上述树脂移动到C阶段状态的工序。
由此,第二半导体封装电连接于第一半导体封装上后使树脂固化,不损坏焊锡熔融时的表面张力引起的自对齐,能够用树脂将第二半导体封装固定在第一半导体封装上。
根据本发明的一个形式的电子设备的制造方法,其特征在于包括:向装载第一电子零件的第一封装上的至少一部分区域上供给树脂的工序;在上述树脂维持流动性的状态下,将装载了第二电子零件的第二封装电连接于上述第一封装上的工序。
由此在第一封装上配置树脂后,能够将第二封装配置在第一封装上,容易调整第一封装和第二封装之间的树脂的配置位置。因此,第一封装和第二封装之间的间隙狭窄的情况下,也能够以避开焊锡材料,在第一封装和第二封装之间配置树脂,或确保用于使树脂中包含的水分逃离的路径,并且能够在第一封装和第二封装之间设置树脂。其结果,能够抑制树脂的热损坏,并且能够抑制第一封装和第二封装之间的剥离,同时能够用树脂固定第一封装和第二封装,即使二次安装时进行回流处理的情况下也能够防止第一封装和第二封装之间的位置偏离。
另外,在第一封装上配置第二封装之前,即使将树脂配置在第一封装上的情况下,在第一封装上电连接第二封装时,也能够维持第一封装和第二封装之间设置的树脂的流动性。因此,在第一封装上电连接第二封装时使用焊锡材料的情况下,也能够灵活运用焊锡熔融时的表面张力引起的自对齐,能够在第一封装上精确配置第二封装。
附图说明
图1是表示第一实施方式的半导体装置的示意结构的截面图;
图2是表示图1的半导体装置的制造方法的一例的截面图;
图3是表示第二实施方式的半导体装置的示意结构的截面图;
图4是表示第三实施方式的半导体装置的示意结构的截面图;
图5是表示第四实施方式的半导体装置的示意结构的截面图;
图6是表示第五实施方式的半导体装置的示意结构的截面图。
图中,
PK1、PK2、PK11、PK12、PK21、PK22、PK31、PK32、PK41、PK42—半导体封装,1、11、21、31、41、61、71、81、91、101、201—载体基板,2a、2b、9、12、22a、22c、32a、32c、42a、42c、62a、62b、72、82、92a、92c、102a、102c、202a、202c—岸面,3、23、33a、33b、43、51、63、93、103a、103b、103c、203a、203b、203c—半导体芯片,4、13、24、26、36、44、46、58、64、66、73、83、94、96、106、206—突出电极,5、25、45、65、95—各向异性导电片,7—焊剂,14、37、74、84、107、207—密封树脂,15、38、59、67、97—树脂,22b、32b、42b、92b、102b、202b—内部配线,34a、34b、104a、104b、104c、204a、204b、204c—粘接层,35a、35b、105a、105b、105c、205a、205b、205c—导电性线,52—电极垫,53—绝缘膜,54—应力缓和层,55—再配置配线,56—焊剂抗蚀层,57—开口部。
具体实施方式
下面参考附图说明本发明的实施方式的半导体装置及其制造方法。图1是表示本发明的第一实施方式的半导体装置的示意结构的截面图。图1中,半导体封装PK1上设置载体基板1,载体基板1的两面上分别形成有岸面2a,2b。并且,载体基板1上倒装片安装半导体芯片3,半导体芯片3上设有用于倒装片安装的突出电极4。并且,半导体芯片3上设置的突出电极4隔着各向异性导电片5,ACF(各向异性导电膜)接合于岸面2b上。
另一方面,半导体封装PK2上设置载体基板11,载体基板11的背面上形成岸面12,岸面12上设有突出电极13。载体基板11上安装半导体芯片,已安装半导体芯片的载体基板11用密封树脂14被密封。而且载体基板11上可以安装成线焊接连接的半导体芯片,也可以倒装片安装半导体芯片,也可以安装成半导体芯片的层叠结构。
并且,通过载体基板1上设置的岸面2b上接合突出电极13,使载体基板11配置在半导体芯片3上的形态,在半导体封装PK1上安装有半导体封装PK2。
半导体芯片3上配置树脂15,以使露出半导体芯片3的至少一部分,半导体封装PK2隔着树脂15固定在半导体芯片3上。这里,作为树脂15,可以使用树脂膏或树脂片之任一种。
由此,隔着半导体芯片3上设置的树脂15能够固定半导体封装PK1和半导体封装PK2,在半导体封装PK1,PK2之间设置树脂15的情况下,也能够在半导体封装PK1,PK2之间残留间隙。这样,能够容易去除半导体封装PK1,PK2之间的树脂15中包含的水分,二次安装时进行突出电极6的回流处理时,也能够抑制半导体封装PK1,PK2之间的树脂15膨胀。其结果,能够抑制半导体封装PK1,PK2之间的剥离,并且能够用树脂15固定半导体封装PK1和半导体封装PK2,能够防止半导体封装PK1,PK2之间的位置偏离。
使半导体芯片3的至少一部分露出的形态,在半导体芯片3上设置树脂15的情况下,隔着突出电极13电连接半导体封装PK1和半导体封装PK2之前,可以将树脂15配置在半导体芯片3上。并且隔着突出电极13电连接半导体封装PK1和半导体封装PK2的情况下,优选将半导体芯片3上配置的树脂15维持在A阶段状态(通过升温树脂软化的状态)或B阶段状态(通过升温树脂粘度增高的状态)。
由此,即使在半导体封装PK1上配置半导体封装PK2之前在半导体芯片3上配置树脂15的情况下,隔着突出电极13在半导体封装PK1上电连接半导体封装PK2时,能够维持半导体封装PK1,PK2之间设置的树脂15的流动性。这样,将焊锡球用作突出电极13时,也能够灵活运用焊锡熔融时的表面张力引起的自对齐,能够在半导体封装PK1上精确配置半导体封装PK2。
树脂15也可以设置在半导体芯片15的中央部。由此,隔着突出电极13电连接半导体封装PK1和半导体封装PK2的情况下,也能够在从突出电极13离开的位置上配置树脂15。这样,能够抑制树脂15的伸缩影响波及突出电极13,能够提高温度循环等的耐久性。
半导体芯片3和半导体封装PK2之间设置的树脂15,与半导体芯片3和载体基板1之间设置的各向异性导电片5相比,弹性系数低为好。由此,施加在半导体芯片3上的冲击能够被树脂15有效吸收。这样,能够提高半导体芯片3的耐冲击性,确保半导体芯片3的可靠性,并且能够层叠半导体封装PK1,PK2。
另外,树脂15中也可以混入氧化硅、氧化铝等的填充物。由此,能够容易控制树脂15的粘度,防止树脂15的液态下垂,并能够容易控制树脂15的存在范围。
半导体芯片3上的树脂15可以仅配置在1个位置上,但也可以分散配置在半导体芯片3上。这里,通过将树脂15分散配置到半导体芯片3上,能够在半导体芯片3上确保用于树脂15中包含的水分逃离的路径,在半导体芯片3和半导体封装PK2之间的间隙狭窄的情况下也能够减少树脂15中包含的水分。
作为载体基板1,11,例如可以使用两面基板、多层配线基板、叠放基板、带基板或膜基板等,作为载体基板1,11的材质,能够使用例如聚酰胺树脂、玻璃环氧树脂、BT树脂、芳基酰胺和环氧树脂的复合物或陶瓷等。作为突出电极4,6,13,可以使用例如由Au块、焊锡材料等覆盖的Cu块,Ni块或焊锡球等。
另外,在隔着突出电极13彼此接合半导体封装PK1,PK2的情况下,可以使用焊接接合、合金接合等的金属接合,或使用ACF接合、NCF(非导电膜)接合、ACP(各向异性导电膏)接合、NCP(非导电膏)接合等的压接接合。另外,在上述实施方式中,说明了在隔着突出电极4在载体基板1上倒装片安装半导体芯片3的情况下使用ACF接合的方法,但也可以使用NCF接合、ACP接合、NCP接合等的压接接合,也可以使用焊锡接合、合金接合等的金属接合。
图2是表示图1的半导体装置的制造方法的一个例子的截面图。图2(a)中,半导体封装PK1上层叠半导体封装PK2的情况下,在半导体封装PK2的岸面12上作为突出电极13形成焊接球,同时向载体基板1的岸面2b上供给焊剂7。通过使用分散器等将树脂15供给半导体芯片3上。这里在半导体封装PK1上层叠半导体封装PK2之前,通过向半导体芯片3供给树脂15,在层叠时的半导体封装PK1,PK2之间的间隙狭窄的情况下也能够仅在半导体芯片3上的特定区域容易地设置树脂15。
接着如图2(b)所示,在半导体封装PK1上安装半导体封装PK2。并且,通过进行突出电极13的回流处理使突出电极13熔融,将突出电极13接合在岸面2b上。
这里,将突出电极13接合在岸面2b上时,最好将树脂15维持在A阶段状态或B阶段状态。由此,通过突出电极3熔融时的表面张力能够将突出电极13自我匹配地配置在岸面2b上,能够在半导体封装PK1上精确配置半导体封装PK2。并且,将突出电极13接合在岸面2b上时,在比突出电极13的回流时的温度低的温度下固化树脂15,将树脂15移动到C阶段状态(固化状态)。
这里,通过在半导体芯片3上设置树脂15,使得半导体芯片3的至少一部分露出,确保树脂15中包含的水分逃离用的间隙,并且隔着半导体芯片3彼此固定半导体封装PK1,PK2,同时减少树脂15中包含的水分的残留量。
接着如图2(c)所示,在载体基板1的背面上设置的岸面2a上形成用于将载体基板1安装在母基板8上的突出电极6。接着如图2(d)所示,将形成突出电极6的载体基板1安装在母基板8上。并且,通过进行突出电极6的回流处理将突出电极6接合在母基板8的岸面9上。
这里,通过在半导体芯片3上设置树脂15,使得半导体芯片3的至少一部分露出,在基本去除半导体封装PK1,PK2之间的树脂15中包含的水分的状态下,可以进行突出电极6的回流处理。这样突出电极6回流时能够抑制树脂15膨胀,能够防止半导体封装PK1,PK2彼此剥离。在突出电极6回流时进行突出电极13的再回流的情况下,也能够维持用树脂15彼此固定半导体封装PK1,PK2的原样状态,防止半导体封装PK1,PK2之间的位置偏离。
上述实施方式中,说明了为了将半导体封装PK2安装在半导体封装PK1上,在载体基板1的岸面2b上设置突出电极13的同时,在载体基板11的岸面12上供给焊剂7的方法,但载体基板1的岸面2b上供给焊剂7的同时可以在载体基板11的岸面12上设置突出电极13。而且,上述实施方式中说明了通过使用分散器等向半导体芯片3上供给膏状树脂15的方法,但也可以向半导体芯片3上供给片状树脂15。也可以向载体基板1的岸面2b上供给焊锡膏。
图3是表示本发明的第二实施方式的半导体装置的简要结构的截面图。
图3中,半导体封装PK11上设置载体基板21,在载体基板21的两面上分别形成岸面22a,22c,同时载体基板21内形成内部配线22b。并且,载体基板21上倒装片安装半导体芯片23,半导体芯片23上设置用于倒装片安装的突出电极24。并且,在半导体芯片23上设置的突出电极24隔着各向异性导电片25,ACF接合在岸面22c上。载体基板21的背面设置的岸面22a上设有用于将载体基板21安装在母基板上的突出电极26。
另一方面,半导体封装PK12上设置载体基板31,载体基板31的两面上分别形成岸面32a,32c,同时,载体基板31内形成有内部配线32b。并且,载体基板31上隔着粘接层34a正片安装半导体芯片33a,半导体芯片33a隔着导电性线35a线焊接连接于岸面32c。另外,半导体芯片33a上避开导电性线35a正片安装半导体芯片33b,半导体芯片33b隔着粘接层34b固定在安装半导体芯片33a上,同时隔着导电性线35b线焊接连接于岸面32c。
载体基板31的背面上设置的岸面32a上,以使载体基板31保持在半导体芯片23上的形态、设有用于将载体基板31安装在载体基板21上的突出电极36。这里,使突出电极36避开半导体芯片23的装载区域地配置,例如可以在载体基板31的背面周围配置突出电极36。并且载体基板21上设置的岸面22c上接合突出电极36,使得载体基板31安装在载体基板21上。
在半导体芯片33a,33b的安装面侧的载体基板31上设置密封树脂37,通过该密封树脂37密封了半导体芯片33a,33b。密封树脂37密封半导体芯片33a,33b的情况下,通过使用例如环氧树脂等的热固化树脂的模压成型等进行。
在半导体芯片23上配置树脂38以露出半导体芯片23的至少一部分,半导体封装PK12隔着树脂38固定在半导体芯片23上。这里半导体芯片23的至少一部分露出地在半导体芯片23上设置树脂38的情况下,隔着突出电极36电连接半导体封装PK11和半导体封装PK12之前,可以在半导体芯片23上配置树脂38。并且隔着突出电极38电连接半导体封装PK11和半导体封装PK12的情况下将半导体芯片23上配置的树脂38维持在A阶段状态或B阶段状态为好。
由此,半导体封装PK11和半导体封装PK12为不同种类或不同大小的情况下,也能够防止层叠的半导体封装PK11,PK12之间的二次安装时的位置偏离,并且抑制半导体封装PK11,PK12之间的剥离,同时灵活运用自对齐,高精度地在半导体封装PK11上配置半导体封装PK12,可以节省空间,并且提高半导体封装PK11,PK12之间的连接靠可靠性。
图4是表示本发明的第三实施方式的半导体装置的简要结构的截面图。
图4中,半导体封装PK21上设置载体基板41,载体基板41的两面上分别形成岸面42a,42c,同时载体基板41内形成内部配线42b。并且,载体基板41上倒装片安装半导体芯片43,半导体芯片43上设有用于倒装片安装的突出电极44。并且,半导体芯片43上设置的突出电极44隔着各向异性导电片45ACF接合在岸面42c上。载体基板41的背面设置的岸面42a上设有用于将载体基板41安装在母基板上的突出电极46。另一方面,半导体封装PK22上设置半导体芯片51,半导体芯片51上设置电极垫52的同时,使电极垫52露出的形态,设有绝缘膜53。并且在半导体芯片51上露出电极垫52的形态、形成应力缓和层54,电极垫52上形成在应力缓和层54上延伸的再配置配线55。
并且,再配置配线55上形成焊料抗蚀剂膜56,焊料抗蚀剂膜56上形成有在应力缓和层54中露出再配置配线55的开口部57。并且隔着开口部57露出的再配置配线55上设置用于将半导体芯片51面朝下安装在载体基板41上的突出电极58,以将半导体封装PK32保持在半导体芯片53上。这里,突出电极58避开半导体芯片43的装载区域配置,例如在半导体芯片51的周围配置突出电极58。并且,在载体基板41上设置的岸面42c上接合突出电极58,将半导体芯片PK22安装在载体基板41上。
另外,半导体芯片43上配置树脂59以露出半导体芯片43的至少一部分,半导体芯片PK22隔着树脂59固定在半导体芯片43上。这里使半导体芯片43的至少一部分露出地在半导体芯片43上设置树脂59的情况下,隔着突出电极58电连接半导体封装PK21和半导体封装PK22之前,可以在半导体芯片53上配置树脂59。并且隔着突出电极58电连接半导体封装PK21和半导体封装PK22的情况下,优选将半导体芯片43上配置的树脂59维持在A阶段状态或B阶段状态。
由此,在半导体封装PK21上层叠W-CSP(晶片级—芯片大小封装)时,防止层叠的半导体封装PK21,PK22在2次安装时位置偏离,并且能够抑制半导体封装PK21,PK22之间的剥离,同时灵活运用自对齐将半导体封装PK22高精度地配置在半导体封装PK21上成为可能。因此,半导体芯片43,51的种类或大小不同的情况下,也不用在半导体芯片43,51之间插入载体基板,能够在半导体芯片43上3维安装半导体芯片51,并实现半导体芯片43,51安装时节省空间,提高3维安装的半导体芯片43,51的可靠性成为可能。
图5是表示本发明的第四实施方式的半导体装置的简要结构的截面图。
图5中,半导体封装PK31上设置载体基板61,载体基板61的两面上分别形成岸面62a,62b。并且,载体基板61上倒装片安装半导体芯片63,半导体芯片63上设有用于倒装片安装的突出电极64。并且,半导体芯片63上设置的突出电极64隔着各向异性导电片65ACF接合在岸面62b上。另一方面,半导体封装PK32,PK33上分别设置载体基板71,81,载体基板71,81的背面上分别形成岸面72,82,岸面72,82上分别设有焊锡球等的突出电极73,83。载体基板71,81上分别安装半导体芯片,安装半导体芯片的载体基板71,81分别用密封树脂74,84被密封着。
并且,通过载体基板61上设置的岸面62b上分别接合突出电极73,83,以使载体基板71,81的端部分别配置在半导体芯片63上的形态,将多个半导体封装PK32,PK33安装在半导体封装PK31上。
另外,半导体芯片63上配置树脂67以露出半导体芯片63的至少一部分,半导体封装PK32,PK33的端部隔着树脂67固定在半导体芯片63上。这里半导体芯片63的至少一部分露出地在半导体芯片63上设置树脂67的情况下,分别隔着突出电极73,83电连接半导体封装PK31和半导体封装K32,PK33之前,可以在半导体芯片63上配置树脂67。并且分别隔着突出电极73,83电连接半导体封装PK31和半导体封装PK32,PK33的情况下,优选将在半导体芯片63上配置的树脂59维持在A阶段状态或B阶段状态。
由此,能够防止半导体封装PK31,PK32,PK33在二次安装时的位置偏离,并且能够抑制半导体封装PK32,PK33和半导体封装PK31之间的剥离,同时,在同一半导体芯片63上能够配置多个半导体封装PK32,PK33,并且灵活运用自对齐将半导体封装PK32,PK33高精度地配置在半导体封装PK31上成为可能。因此,能够节省空间,并且将半导体封装PK32,PK33高精度地配置在半导体封装Pk31上,同时能够提高半导体封装PK31,PK32,PK33的可靠性。
半导体芯片63和半导体封装PK32,PK33之间分别设置树脂67的情况下,可以在向半导体芯片63供给树脂67后,向半导体芯片63上分别配置半导体封装PK32,PK33。也可以在向半导体芯片63上分别配置半导体封装PK32,PK33后隔着半导体封装PK32,PK33之间的间隙向半导体芯片63上供给树脂67。
图6是表示本发明的第五实施方式的半导体装置的简要结构的截面图。
图6中,半导体封装PK41上设置载体基板91,载体基板91的两面上分别形成岸面92a,92b,同时载体基板91内形成内部配线92b。并且,载体基板91上倒装片安装半导体芯片93,半导体芯片93上设置用于倒装片安装的突出电极94。并且,半导体芯片93上设置的突出电极94隔着各向异性导电片95ACF接合在岸面92c。载体基板91的背面上设置的岸面92a上设有用于将载体基板91安装到母基板的突出电极96。
另一方面,半导体封装PK42,PK43上分别设有载体基板101,201。而且载体基板101,201的背面上分别形成岸面102a,202a的同时,载体基板101,201的表面分别形成岸面102c,202c,载体基板101,201内分别形成内部配线102b,202b。
并且,载体基板101,201上分别隔着粘接层104a,204a各自正片安装半导体芯片103a,203a,半导体芯片103a,203a分别隔着导电线105a,205a各自线焊接连接在岸面102c,202c。
另外,半导体芯片103a,203a上,以避开导电线105a,205a分别正片安装半导体芯片103b,203b,半导体芯片103b,203b分别隔着粘接层104b,204b各自固定于半导体芯片103a,203a上,同时分别隔着导电线105b,205b各自线焊接连接在岸面102c,202c。另外,半导体芯片103b,203b上,以避开导电线105b,205b的形态,分别正片安装半导体芯片103c,203c,半导体芯片103c,203c分别隔着粘接层104c,204c各自固定于半导体芯片103b,203b上,同时分别隔着导电线105c,205c分别线焊接连接在岸面102c,202c。
另外,载体基板101,201的背面上分别设置的岸面102a,202a上,以将载体基板101,201分别支持在半导体芯片93上的形态,分别设有用于将载体基板101,201分别安装在载体基板91上的突出电极106,206。这里突出电极106,206最好至少存在于载体基板101,201的4角上,例如可以按字状排列突出电极106,206。
并且通过在设置于载体基板91上设置的岸面92c上分别接合突出电极106,206,使载体基板101,201的端部分别配置在半导体芯片93上的形态,可以将载体基板101,201分别安装在载体基板91上。在半导体芯片103a~03c、203a~203c的安装面侧的载体基板101,201上分别设置密封树脂107,207,通过该密封树脂107,207分别密封半导体芯片103a~103c、203a~203c。
另外,半导体芯片93上配置树脂97以露出半导体芯片93的至少一部分,半导体封装PK42,PK43的端部隔着树脂97固定在半导体芯片93上。这里,以使半导体芯片93的至少一部分露出地在半导体芯片93上设置树脂97的情况下,分别隔着突出电极106,206电连接半导体封装PK41和半导体封装PK42,PK43之前,可以在半导体芯片93上配置树脂97。并且分别隔着突出电极106,206电连接半导体封装PK41和半导体封装PK42,43的情况下,优选将半导体芯片93上配置的树脂59维持在A阶段状态或B阶段状态。
由此,在同一半导体芯片93上能够配置多个半导体封装PK42,PK43,能够缩小安装面积,并且实现不同种类的半导体芯片93,103a~103c、203a~203c的三维安装,同时抑制半导体封装PK42,PK43和半导体封装PK41之间的剥离,并且防止半导体封装PK41,PK42,PK43在二维安装时的位置偏离。即使将半导体封装PK42,PK43配置在半导体封装PK41之前,在半导体芯片93上配置树脂97的情况下,在分别隔着突出电极106,206将半导体封装PK42,PK43电连接在半导体封装PK41上时,能够维持半导体封装PK41和半导体封装PK42,PK43之间设置的树脂97的流动性。因此,在将焊锡球分别用作突出电极106,206时,能够灵活运用焊锡熔融时的表面张力而引起(带来)的自对齐,能够在半导体封装PK41上高精度地分别配置半导体封装PK42,PK43。
上述的半导体装置可以适用于例如液晶显示装置、便携电话、便携信息终端、摄像机、数码相机、MD(Mini Disk)播放器等的电子仪器,能够实现电子仪器的小型化、轻量化,并且提高电子仪器的可靠性。
另外,在上述实施方式中,举例说明了层叠半导体封装的方法,但本发明不限定于层叠半导体封装的方法,例如可以用于层叠弹性表面波(SAW)元件等的陶瓷元件、光调制器和光开关等的光学元件、磁传感器和生物传感器等的各种传感器类等。
Claims (8)
1.一种半导体装置的制造方法,其特征在于包括:
向第一半导体封装上的至少一部分区域供给树脂的工序;和
在上述树脂维持流动性的状态下,将第二半导体封装电连接在上述第一半导体封装上的工序。
2.一种半导体装置的制造方法,其特征在于包括:
向装载在第一半导体封装上的第一半导体芯片的至少一部分区域供给树脂的工序;和
在上述树脂维持流动性的状态下,将装载第二半导体芯片的第二半导体封装电连接在上述第一半导体封装上的工序。
3.一种半导体装置,其特征在于包括:
向装载第一半导体芯片的第一半导体封装上的至少一部分区域供给树脂的工序;和
维持上述树脂的流动性,并配置在上述第一半导体芯片上的形态,将装载了第二半导体芯片的第二半导体封装电连接在上述第一半导体封装上的工序。
4.一种半导体装置,其特征在于包括:
向装载了第一半导体芯片的第一半导体封装上的至少一部分区域供给树脂的工序;和
维持上述树脂的流动性并使端部配置在上述第一半导体芯片上的形态,将装载了第二半导体芯片的第二半导体封装电连接在上述第一半导体封装上的工序。
5.根据权利要求1~4中的任一项所述的半导体装置的制造方法,其特征在于:上述第一半导体封装和上述第二半导体芯片隔着焊锡球电连接。
6.根据权利要求1~5中的任一项所述的半导体装置的制造方法,其特征在于:
上述树脂维持流动性的状态是A阶段状态或B阶段状态。
7.根据权利要求1~6中的任一项所述的半导体装置的制造方法,其特征在于还包括:
上述第二半导体封装电连接于上述第一半导体封装上后,将上述树脂移动到C阶段状态的工序。
8.一种电子设备的制造方法,其特征在于包括:
向装载第一电子零件的第一封装的至少一部分区域上供给树脂的工序;和
在上述树脂维持流动性的状态下,将装载第二电子零件的第二封装电连接于上述第一封装上的工序。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003127058A JP2004335604A (ja) | 2003-05-02 | 2003-05-02 | 半導体装置の製造方法および電子デバイスの製造方法 |
JP2003127058 | 2003-05-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1542932A true CN1542932A (zh) | 2004-11-03 |
CN1286158C CN1286158C (zh) | 2006-11-22 |
Family
ID=33503750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100386304A Expired - Fee Related CN1286158C (zh) | 2003-05-02 | 2004-04-27 | 半导体装置的制造方法和电子设备的制造方法 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2004335604A (zh) |
CN (1) | CN1286158C (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106601636A (zh) * | 2016-12-21 | 2017-04-26 | 江苏长电科技股份有限公司 | 一种贴装预包封金属导通三维封装结构的工艺方法 |
CN108630552A (zh) * | 2017-03-23 | 2018-10-09 | 东和株式会社 | 半导体封装体配置装置、制造装置、配置方法及其应用 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4324773B2 (ja) * | 2003-09-24 | 2009-09-02 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP6010880B2 (ja) * | 2011-04-15 | 2016-10-19 | 株式会社ニコン | 位置情報検出センサ、位置情報検出センサの製造方法、エンコーダ、モータ装置及びロボット装置 |
-
2003
- 2003-05-02 JP JP2003127058A patent/JP2004335604A/ja active Pending
-
2004
- 2004-04-27 CN CNB2004100386304A patent/CN1286158C/zh not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106601636A (zh) * | 2016-12-21 | 2017-04-26 | 江苏长电科技股份有限公司 | 一种贴装预包封金属导通三维封装结构的工艺方法 |
CN106601636B (zh) * | 2016-12-21 | 2018-11-09 | 江苏长电科技股份有限公司 | 一种贴装预包封金属导通三维封装结构的工艺方法 |
CN108630552A (zh) * | 2017-03-23 | 2018-10-09 | 东和株式会社 | 半导体封装体配置装置、制造装置、配置方法及其应用 |
CN108630552B (zh) * | 2017-03-23 | 2021-08-03 | 东和株式会社 | 半导体封装体配置装置、制造装置、配置方法及其应用 |
Also Published As
Publication number | Publication date |
---|---|
CN1286158C (zh) | 2006-11-22 |
JP2004335604A (ja) | 2004-11-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100349292C (zh) | 半导体装置及其制造方法、电子设备、电子仪器 | |
CN100342538C (zh) | 半导体装置、电子设备及它们的制造方法,以及电子仪器 | |
CN101221946B (zh) | 半导体封装、及系统级封装模块的制造方法 | |
CN1291467C (zh) | 电子器件的制造方法 | |
US6987058B2 (en) | Methods for underfilling and encapsulating semiconductor device assemblies with a single dielectric material | |
EP1134804B1 (en) | Thermally enhanced semiconductor carrier | |
EP1229577A2 (en) | Flip chip semiconductor device in a moulded chip scale package (csp) and method of assembly | |
JP2003115560A (ja) | 半導体装置、積層半導体装置、半導体装置の製造方法及び積層半導体装置の製造方法 | |
CN1695246A (zh) | 半导体封装及层叠型半导体封装 | |
TW200414471A (en) | Semiconductor device and manufacturing method for the same | |
EP1172851A2 (en) | Semiconductor device having heat spreader attached thereto and method of manufacturing the same | |
CN1453868A (zh) | 多芯片封装体及其制造方法 | |
JP2009152253A (ja) | 半導体装置およびその製造方法 | |
CN1542963A (zh) | 半导体装置及其制造方法、电子设备、电子仪器 | |
TW201207961A (en) | Semiconductor package device using underfill material and packaging method thereof | |
CN1601713A (zh) | 半导体装置的制造方法 | |
CN1531088A (zh) | 半导体装置、电子设备及它们的制造方法,以及电子仪器 | |
CN1532930A (zh) | 半导体装置、电子设备及它们的制造方法,以及电子仪器 | |
CN1531089A (zh) | 半导体装置、电子设备及它们制造方法,以及电子仪器 | |
CN1286158C (zh) | 半导体装置的制造方法和电子设备的制造方法 | |
CN1228839C (zh) | 一种多晶粒封装结构 | |
US20080179726A1 (en) | Multi-chip semiconductor package and method for fabricating the same | |
KR20040069827A (ko) | 반도체 장치 및 반도체 장치의 패키지 방법 | |
KR100370116B1 (ko) | 반도체 패키지 및 그 제조방법 | |
CN1606160A (zh) | 半导体装置及其制造方法、电路基板以及电子设备 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20061122 Termination date: 20140427 |