CN101221946B - 半导体封装、及系统级封装模块的制造方法 - Google Patents

半导体封装、及系统级封装模块的制造方法 Download PDF

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CN101221946B
CN101221946B CN2007101273631A CN200710127363A CN101221946B CN 101221946 B CN101221946 B CN 101221946B CN 2007101273631 A CN2007101273631 A CN 2007101273631A CN 200710127363 A CN200710127363 A CN 200710127363A CN 101221946 B CN101221946 B CN 101221946B
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surface
semiconductor chip
substrate
bolt
winding
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CN2007101273631A
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CN101221946A (zh
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曹佩华
江浩然
林亮臣
牛保刚
刘忆台
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台湾积体电路制造股份有限公司
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Priority to US11/652,086 priority Critical patent/US7719122B2/en
Priority to US11/652,086 priority
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Abstract

一种半导体封装、及系统级封装模块的制造方法。在一个实施例中,系统级封装包括具有第一表面和相对第一表面的第二表面的基底,且一组接合线栓位于基底第二表面的接合垫上。第一半导体芯片具有第一表面和相对第一表面的第二表面,其中第一半导体芯片的第一表面通过焊锡凸块贴合基底的第二表面。填充材料设置于第一半导体芯片和基底间,其中填充材料将焊锡凸块封定。第二半导体芯片具有第一表面和相对第一表面的第二表面,其中第二半导体芯片的第一表面贴合第一半导体芯片的第二表面。一组接合线电性耦接第二半导体芯片和基底上的接合线栓。本发明可避免因填充物或粘着物溢流至邻近的接合垫时造成的合格率的损失,从而可设计出较小尺寸的封装。

Description

半导体封装、及系统级封装模块的制造方法

技术领域

[0001] 本发明涉及一种集成电路封装,特别是涉及一种系统级封装 (System-In-Package, SIP),以减少接合线污染及其造成的合格率损失。

背景技术

[0002] 随着便携式电子元件变得越来越小,必须缩小电子元件的半导体封装的尺寸。为 了达到上述目的,广泛的使用系统级封装技术,其理由是因为系统级封装技术可增加半导 体封装的容量。系统级封装包括多个芯片,其可堆叠或是彼此通过焊锡凸块(solder bump) 和/或接合线连接。

[0003] 图1揭示一种公知包括接合线的倒装基础系统级封装。封装体10包括分别具有 第一表面30和第二表面40的基底20。多个焊锡球110位于第一表面30。多个焊锡凸块 60电性连接基底20的第二表面40和大尺寸芯片50的有源表面,其中大尺寸芯片可为数字 元件。一个例如模拟元件的小尺寸芯片80堆叠于大尺寸芯片50的背部表面,接合线90电 性连接小尺寸芯片80和基底上的接合垫95。

[0004] 为提供大尺寸芯片50和基底20间的机械强化,通常会在大尺寸芯片50和基底 20的间隙填入例如光致抗蚀剂的填充材料70,若未将此间隙填充,当封装体10在高温条件 下,可能会造成其疲劳破裂或电性失效。然而,公知的填充工艺具有以下缺点:在线接合工 艺之前,填充的光致抗蚀剂很可能会不规则地流向邻近的接合垫,造成接合垫的污染,且接 合线90和接合垫95难以正确的接合,而造成合格率损失。因此,封装的设计者通常会将接 合垫距离大尺寸芯片50边缘间的最小距离大于0. 3mm,以避免填充材料溢到接合垫95上。 然而,设计者又必须使封装尺寸减小,再加上上述设计限制条件,使得设计者在设计上没有 足够的弹性。

[0005] 图1显示一个系统级封装的剖面图,其中填充材料70没有溢流到接合垫95上,图 2A和图2B显示系统级封装的溢流问题120的范例,其中如图2A所示,在一个倒装基础系统 级封装中,填充材料70溢流至接合垫95上,如图2B所示,在一个线接合系统级封装中,粘 性材料75溢流至接合垫95上。

发明内容

[0006] 根据上述问题,本发明的目的为提供一种改进的系统级封装,以最小化接合线的 污染和合格率的损失。另外,本发明的另一目的为提供一种方法,避免公知系统级封装的可 靠度的相关问题。

[0007] 本发明提供一种半导体封装,包括以下元件,基底,具有第一表面和相对第一表面 的第二表面,且一组接合线栓位于基底第二表面的接合垫上。第一半导体芯片,具有第一表 面和相对第一表面的第二表面,其中第一半导体芯片的第一表面通过焊锡凸块贴合基底的 第二表面。填充材料,设置于第一半导体芯片和基底间,其中填充材料将焊锡凸块封定。第 二半导体芯片,具有第一表面和相对第一表面的第二表面,其中第二半导体芯片的第一表

4面贴合第一半导体芯片的第二表面。一组接合线,电性耦接第二半导体芯片和基底上的该 组接合线栓。

[0008] 如上所述的半导体封装,其中该填充材料通过毛细动作填入该第一半导体芯片和 该基底的间隙,且该填充材料不溢流覆盖和/或重叠该组接合线栓的顶部表面。

[0009] 如上所述的半导体封装,其中该第一半导体芯片边缘和该组接合线栓中的一个接 合线栓的距离大体上介于0. Imm〜0. 2mm。

[0010] 如上所述的半导体封装,其中该组接合线栓中的一个接合线栓的高度大体上介于 10 μ m 〜30 μ m0

[0011] 本发明提供一种半导体封装,包括以下元件,基底,具有第一表面和相对第一表面 的第二表面。多个接合线栓位于基底第二表面的接合垫上,其中上述接合线栓包括第一组 接合线栓和第二组接合线栓。第一半导体芯片,具有第一表面和相对第一表面的第二表面, 其中第一半导体芯片的第一表面通过粘着物贴合基底的第二表面。第二半导体芯片,具有 第一表面和相对第一表面的第二表面,其中第二半导体芯片的第一表面贴合第一半导体芯 片的第二表面。第一组接合线,电性耦接第一半导体芯片和基底上的第一组接合线栓。第 二组接合线,电性耦接第二半导体芯片和基底上的第二组接合线栓。

[0012] 如上所述的半导体封装,其中该粘着物不溢流覆盖和重叠该多个接合线栓的顶部 表面。

[0013] 如上所述的半导体封装,其中该多个接合线栓中的一个接合线栓的高度大体上介 于 10 μ m 〜30 μ m0

[0014] 如上所述的半导体封装,还包括封装体,封装该第一和该第二半导体芯片、该第一 和第二组接合线和该第一和第二组接合线栓。

[0015] 本发明提供一种系统级封装模块的制造方法,包括以下步骤。首先,提供基底,具 有第一表面和相对第一表面的第二表面,形成一组接合线栓于基底的第二表面的接合垫 上。接着,提供第一半导体芯片,具有第一表面和相对第一表面的第二表面,其中第一半导 体芯片的第一表面通过焊锡凸块,贴合基底的第二表面,将填充材料填充于第一半导体芯 片和基底间,并将焊锡凸块封定。然后,提供第二半导体芯片,具有第一表面和相对第一表 面的第二表面,其中第二半导体芯片的第一表面贴合第一半导体芯片的第二表面。接下来, 线接合第二半导体芯片和基底上的接合线栓。

[0016] 如上所述的系统级封装模块的制造方法,其中该填充材料通过毛细动作填入该第 一半导体芯片和该基底的间隙,且该填充材料不溢流覆盖和重叠该组接合线栓的顶部表

[0017] 本发明提供一种系统级封装模块的制造方法,包括以下步骤。首先,提供基底,具 有第一表面和相对第一表面的第二表面,形成第一组接合线栓和第二组接合线栓于基底的 第二表面的接合垫上。其后,提供第一半导体芯片,具有第一表面和相对第一表面的第二表 面,其中第一半导体芯片的第一表面通过粘着物,贴合基底的第二表面。接下来,提供第二 半导体芯片,具有第一表面和相对第一表面的第二表面,其中第二半导体芯片的第一表面 贴合第一半导体芯片的第二表面。然后,利用第一组接合线,线接合第一半导体芯片和基底 上的第一组接合线栓。接着,利用第二组接合线,线接合第二半导体芯片和基底上的第二组 接合线栓。[0018] 如上所述的系统级封装模块的制造方法,其中该粘着物不溢流覆盖和重叠该多个 接合线栓的顶部表面。

[0019] 本发明可通过接合线栓的设置,避免当填充物或粘着物溢流至邻近的接合垫时, 产生污染或不适当的线接合,而造成合格率损失的问题。设计者可不考虑贴合基底的大芯 片边缘和接合垫的距离问题,从而设计较小尺寸的封装。

附图说明

[0020] 图1显示一个公知包括接合线的倒装基础系统级封装的剖面图。

[0021] 图2A-2B显示公知系统级封装的剖面图,揭示公知系统级封装工艺的缺点。

[0022] 图3显示本发明一个实施例系统级封装的剖面图。

[0023] 图4显示本发明一个实施例中,应用于系统级封装的接合线栓的详细图示。

[0024] 图5显示本发明另一个实施例系统级封装的剖面图。

[0025] 其中,附图标记说明如下:

[0026] 10〜封装体;20〜基底;

[0027] 30〜第一表面;40〜第二表面;

[0028] 50〜大尺寸芯片;55〜第一半导体芯片;

[0029] 60〜焊锡凸块;70〜填充材料;

[0030] 75〜粘性材料;80〜小尺寸芯片;

[0031] 85〜第二半导体芯片;90〜接合线;

[0032] 95〜接合垫;100〜封装体;

[0033] 110〜焊锡球;120〜溢流问题;

[0034] 130〜接合线栓。

具体实施方式

[0035] 以下详细讨论本发明较佳实施例的制造和使用,然而,根据本发明的概念,其可包 括或运用于更广泛的技术范围。须注意的是,实施例仅用以揭示本发明制造和使用的特定 方法,并不用以限定本发明。在一些范例中,并未详细描述熟知的结构和制造工艺,以避免 模糊本发明。

[0036] 图3显示本发明一个实施例系统级封装的剖面图,如图所示,封装体10包括分别 具有第一表面30和第二表面40的基底20,其中基底20可以是导线架(lead frame)、印刷 电路板(PCB),或是其它熟知的封装基底。多个焊锡球110可设置于基底20的第一表面30, 以耦接其它基底(未显示)。基底20的第二表面有一组接合线栓130 (bond wire stud), 其中接合线栓130可采用传统的线接合或凸块工艺,形成于基底20上,且接合线栓可包括 金、铜、铝、上述的合金,或是其它熟知的导电材料。接合线栓130在贴合芯片于基底20之 前,形成于基底的接合垫(有时称为接合线手指)上。根据此方法,即使例如环氧化物的 填充,或是粘性材料溢流至接合垫上,只要接合线栓的顶部表面是暴露的,且其上有足够的 接合线区域,接合线即可恰当的接合至接合线栓130。当然,接合线栓130的尺寸依照设计 需求,在本发明的一个实施例中,接合线栓130的高度介于ΙΟμπι〜30μπι之间。在本发明 的另一个实施例中,第一半导体芯片55的边缘至一组中的一个接合线栓130的距离约为

60. Imm〜0.2mm。图4显示本发明一个实施例中,应用于系统级封装的接合线栓的区域B的 详细图示。

[0037] 在于基底20的第二表面40上形成一组接合线栓130之后,将第一半导体芯片55 以倒装的方式,贴合于基底20上方,以减少封装剖面尺寸。第一半导体芯片55具有第一 表面和相对第一表面的第二表面,其中第一半导体芯片55的第一表面,经由多个焊锡凸块 60贴合基底20的第二表面40。焊锡凸块60可以是焊锡、金、铜、导电有机材料,或是其它 熟知的导电材料所组成。在另一个实施例中,可应用线接合(如图5所示)、自动胶带接合 (tape-automatic bonding,TAB),或其它熟知的封装技术电性连接第一半导体芯片55和基 底20。

[0038] 接着,将一填充材料70填充于第一半导体芯片55和基底20之间,以封装焊锡凸 块,使整个结构坚固,且增加封装的可靠度,并缓冲例如热循环的环境因素所产生的热应 力。固定剂量的填充材料70 (例如树脂)直接填充入第一半导体芯片55和基底20的间隙 中。之后,填充的树脂会通过毛细动作填满整个间隙,树脂可接触接合线栓130,但是其不覆 盖或是重叠接合线栓130的顶部表面。

[0039] 在第一半导体芯片55和基底20的间隙中形成填充材料之后,将第二半导体芯片 85经由例如环氧化物的粘性材料,贴合于第一半导体芯片55的背部表面。通过传统的线 接合工艺,接合线电性耦接第二半导体芯片85和基底20上的接合线栓130。之后,封装体 100 (例如热固性环氧化物、填充硅土、粘性聚合物,或其它熟知的材料或上述的组合)将第 一和第二半导体芯片、接合线90和接合线栓封装,以避免因水气或其它环境的污染造成损 坏。

[0040] 在本发明的另一个实施例中,如图5所示,第一半导体芯片55经由粘性材料 75 (例如环氧化物)贴合基底20,且其它的接合线经由其它的接合线栓电性连接第一半导 体芯片和基底。

[0041] 本发明上述实施例的系统级封装可提供芯片设计者以下好处:第一、本发明可通 过接合线栓,避免当填充物或粘着物溢流至邻近的接合垫时,产生污染或不适当的线接合, 而造成合格率损失的问题。第二、设计者在设计芯片时,因不需考虑贴合基底的大芯片边缘 和接合垫的距离至少大于0. 3mm,有较大的设计弹性。因此,设计者可不考虑上述问题,设计 较小尺寸的封装。

[0042] 虽然本发明已以较佳实施例揭示如上,然其并非用以限定本发明,任何本领域普 通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰。因此,本发明的 保护范围,当视随附的权利要求所界定的范围为准。

7

Claims (12)

  1.  一种半导体封装,包括:基底,具有第一表面和相对该第一表面的第二表面,一组接合线栓位于该基底的第二表面的接合垫上;第一半导体芯片,具有第一表面和相对该第一表面的第二表面,其中该第一半导体芯片的第一表面通过焊锡凸块贴合该基底的第二表面;填充材料,设置于该第一半导体芯片和该基底间,其中填充材料将该焊锡凸块封定;第二半导体芯片,具有第一表面和相对该第一表面的第二表面,其中该第二半导体芯片的第一表面贴合该第一半导体芯片的第二表面;及一组接合线,电性耦接该第二半导体芯片和该基底上的该组接合线栓。
  2. 2.如权利要求1所述的半导体封装,其中该填充材料通过毛细动作填入该第一半导 体芯片和该基底的间隙,且该填充材料不溢流覆盖和/或重叠该组接合线栓的顶部表面。
  3. 3.如权利要求1所述的半导体封装,其中该第一半导体芯片边缘和该组接合线栓中 的一个接合线栓的距离大体上介于0. Imm〜0. 2mm。
  4. 4.如权利要求1所述的半导体封装,其中该组接合线栓中的一个接合线栓的高度大 体上介于ΙΟμίΉ〜30μπΐ。
  5. 5. 一种半导体封装,包括:基底,具有第一表面和相对该第一表面的第二表面,多个接合线栓位于该基底的第二 表面的接合垫上,其中该多个接合线栓包括第一组接合线栓和第二组接合线栓;第一半导体芯片,具有第一表面和相对该第一表面的第二表面,其中该第一半导体芯 片的第一表面通过粘着物贴合该基底的第二表面;第二半导体芯片,具有第一表面和相对该第一表面的第二表面,其中该第二半导体芯 片的第一表面贴合该第一半导体芯片的第二表面;及第一组接合线,电性耦接该第一半导体芯片和该基底上的该第一组接合线栓;及 第二组接合线,电性耦接该第二半导体芯片和该基底上的第二组接合线栓。
  6. 6.如权利要求5所述的半导体封装,其中该粘着物不溢流覆盖和重叠该多个接合线 栓的顶部表面。
  7. 7.如权利要求5所述的半导体封装,其中该多个接合线栓中的一个接合线栓的高度 大体上介于10 μ m〜30 μ m。
  8. 8.如权利要求5所述的半导体封装,还包括封装体,封装该第一和该第二半导体芯 片、该第一和第二组接合线和该第一和第二组接合线栓。
  9. 9. 一种系统级封装模块的制造方法,包括:提供基底,具有第一表面和相对该第一表面的第二表面; 形成一组接合线栓于该基底的第二表面的接合垫上;提供第一半导体芯片,具有第一表面和相对该第一表面的第二表面,其中该第一半导 体芯片的第一表面通过焊锡凸块贴合该基底的第二表面;将填充材料填充于该第一半导体芯片和该基底间,并将该焊锡凸块封定; 提供第二半导体芯片,具有第一表面和相对该第一表面的第二表面,其中该第二半导 体芯片的第一表面贴合该第一半导体芯片的第二表面;及 线接合该第二半导体芯片和该基底上的接合线栓。
  10. 10.如权利要求9所述的系统级封装模块的制造方法,其中该填充材料通过毛细动作 填入该第一半导体芯片和该基底的间隙,且该填充材料不溢流覆盖和重叠该组接合线栓的 顶部表面。
  11. 11. 一种系统级封装模块的制造方法,包括:提供基底,具有第一表面和相对该第一表面的第二表面; 形成第一组接合线栓和第二组接合线栓于该基底的第二表面的接合垫上; 提供第一半导体芯片,具有第一表面和相对该第一表面的第二表面,其中该第一半导 体芯片的第一表面通过粘着物贴合该基底的第二表面;提供第二半导体芯片,具有第一表面和相对该第一表面的第二表面,其中该第二半导 体芯片的第一表面贴合该第一半导体芯片的第二表面;利用第一组接合线,线接合该第一半导体芯片和该基底上的该第一组接合线栓;及 利用第二组接合线,线接合该第二半导体芯片和该基底上的该第二组接合线栓。
  12. 12.如权利要求11所述的系统级封装模块的制造方法,其中该粘着物不溢流覆盖和 重叠该多个接合线栓的顶部表面。
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