JP5636497B2 - 電磁シールド及び放熱部を有する電子デバイス集合体の製造方法,並びに電磁シールド及び放熱部を有する電子デバイス - Google Patents
電磁シールド及び放熱部を有する電子デバイス集合体の製造方法,並びに電磁シールド及び放熱部を有する電子デバイス Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
- H05K9/002—Casings with localised screening
- H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
- H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
- H05K9/002—Casings with localised screening
- H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
- H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
- H05K9/003—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields made from non-conductive materials comprising an electro-conductive coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
Claims (8)
- 電子デバイス(111,112)の集合体(110)を製造する方法であって,
・平坦なパネル(100)を準備するステップを含み,該パネル(100)は,
- 基板(120)と,
- 前記基板に設けられた少なくとも1個の電子部品(171〜173)と,
- 少なくとも1個の電子部品(171〜173)を覆う封入部(140)と,
を備えるものとし,更に前記方法は,
・前記パネル(100)を電子デバイス(111,112)の集合体(110)に区分けするステップと,
・区分けした後,電子デバイス(111,112)の集合体(110)における各電子デバイス(111,112)に電磁保護層(130)を形成して,区分けにより露出した前記基板(120)の側面(121,122)を被覆すると共に,該電磁保護層(130)を電子デバイス(111,112)における前記封入部(140)に包囲されている領域(168)に対して熱的及び/又は電気的に接続するステップと,
・前記封入部に凹部(161)を設けるステップと,
・前記電磁保護層(130)を形成する前に該凹部(161)を熱伝導材料及び/又は導電材料で少なくとも部分的に充填することにより,前記封入部で包囲されている前記領域(168)を,充填した前記凹部(161)を介して,電磁保護層(130)の形成後に該電磁保護層(130)に接続するステップと,
を含む方法。 - 請求項1に記載の方法であって,前記凹部(161)を設けるステップは,前記封入部(140)へのソーイング又は穿孔を含む方法。
- 請求項1又は2に記載の方法であって,前記電磁保護層(130)の形成前に接続素子(162〜166)を配置することにより,該接続素子(162〜166)を,前記封入部で包囲されている前記領域(168)に接続するステップを含む方法。
- 請求項3に記載の方法であって,前記接続素子(162〜166)を,電磁保護層(130)の形成後に,該電磁保護層(130)と熱的及び/又は電気的に接続する方法。
- 請求項1〜4の何れか一項に記載の方法であって,前記電磁保護層(130)を電子デバイス(111,112)に形成することにより,該電子デバイス(111,112)における基板に対向する表面(143)を完全に被覆すると共に,該表面(143)に直交し,かつ区分けにより露出した前記封入部(140)及び基板(120)の側面(121,141,122,142)を完全に被覆する方法。
- 請求項1〜5の何れか一項に記載の方法であって,部品(172)と部品(173)との間の前記凹部が、前記封入部の表面(143)から前記導電材料(163)まで達している,方法。
- 請求項1〜6の何れか一項に記載の方法であって,前記凹部は、表面(143)から前記封入部(140)を完全に貫通して前記基板(120)内まで達している,方法。
- 請求項1〜7の何れか一項に記載の方法であって,前記基板において、前記凹部(161)に配置されている前記導電材料(162)が接点(152)に電気接続されている,方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE201010033551 DE102010033551A1 (de) | 2010-08-05 | 2010-08-05 | Verfahren zur Herstellung einer Mehrzahl von elektronischen Bauelementen mit elektromagnetischer Schirmung und elektronisches Bauelement mit elektromagnetischer Schirmung |
DE102010033551.7 | 2010-08-05 | ||
DE102010048632.9 | 2010-10-15 | ||
DE102010048632A DE102010048632A1 (de) | 2010-10-15 | 2010-10-15 | Verfahren zur Herstellung einer Mehrzahl von elektronischen Bauelementen mit elektromagnetischer Schirmung und insbesondere mit Wärmeabführung und elektronisches Bauelement mit elektromagnetischer Schirmung und insbesondere mit Wärmeabführung |
PCT/EP2011/062919 WO2012016898A2 (de) | 2010-08-05 | 2011-07-27 | Verfahren zur herstellung einer mehrzahl von elektronischen bauelementen mit elektromagnetischer schirmung und insbesondere mit wärmeabführung und elektronisches bauelement mit elektromagnetischer schirmung und insbesondere mit wärmeabführung |
Publications (2)
Publication Number | Publication Date |
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JP2013534366A JP2013534366A (ja) | 2013-09-02 |
JP5636497B2 true JP5636497B2 (ja) | 2014-12-03 |
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ID=45559866
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Application Number | Title | Priority Date | Filing Date |
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JP2013522203A Expired - Fee Related JP5636497B2 (ja) | 2010-08-05 | 2011-07-27 | 電磁シールド及び放熱部を有する電子デバイス集合体の製造方法,並びに電磁シールド及び放熱部を有する電子デバイス |
Country Status (3)
Country | Link |
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US (1) | US9386734B2 (ja) |
JP (1) | JP5636497B2 (ja) |
WO (1) | WO2012016898A2 (ja) |
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TWI471086B (zh) * | 2011-03-14 | 2015-01-21 | E Ink Holdings Inc | 一種於電子紙顯示器上形成電磁波屏蔽層之方法 |
CN104065774B (zh) * | 2014-07-08 | 2017-06-16 | 马鞍山绿盾防护材料科技有限公司 | 一种具有信号增强功能的防辐射手机壳及其制备方法 |
TWI656543B (zh) | 2015-10-16 | 2019-04-11 | 日商村田製作所股份有限公司 | Electronic parts |
CN106535606B (zh) * | 2016-12-30 | 2024-05-10 | 深圳天珑无线科技有限公司 | 射频屏蔽装置 |
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EP4040483A3 (en) * | 2021-02-04 | 2022-10-26 | Murata Manufacturing Co., Ltd. | Electronic component with internal shielding |
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-
2011
- 2011-07-27 WO PCT/EP2011/062919 patent/WO2012016898A2/de active Application Filing
- 2011-07-27 JP JP2013522203A patent/JP5636497B2/ja not_active Expired - Fee Related
- 2011-07-27 US US13/814,225 patent/US9386734B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US20130170172A1 (en) | 2013-07-04 |
JP2013534366A (ja) | 2013-09-02 |
WO2012016898A3 (de) | 2012-06-07 |
WO2012016898A2 (de) | 2012-02-09 |
US9386734B2 (en) | 2016-07-05 |
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