TWI491009B - 晶片級電磁干擾屏蔽結構及製造方法 - Google Patents
晶片級電磁干擾屏蔽結構及製造方法 Download PDFInfo
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Description
本發明是有關於一種電磁干擾屏蔽結構,且特別是有關於一種晶片級(chip level)電磁干擾屏蔽結構及製造方法,並且可直接在晶圓背面形成保形屏蔽(conformal shielding)以達到抑制電磁干擾(Electromagnetic Interference,EMI)的效果。
積體電路產業主要包括積體電路設計、積體電路製造與晶片結構。晶片結構會直接影響積體電路本身的電性能、機械性能、熱性能與光性能,對於積體電路的穩定性相當重要,因此晶片結構與電子產品是密不可分的,已經成為電子工業中的核心技術。
目前的晶片主要是以印刷電路板(printed circuit board,PCB)作為基板,晶片可設置於基板上,然後再經由基板將晶片的電性接腳連接至外部。基板上會設置接地層或是金屬層來抑制電磁干擾,通常金屬層是形成在基板的表面或是內層。但是隨著電子產品愈來愈輕薄的設計趨勢,傳統的晶片防電磁干擾的設計已經無法滿足目前的需求。
本發明提供一種晶片級電磁干擾屏蔽結構及製造方法,直接在晶圓背面與側壁上形成接地層與連接結構以形成保形屏蔽(conformal shielding),這樣的設計方式不僅可以達到抑制電磁干擾的效果,同時可以縮小晶片的尺寸。
本發明提出一種晶片級電磁干擾屏蔽結構,適用於設置至
少一晶片,該晶片級電磁干擾屏蔽結構包括一半導體基材、至少一接地導線、一接地層與一連接結構。半導體基材的一第一面具有一重配置層,接地層設置於半導體基材的一第二面上。接地導線設置於半導體基材的第一面上且接地導線位於半導體基材的邊緣,連接結構設置於半導體基材的一側壁上,用以連接接地導線與接地層。
在本發明一實施例中,上述半導體基材為一矽基材。上述連接結構係以無電鍍製程形成於半導體基材的側壁上。上述重配置層包括複數個金屬導線,用以電性連接至該些晶片。
在本發明一實施例中,上述晶片設置於上述半導體基材之第一面上,晶片級電磁干擾屏蔽結構更包括一保護層,覆蓋於上述晶片之上。保護層中具有複數個金屬導線,用以電性連接至重配置層。
本發明另提出一種晶片級電磁干擾屏蔽結構的製造方法,包括下列步驟:首先,形成一重配置層於一晶圓的一第一面上;然後形成至少一接地導線於晶圓的第一面上;接下來,設置至少一晶片於晶圓的第一面上且上述接地導線位於晶片之間。然後,形成一接地層於晶圓的一第二面;接下來,將晶圓切割為複數個半導體基材,且該些接地導線分別位於該些半導體基材的邊緣。然後,形成一連接結構於該些半導體基材中之一第一半導體基材的一側壁上,該連接結構用以連接對應於該第一半導體基材的該些接地導線與該接地層。
綜合上述,本發明直接於半導體背面與側面鍍上金屬層以直接形成屏蔽,並且直接於構裝體上直接設計出電路,藉此可省略一個印刷電路板以降低成本與體積。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉較
佳實施例,並配合所附圖式,作詳細說明如下。
圖1為根據本發明第一實施例之晶片級電磁干擾屏蔽結構示意圖。晶片級電磁干擾屏蔽結構主要包括半導體基材110、接地層111、連接結構112、接地導線121與保護層140。半導體基材110的上表面(第一面)上具有重配置層(Redistribution Layer,RDL)以連接晶片131~134,重配置層中具有複數個金屬導線,用以連接晶片131~134或進行電信號的傳送。接地導線121設置於半導體基材110的第一面上且位於半導體基材110的邊緣。半導體基材110的下表面(第二面)具有整面的金屬層,此金屬層為接地層111。連接結構112形成於半導體基材110的側壁上,接地層111會經由連接結構112連接至接地導線121以形成保形屏蔽(conformal shielding)。其中值得注意的是,上述接地層111、連接結構112與接地導線121可利用濺鍍(sputtering)的方式形成,但本發明並不受限於此。
晶片131~134上的接地線也可以透過重配置層連接至接地導線121。接地層111與接地導線121會形成金屬屏蔽效應以達到抑制電磁干擾(Electromagnetic Interference,EMI)的效果。連接結構112可利用例如無電鍍製程與鐳射技術形成於半導體基材110的側壁上,主要用來連接半導體基材110上下表面的接地導線121與接地層111。此外,晶片131~134的接地接腳可以透過重配置層連接至接地導線121。
晶片131~134是以覆晶技術配置於半導體基材110的上表面,保護層140覆蓋於積體電路晶片131~134的上以保護晶片131~134。保護層140為模塑複合材料(Molding Compound)。保護層140中利用鑽孔或鍍孔等形成金屬導線151,將晶片131~134的輸出/輸入(I/O)接腳連接至保護層140上方的金屬導線152。半導體基材110例如為矽基材或是由矽晶圓切割而成的基材。本發明是直接在半導體基材110的背面形成整面的金屬層來形成屏蔽(shielding),所以不需以額外的印刷電路板來形成屏蔽。因此利用本發明之晶片級電磁干擾屏蔽結構可以縮小晶片尺寸,同時簡化程序與降低製造成本。
另外,晶片131~134的接腳可經由金屬導線151連接至保護層140的上方的金屬導線152,外部的電路可以經由金屬導線151與152與積體電路晶片131~134進行電性連接。也就是說,本實施例直接於保護層140上設計出電路以進行電性連接,這樣的結構具有取代積體電路基板的優點,同時可以降低製造成本與體積。值得注意的是,位於半導體基材110的側壁的連接結構112主要是用來連接半導體基材110背面的接地層111與正面的接地導線121。在本發明中,連接結構112的形成方式與形狀可依照設計需求決定,本發明並不受限。在經由上述實施例之說明後,本技術領域具有通常知識者應可推知其他實施方式,在此不加累述。
為實現上述晶片級電磁干擾屏蔽結構,本發明提出一種晶片級電磁干擾屏蔽結構的製造方法,請同時參照圖2,圖2為根據本發明第二實施例之晶片製程之示意圖。首先在半導體基材110(或是晶圓)上形成重配置層與接地導線121,接地導線
121設置在半導體基材110的邊緣。若接地導線121是形成於晶圓上,接地導線121會設置在不同晶片設置區域之間,在切割晶圓後,接地導線121同樣會位於切割後的半導體基材110的邊緣。晶片131~134則是以覆晶方式設置於半導體基材110上(參照結構210)。接下來,在半導體基材110上形成保護層140,保護層140為模塑複合材料以保護晶片131~134(參照結構220)。其中,值得注意的是,在晶圓切割前,可進行晶片研磨以降低產品厚度。研磨的時機可選擇在重配置層形成前或形成後,本實施例並不受限,其研磨後的晶片厚度亦可依照產品需求決定,本實施例並不受限。
接下來,利用鑽孔與填孔或是鍍孔等方式,在保護層140中形成金屬導線151,然後利用金屬導線151將晶片131~134連接至保護層140上方的金屬導線152(參照結構230)。然後,在半導體基材110的側壁上形成連接結構112以連接半導體基材110兩面的接地導線121與接地層111以形成金屬屏蔽。值得注意的是,上述結構可直接應用於晶圓上,在形成保護層140後將晶圓切割為複數個半導體基材110,接地導線121需要事先規畫位置以便於在切割後可以位於半導體基材110的邊緣。本實施例中,接地導線121會設置於晶片之間,這樣在切割晶圓後,接地導線121便會自然位於半導體基材110。請參照圖3,圖3為根據本發明第二實施例晶圓示意圖,其中圖3(b)為圖3(a)中區域305的放大圖。晶片設置區域310與320為晶圓301上用來設置晶片的區域(請參照圖3(a)),接地導線121設置於晶片設置區域310與320之間(請參照圖3(b)),在沿著晶片設置區域進行切割後,接地導線121便會位於晶片設置區域310的邊緣,也就是半導體基材的邊緣。然後在半導體
基材的側壁上形成連接結構以連接接地導線121與另一面的接地層。
接下來,以流程圖說明本發明之晶片級電磁干擾屏蔽結構的製造方法,請同時參照圖3與4,圖4為根據本發明第三實施例之製造方法流程圖。首先,形成一重配置層於一晶圓的一第一面上(步驟S410),然後形成至少一接地導線121於晶圓的第一面上(步驟S420)。接下來,設置至少一晶片131~134於晶圓的第一面上且該些接地導線121位於該些晶片131~134之間(步驟S430)。然後形成一接地層111於晶圓的一第二面(步驟S440)。接下來,形成一保護層140於晶圓上以覆蓋該些晶片131~134(步驟S450),在保護層140與金屬導線151、152形成後,將晶圓切割為複數個半導體基材110,接地導線121會分別位於半導體基材110的邊緣(步驟S460)。然後,形成連接結構112於各該半導體基材110的一側壁上,用以連接各該半導體基材的接地導線121與接地層111以形成屏蔽。本實施例之晶片級電磁干擾屏蔽結構的製造方法的其餘實施細節請參照上述圖1~圖3的說明,在此不加累述。
值得注意的是,本實施例可依照設計需求選擇性在晶圓上的特定區域設置接地層與接地導線,這樣可以在特定的半導體基材上形成所需的屏蔽以達到抑制電磁干擾的效果。本發明並不限制形成接地層與接地導線的區域、形狀與數量。
綜上所述,本發明直接在晶圓背面與側壁上形成金屬層與連接結構以達到屏蔽的效果,利用本發明之晶片級電磁干擾屏蔽結構至少具有以下優點:
1.簡化電磁干擾屏蔽結構並降低晶片尺寸。
2.降低製造成本。
3.提高晶片的穩定度。
雖然本發明之較佳實施例已揭露如上,然本發明並不受限於上述實施例,任何所屬技術領域中具有通常知識者,在不脫離本發明所揭露之範圍內,當可作些許之更動與調整,因此本發明之保護範圍應當以後附之申請專利範圍所界定者為準。
110‧‧‧半導體基材
111‧‧‧接地層
112‧‧‧連接結構
121‧‧‧接地導線
131~134‧‧‧晶片
140‧‧‧保護層
151、152‧‧‧金屬導線
210~240‧‧‧結構
301‧‧‧晶圓
305‧‧‧區域
310、320‧‧‧晶片設置區域
S410~S470‧‧‧流程圖步驟
圖1為根據本發明第一實施例之晶片級電磁干擾屏蔽結構示意圖。
圖2為根據本發明第二實施例之晶片製程之示意圖。
圖3為根據本發明第二實施例晶圓結構示意圖。
圖4為根據本發明第三實施例之晶片級電磁干擾屏蔽結構的製造方法流程圖。
110‧‧‧半導體基材
111‧‧‧接地層
112‧‧‧連接結構
121‧‧‧接地導線
131~134‧‧‧晶片
140‧‧‧保護層
151、152‧‧‧金屬導線
Claims (8)
- 一種晶片級電磁干擾屏蔽結構,適用於設置至少一晶片,該晶片級電磁干擾屏蔽結構包括:一半導體基材,其中該晶片設置於該半導體基材之一第一面上;至少一接地導線,設置於該半導體基材的該第一面上且該接地導線位於該半導體基材的邊緣;一保護層,該保護層覆蓋於該晶片之上;一接地層,設置於該半導體基材的一第二面上;一連接結構,設置於該半導體基材的一側壁上,用以連接該些接地導線與該接地層;以及複數個金屬導線,部分該金屬導線配置於該保護層中,另部分該金屬導線位於該保護層上,其中該晶片經由配置於該保護層中的該金屬導線電性連接至配置於該保護層上方的金屬導線。
- 如申請專利範圍第1項所述之晶片級電磁干擾屏蔽結構,其中該半導體基材為一矽基材,該半導體基材的該第一面具有一重配置層以連接至該些晶片。
- 如申請專利範圍第1項所述之晶片級電磁干擾屏蔽結構,其中該連接結構係以無電鍍製程形成於該半導體基材的該側壁上。
- 如申請專利範圍第2項所述之晶片級電磁干擾屏蔽結構,其中該重配置層包括複數個金屬導線,用以電性連接至該些晶片。
- 如申請專利範圍第1項所述之晶片級電磁干擾屏蔽結構,其中配置於該保護層中的該金屬導線用以電性連接至該重 配置層。
- 一種晶片級電磁干擾屏蔽結構的製造方法,包括:形成一重配置層於一晶圓的該第一面上;形成至少一接地導線於該晶圓的一第一面上;設置至少一晶片於該晶圓的該第一面上且該些接地導線位於該些晶片之間;形成一接地層於該晶圓的一第二面;形成一保護層於該晶圓上以覆蓋該些晶片;形成複數個金屬導線於該保護層中以及該保護層上方,其中在該保護層中的該些金屬導線連接至該重配置層;將該晶圓切割為複數個半導體基材,且該些接地導線分別位於該些半導體基材的邊緣;以及形成一連接結構於該些半導體基材中之一第一半導體基材的一側壁上,該連接結構用以連接對應於該第一半導體基材的該些接地導線與該接地層。
- 如申請專利範圍第6項所述之製造方法,其中該晶圓為一矽晶圓。
- 如申請專利範圍第6項所述之製造方法,其中該連接結構係以無電鍍製程形成於該第一半導體基材的該側壁上。
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US13/053,528 US9287218B2 (en) | 2010-10-08 | 2011-03-22 | Chip level EMI shielding structure and manufacture method thereof |
JP2011098167A JP5527700B2 (ja) | 2010-10-08 | 2011-04-26 | チップレベル電磁(emi)シールド構造及び製造方法 |
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US20120086108A1 (en) | 2012-04-12 |
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