CN201681864U - 埋入型单基岛多圈引脚无源器件封装结构 - Google Patents

埋入型单基岛多圈引脚无源器件封装结构 Download PDF

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CN201681864U
CN201681864U CN2010201774505U CN201020177450U CN201681864U CN 201681864 U CN201681864 U CN 201681864U CN 2010201774505 U CN2010201774505 U CN 2010201774505U CN 201020177450 U CN201020177450 U CN 201020177450U CN 201681864 U CN201681864 U CN 201681864U
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王新潮
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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Abstract

本实用新型涉及一种埋入型单基岛多圈引脚无源器件封装结构，包括基岛(1)、引脚(2)、导电或不导电粘结物质(6)、芯片(7)、金属线(8)和有填料塑封料(9)，在所述基岛(1)和引脚(2)的正面设置有第一金属层(4)，在所述引脚(2)的背面设置有第二金属层(5)，在引脚(2)与引脚(2)之间或引脚(2)与基岛(1)之间跨接有无源器件(10)，在引脚(2)外围、基岛(1)背面、基岛(1)与引脚(2)之间的区域以及引脚(2)与引脚(2)之间的区域嵌置无填料塑封料(3)，所述无填料塑封料(3)将引脚(2)下部外围、基岛(1)背面、基岛(1)背面与引脚(2)的下部以及引脚(2)与引脚(2)的下部连接成一体，且使所述引脚(2)背面尺寸小于引脚(2)正面尺寸，所述基岛(1)设置有一个，引脚(2)设置有多圈。本实用新型的有益效果是：塑封体与金属脚的束缚能力大。

Description

埋入型单基岛多圈引脚无源器件封装结构
(一)技术领域
本实用新型涉及一种埋入型单基岛多圈引脚无源器件封装结构。属于半导体封装技术领域。
(二)背景技术
传统的封装结构，详细如下说明：
采用金属基板的正面进行化学蚀刻及表面电镀层后，即完成引线框的制作(如图3所示)。而引线框的背面则在封装过程中再进行背面蚀刻。
而上述的引线框在封装过程中存在了以下的不足点：
此种的引线框架结构在金属基板正面进行了半蚀刻工艺，因为只在金属基板正面进行了半蚀刻工作，而在塑封过程中塑封料只有包覆住半只脚的高度，所以塑封体与金属脚的束缚能力就变小了，如果塑封体贴片到PCB板上不是很好时，再进行返工重贴，就容易产生掉脚的问题(如图4所示)。
尤其塑封料的种类是采用有填料时候，因为材料在生产过程的环境与后续表面贴装的应力变化关系，会造成金属与塑封料产生垂直型的裂缝，其特性是填料比例越高则越硬越脆越容易产生裂缝。
(三)发明内容
本实用新型的目的在于克服上述不足，提供一种塑封体与金属脚的束缚能力大的埋入型单基岛多圈引脚无源器件封装结构。
本实用新型的目的是这样实现的：一种埋入型单基岛多圈引脚无源器件封装结构，包括基岛、引脚、导电或不导电粘结物质、芯片、金属线和有填料塑封料，在所述基岛和引脚的正面设置有第一金属层，在所述引脚的背面设置有第二金属层，在基岛正面通过导电或不导电粘结物质设置有芯片，芯片正面与引脚正面第一金属层之间用金属线连接，在引脚与引脚之间或引脚与基岛之间跨接有无源器件，在所述基岛和引脚的上部以及芯片、金属线和无源器件外包封有填料塑封料，所述基岛设置有一个，引脚设置有多圈，在所述引脚外围、基岛背面、基岛与引脚之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料，所述无填料塑封料将引脚下部外围、基岛背面、基岛背面与引脚的下部以及引脚与引脚的下部连接成一体，且使所述引脚背面尺寸小于引脚正面尺寸，形成上大下小的引脚结构。
本实用新型的有益效果是：
1)由于在所述金属脚与金属脚间的区域嵌置无填料软性填缝剂，该无填料软性填缝剂与在塑封过程中的常规有填料塑封料一起包覆住整个金属脚的高度，所以塑封体与金属脚的束缚能力就变大了，不会再有产生掉脚的问题。
2)由于采用了正面与背面分开蚀刻作业的方法，所以在蚀刻作业中可形成背面基岛的尺寸稍小而正面基岛尺寸稍大的结构，而同个基岛的上下大小不同尺寸在被无填料塑封料所包覆的更紧更不容易产生滑动而掉脚。
(四)附图说明
图1为本实用新型埋入型单基岛多圈引脚无源器件封装结构示意图。
图2为图1的俯视图。
图3为以往形成绝缘脚示意图。
图4为以往形成的掉脚图。
图中附图标记：
基岛1、引脚2、无填料塑封料3、第一金属层4、第二金属层5、导电或不导电粘结物质6、芯片7、金属线8、有填料塑封料9、无源器件10。
(五)具体实施方式
参见图1～2，图1为本实用新型埋入型单基岛多圈引脚无源器件封装结构示意图。图2为图1的俯视图。由图1和图2可以看出，本实用新型埋入型单基岛多圈引脚无源器件封装结构，包括基岛1、引脚2、导电或不导电粘结物质6、芯片7、金属线8和有填料塑封料9，在所述基岛1和引脚2的正面设置有第一金属层4，在所述引脚2的背面设置有第二金属层5，在基岛1正面通过导电或不导电粘结物质6设置有芯片7，芯片7正面与引脚2正面第一金属层4之间用金属线8连接，在引脚2与引脚2之间或引脚2与基岛1之间跨接有无源器件10，在所述基岛1和引脚2的上部以及芯片7、金属线8和无源器件10外包封有填料塑封料9，所述基岛1设置有一个，引脚2设置有多圈，在所述引脚2外围、基岛1背面、基岛1与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3，所述无填料塑封料3将引脚2下部外围、基岛1背面、基岛1背面与引脚2的下部以及引脚2与引脚2的下部连接成一体，且使所述引脚2背面尺寸小于引脚2正面尺寸，形成上大下小的引脚结构。

Claims (1)

1.一种埋入型单基岛多圈引脚无源器件封装结构，包括基岛(1)、引脚(2)、导电或不导电粘结物质(6)、芯片(7)、金属线(8)和有填料塑封料(9)，在所述基岛(1)和引脚(2)的正面设置有第一金属层(4)，在所述引脚(2)的背面设置有第二金属层(5)，在基岛(1)正面通过导电或不导电粘结物质(6)设置有芯片(7)，芯片(7)正面与引脚(2)正面第一金属层(4)之间用金属线(8)连接，在引脚(2)与引脚(2)之间或引脚(2)与基岛(1)之间跨接有无源器件(10)，在所述基岛(1)和引脚(2)的上部以及芯片(7)、金属线(8)和无源器件(10)外包封有填料塑封料(9)，其特征在于：所述基岛(1)设置有一个，引脚(2)设置有多圈，在所述引脚(2)外围、基岛(1)背面、基岛(1)与引脚(2)之间的区域以及引脚(2)与引脚(2)之间的区域嵌置无填料塑封料(3)，所述无填料塑封料(3)将引脚(2)下部外围、基岛(1)背面、基岛(1)背面与引脚(2)的下部以及引脚(2)与引脚(2)的下部连接成一体，且使所述引脚(2)背面尺寸小于引脚(2)正面尺寸，形成上大下小的引脚结构。
CN2010201774505U 2010-04-26 2010-04-26 埋入型单基岛多圈引脚无源器件封装结构 Expired - Lifetime CN201681864U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108321151A (zh) * 2018-01-24 2018-07-24 矽力杰半导体技术(杭州)有限公司 芯片封装组件及其制造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108321151A (zh) * 2018-01-24 2018-07-24 矽力杰半导体技术(杭州)有限公司 芯片封装组件及其制造方法
US20190229043A1 (en) * 2018-01-24 2019-07-25 Silergy Semiconductor Technology (Hangzhou) Ltd Chip Package Assembly And Method For Manufacturing The Same
US10950528B2 (en) 2018-01-24 2021-03-16 Silergy Semiconductor Technology (Hangzhou) Ltd Chip package assembly and method for manufacturing the same
TWI744562B (zh) * 2018-01-24 2021-11-01 大陸商矽力杰半導體技術（杭州）有限公司 晶片封裝組件及其製造方法
US11605578B2 (en) 2018-01-24 2023-03-14 Silergy Semiconductor Technology (Hangzhou) Ltd Chip package assembly and method for manufacturing the same

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