CN201681873U - 多个基岛露出型单圈引脚封装结构 - Google Patents

多个基岛露出型单圈引脚封装结构 Download PDF

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CN201681873U
CN201681873U CN2010201777787U CN201020177778U CN201681873U CN 201681873 U CN201681873 U CN 201681873U CN 2010201777787 U CN2010201777787 U CN 2010201777787U CN 201020177778 U CN201020177778 U CN 201020177778U CN 201681873 U CN201681873 U CN 201681873U
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王新潮
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
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    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

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Abstract

本实用新型涉及一种多个基岛露出型单圈引脚封装结构，包括基岛(1)、引脚(2)、导电或不导电粘结物质(6)、芯片(7)、金属线(8)和有填料塑封料(9)，所述基岛(1)设置有多个，引脚(2)设置有一圈，在所述基岛(1)和引脚(2)的正面和背面分别设置有第一金属层(4)和第二金属层(5)在所述引脚(2)外围、基岛(1)与基岛(1)之间的区域以及基岛(1)与引脚(2)之间的区域嵌置无填料塑封料(3)，所述无填料的塑封料(3)将引脚(2)下部外围、基岛(1)与基岛(1)的下部以及基岛(1)与引脚(2)的下部连接成一体，且使所述基岛(1)和引脚(2)背面尺寸小于基岛(1)和引脚(2)正面尺寸，形成上大下小的基岛和引脚结构。本实用新型的有益效果是：塑封体与金属脚的束缚能力大。

Description

多个基岛露出型单圈引脚封装结构
(一)技术领域
本实用新型涉及一种多个基岛露出型单圈引脚封装结构。属于半导体封装技术领域。
(二)背景技术
传统的封装结构主要有二种：
第一种：采用金属基板的正面进行化学蚀刻及表面电镀层后，在金属基板的背面贴上一层耐高温的胶膜形成可以进行封装过程的引线框载体(如图3所示)；
第二种：采用金属基板的正面进行化学蚀刻及表面电镀层后，即完成引线框的制作(如图4所示)。而引线框的背面则在封装过程中再进行背面蚀刻。
而上述的二种引线框在封装过程中存在了以下的不足点：
第一种：
1)此种的引线框架因背面必须要贴上一层昂贵可抗高温的胶膜。所以直接增加了高昂的成本。
2)也因为此种的引线框架的背面必须要贴上一层可抗高温的胶膜，所以在封装过程中的装片工艺只能使用导电或是不导电的树脂工艺，而完全不能采用共晶工艺以及软焊料的工艺进行装片，所以可选择的产品种类就有较大的局限性。
3)又因为此种的引线框架的背面必须要贴上一层可抗高温的胶膜，而在封装过程中的球焊键合工艺中，因为此可抗高温的胶膜是软性材质，所以造成了球焊键合参数的不稳定，严重的影响了球焊的质量与产品可靠度的稳定性。
4)再因为此种的引线框架的背面必须要贴上一层可抗高温的胶膜，而在封装过程中的塑封工艺过程，因为塑封的高压关系很容易造成引线框架与胶膜之间渗入塑封料，而将原本应属金属脚是导电的型态因为渗入了塑封料反而变成了绝缘脚(如图5所示)。
第二种：
此种的引线框架结构在金属基板正面进行了半蚀刻工艺，虽然可以解决第一种引线框架的问题，但是因为只在金属基板正面进行了半蚀刻工作，而在塑封过程中塑封料只有包覆住半只脚的高度，所以塑封体与金属脚的束缚能力就变小了，如果塑封体贴片到PCB板上不是很好时，再进行返工重贴，就容易产生掉脚的问题(如图6所示)。
尤其塑封料的种类是采用有填料时候，因为材料在生产过程的环境与后续表面贴装的应力变化关系，会造成金属与塑封料产生垂直型的裂缝，其特性是填料比例越高则越硬越脆越容易产生裂缝。
(三)发明内容
本实用新型的目的在于克服上述不足，提供一种降低封装成本、可选择的产品种类广、球焊的质量与产品可靠度的稳定性好、塑封体与金属脚的束缚能力大的多个基岛露出型单圈引脚封装结构。
本实用新型的目的是这样实现的：一种多个基岛露出型单圈引脚封装结构，包括基岛、引脚、导电或不导电粘结物质、芯片、金属线和有填料塑封料，在所述基岛和引脚的正面和背面分别设置有第一金属层和第二金属层，在基岛正面通过导电或不导电粘结物质设置有芯片，芯片正面与引脚正面第一金属层之间用金属线连接，在所述基岛和引脚的上部以及芯片和金属线外包封有填料塑封料，所述基岛设置有多个，引脚设置有一圈，在所述引脚外围、基岛与基岛之间的区域以及基岛与引脚之间的区域嵌置无填料塑封料，所述无填料的塑封料将引脚下部外围、基岛与基岛的下部以及基岛与引脚的下部连接成一体，且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸，形成上大下小的基岛和引脚结构。
本实用新型的有益效果是：
1)此种的引线框的背面不须要贴上一层昂贵可抗高温的胶膜。所以直接降低了高昂的成本。
2)也因为此种的引线框架的背面不须要贴上一层可抗高温的胶膜，所以在封装过程中的装片工艺除了能使用导电或是不导电的树脂工艺外，还能采用共晶工艺以及软焊料的工艺进行装片，所以可选择的产品种类就广。
3)又因为此种的引线框架的背面不须要贴上一层可抗高温的胶膜，确保了球焊键合参数的稳定性，保证了球焊的质量与产品可靠度的稳定性。
4)再因为此种的引线框架不须要贴上一层可抗高温的胶膜，而在封装过程中的塑封工艺过程，完全不会造成引线框与胶膜之间渗入塑封料。
5)由于在所述金属脚(引脚)与金属脚间的区域嵌置无填料软性填缝剂，该无填料的软性填缝剂与在塑封过程中的常规有填料塑封料一起包覆住整个金属脚的高度，所以塑封体与金属脚的束缚能力就变大了，不会再有产生掉脚的问题。
6)由于采用了正面与背面分开蚀刻作业的方法，所以在蚀刻作业中可形成背面基岛的尺寸稍小而正面基岛尺寸稍大的结构，而同个基岛的上下大小不同尺寸在被无填料的塑封料所包覆的更紧更不容易产生滑动而掉脚。
(四)附图说明
图1为本实用新型多个基岛露出型单圈引脚封装结构示意图。
图2为图1的俯视图。
图3为以往在金属基板的背面贴上一层耐高温的胶膜图作业。
图4为以往采用金属基板的正面进行化学蚀刻及表面电镀层作业图。
图5为以往形成绝缘脚示意图。
图6为以往形成的掉脚图。
图中附图标记：
基岛1、引脚2、无填料的塑封料3、第一金属层4、第二金属层5、导电或不导电粘结物质6、芯片7、金属线8、有填料塑封料9。
(五)具体实施方式
参见图1～2，图1为本实用新型多个基岛露出型单圈引脚封装结构示意图。图2为图1的俯视图。由图1和图2可以看出，本实用新型多个基岛露出型单圈引脚封装结构，包括基岛1、引脚2、导电或不导电粘结物质6、芯片7、金属线8和有填料塑封料9，在所述基岛1和引脚2的正面和背面分别设置有第一金属层4和第二金属层5，在基岛1正面通过导电或不导电粘结物质6设置有芯片7，芯片7正面与引脚2正面第一金属层4之间用金属线8连接，在所述基岛1和引脚2的上部以及芯片7和金属线8外包封有填料塑封料9，所述基岛1设置有多个，引脚2设置有一圈，在所述引脚2外围、基岛1与基岛1之间的区域以及基岛1与引脚2之间的区域嵌置无填料塑封料3，所述无填料的塑封料3将引脚2下部外围、基岛1与基岛1的下部以及基岛1与引脚2的下部连接成一体，且使所述基岛1和引脚2背面尺寸小于基岛1和引脚2正面尺寸，形成上大下小的基岛和引脚结构。

Claims (1)

1.一种多个基岛露出型单圈引脚封装结构，包括基岛(1)、引脚(2)、导电或不导电粘结物质(6)、芯片(7)、金属线(8)和有填料塑封料(9)，在所述基岛(1)和引脚(2)的正面和背面分别设置有第一金属层(4)和第二金属层(5)，在基岛(1)正面通过导电或不导电粘结物质(6)设置有芯片(7)，芯片(7)正面与引脚(2)正面第一金属层(4)之间用金属线(8)连接，在所述基岛(1)和引脚(2)的上部以及芯片(7)和金属线(8)外包封有填料塑封料(9)，其特征在于：所述基岛(1)设置有多个，引脚(2)设置有一圈，在所述引脚(2)外围、基岛(1)与基岛(1)之间的区域以及基岛(1)与引脚(2)之间的区域嵌置无填料塑封料(3)，所述无填料的塑封料(3)将引脚(2)下部外围、基岛(1)与基岛(1)的下部以及基岛(1)与引脚(2)的下部连接成一体，且使所述基岛(1)和引脚(2)背面尺寸小于基岛(1)和引脚(2)正面尺寸，形成上大下小的基岛和引脚结构。
CN2010201777787U 2010-04-26 2010-04-26 多个基岛露出型单圈引脚封装结构 Expired - Lifetime CN201681873U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109979892A (zh) * 2019-03-29 2019-07-05 无锡红光微电子股份有限公司 Esop8双基岛封装框架
CN113571434A (zh) * 2021-06-07 2021-10-29 华宇华源电子科技（深圳）有限公司 一种新型的面板级封装方法及结构

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109979892A (zh) * 2019-03-29 2019-07-05 无锡红光微电子股份有限公司 Esop8双基岛封装框架
CN113571434A (zh) * 2021-06-07 2021-10-29 华宇华源电子科技（深圳）有限公司 一种新型的面板级封装方法及结构
CN113571434B (zh) * 2021-06-07 2023-11-17 华宇华源电子科技（深圳）有限公司 一种新型的面板级封装方法及结构

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