CN102779763A - 一种基于腐蚀的aaqfn产品的二次塑封制作工艺 - Google Patents
一种基于腐蚀的aaqfn产品的二次塑封制作工艺 Download PDFInfo
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- CN102779763A CN102779763A CN2012101822165A CN201210182216A CN102779763A CN 102779763 A CN102779763 A CN 102779763A CN 2012101822165 A CN2012101822165 A CN 2012101822165A CN 201210182216 A CN201210182216 A CN 201210182216A CN 102779763 A CN102779763 A CN 102779763A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2012101822165A CN102779763A (zh) | 2012-06-05 | 2012-06-05 | 一种基于腐蚀的aaqfn产品的二次塑封制作工艺 |
Applications Claiming Priority (1)
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CN2012101822165A CN102779763A (zh) | 2012-06-05 | 2012-06-05 | 一种基于腐蚀的aaqfn产品的二次塑封制作工艺 |
Publications (1)
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CN102779763A true CN102779763A (zh) | 2012-11-14 |
Family
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CN2012101822165A Pending CN102779763A (zh) | 2012-06-05 | 2012-06-05 | 一种基于腐蚀的aaqfn产品的二次塑封制作工艺 |
Country Status (1)
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CN (1) | CN102779763A (zh) |
Citations (17)
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CN1309425A (zh) * | 2000-02-18 | 2001-08-22 | 株式会社日立制作所 | 半导体集成电路器件及其制造方法 |
CN1836319A (zh) * | 2003-06-25 | 2006-09-20 | 先进互连技术有限公司 | 半导体封装中芯片衬垫布线的引线框 |
CN1905142A (zh) * | 2006-08-01 | 2007-01-31 | 上海凯虹科技电子有限公司 | 新型qfn芯片封装工艺 |
CN101694837A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双排引脚的四面扁平无引脚封装件及其生产方法 |
CN101694838A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双扁平无引脚封装件及其生产方法 |
CN101697348A (zh) * | 2009-10-11 | 2010-04-21 | 天水华天科技股份有限公司 | 一种小载体四面扁平无引脚封装件及其制备方法 |
CN101740416A (zh) * | 2009-12-11 | 2010-06-16 | 上海凯虹科技电子有限公司 | 一种四方扁平无引脚封装结构及其封装方法 |
CN101740407A (zh) * | 2008-11-25 | 2010-06-16 | 三星电子株式会社 | 四方扁平无外引脚封装结构的封装工艺 |
CN101826501A (zh) * | 2009-03-06 | 2010-09-08 | 李同乐 | 高密度接点的无引脚集成电路元件 |
CN101853790A (zh) * | 2009-03-30 | 2010-10-06 | 飞思卡尔半导体公司 | Col封装的新工艺流 |
CN102074541A (zh) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 |
CN102222658A (zh) * | 2011-06-30 | 2011-10-19 | 天水华天科技股份有限公司 | 多圈排列ic芯片封装件及其生产方法 |
CN102263081A (zh) * | 2011-07-29 | 2011-11-30 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法 |
CN102324415A (zh) * | 2011-09-13 | 2012-01-18 | 江苏长电科技股份有限公司 | 无基岛预填塑封料先刻后镀引线框结构及其生产方法 |
CN102354691A (zh) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | 一种高密度四边扁平无引脚封装及制造方法 |
CN102354689A (zh) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | 一种面阵引脚排列四边扁平无引脚封装及制造方法 |
CN102365737A (zh) * | 2009-03-30 | 2012-02-29 | 凸版印刷株式会社 | 半导体元件用基板的制造方法及半导体器件 |
-
2012
- 2012-06-05 CN CN2012101822165A patent/CN102779763A/zh active Pending
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1309425A (zh) * | 2000-02-18 | 2001-08-22 | 株式会社日立制作所 | 半导体集成电路器件及其制造方法 |
CN1836319A (zh) * | 2003-06-25 | 2006-09-20 | 先进互连技术有限公司 | 半导体封装中芯片衬垫布线的引线框 |
CN1905142A (zh) * | 2006-08-01 | 2007-01-31 | 上海凯虹科技电子有限公司 | 新型qfn芯片封装工艺 |
CN101740407A (zh) * | 2008-11-25 | 2010-06-16 | 三星电子株式会社 | 四方扁平无外引脚封装结构的封装工艺 |
CN101826501A (zh) * | 2009-03-06 | 2010-09-08 | 李同乐 | 高密度接点的无引脚集成电路元件 |
CN102365737A (zh) * | 2009-03-30 | 2012-02-29 | 凸版印刷株式会社 | 半导体元件用基板的制造方法及半导体器件 |
CN101853790A (zh) * | 2009-03-30 | 2010-10-06 | 飞思卡尔半导体公司 | Col封装的新工艺流 |
CN101697348A (zh) * | 2009-10-11 | 2010-04-21 | 天水华天科技股份有限公司 | 一种小载体四面扁平无引脚封装件及其制备方法 |
CN101694838A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双扁平无引脚封装件及其生产方法 |
CN101694837A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双排引脚的四面扁平无引脚封装件及其生产方法 |
CN101740416A (zh) * | 2009-12-11 | 2010-06-16 | 上海凯虹科技电子有限公司 | 一种四方扁平无引脚封装结构及其封装方法 |
CN102074541A (zh) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 |
CN102222658A (zh) * | 2011-06-30 | 2011-10-19 | 天水华天科技股份有限公司 | 多圈排列ic芯片封装件及其生产方法 |
CN102263081A (zh) * | 2011-07-29 | 2011-11-30 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法 |
CN102324415A (zh) * | 2011-09-13 | 2012-01-18 | 江苏长电科技股份有限公司 | 无基岛预填塑封料先刻后镀引线框结构及其生产方法 |
CN102354691A (zh) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | 一种高密度四边扁平无引脚封装及制造方法 |
CN102354689A (zh) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | 一种面阵引脚排列四边扁平无引脚封装及制造方法 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C53 | Correction of patent of invention or patent application | ||
CB03 | Change of inventor or designer information |
Inventor after: Guo Xiaowei Inventor after: Zhu Wenhui Inventor after: Chen Shiguang Inventor after: Cui Meng Inventor after: Pu Hongming Inventor before: Guo Xiaowei Inventor before: Luo Yuguang Inventor before: Cui Meng Inventor before: Pu Hongming |
|
COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: GUO XIAOWEI LUO YUGUANG CUI MENG PU HONGMING TO: GUO XIAOWEI ZHU WENHUI CHEN SHIGUANG CUI MENG PU HONGMING |
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C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20121114 |
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RJ01 | Rejection of invention patent application after publication |