CN103021885A - 一种基于喷砂的扁平封装件制作工艺 - Google Patents

一种基于喷砂的扁平封装件制作工艺 Download PDF

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CN103021885A
CN103021885A CN2012105274009A CN201210527400A CN103021885A CN 103021885 A CN103021885 A CN 103021885A CN 2012105274009 A CN2012105274009 A CN 2012105274009A CN 201210527400 A CN201210527400 A CN 201210527400A CN 103021885 A CN103021885 A CN 103021885A
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郭小伟
刘建军
崔梦
李万霞
魏海东
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Huatian Technology Xian Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

本发明涉及一种基于喷砂的扁平封装件制作工艺,属于集成电路封装技术领域。本发明使用框架,在生产流程中能够很大程度上的简化生产工艺,降低成本以及减少报废率,然后在框架上用腐蚀的方法形成凹槽,再用先喷砂后刷绿漆的方法填充,并能在一次塑封的塑封料和框架间形成更加有效的防拖拉结构,显著提高封装件的可靠性,且此法易行,生产效率高。

Description

一种基于喷砂的扁平封装件制作工艺
技术领域
本发明涉及一种基于喷砂的扁平封装件制作工艺,属于集成电路封装技术领域。
背景技术    
集成电路是信息产业和高新技术的核心,是经济发展的基础。集成电路封装是集成电路产业的主要组成部分,它的发展一直伴随着其功能和器件数的增加而迈进。自20世纪90年代起,它进入了多引脚数、窄间距、小型薄型化的发展轨道。无载体栅格阵列封装(即AAQFN)是为适应电子产品快速发展而诞生的一种新的封装形式,是电子整机实现微小型化、轻量化、网络化必不可少的产品。
    无载体栅格阵列封装元件,底部没有焊球,焊接时引脚直接与PCB板连接,与PCB的电气和机械连接是通过在PCB焊盘上印刷焊膏,配合SMT回流焊工艺形成的焊点来实现的。该技术封装可以在同样尺寸条件下实现多引脚、高密度、小型薄型化封装,具有散热性、电性能以及共面性好等特点。
AAQFN封装产品适用于大规模、超大规模集成电路的封装。AAQFN封装的器件大多数用于手机、网络及通信设备、数码相机、微机、笔记本电脑和各类平板显示器等高档消费品市场。掌握其核心技术,具备批量生产能力,将大大缩小国内集成电路产业与国际先进水平的差距,该产品有着广阔市场应用前景。
但是由于技术难度等限制,目前AAQFN产品在市场上的推广有一定难度,尤其是在可靠性方面,直接影响产品的使用及寿命,已成为AAQFN封装件的技术攻关难点。
发明内容
为了克服上述现有技术存在的问题,本发明提供一种基于喷砂的扁平封装件制作工艺,使集成电路框架与塑封体结合更加牢固,不受外界环境影响,直接提高产品的封装可靠性,并在一定程度上降低成本。
本发明采用的技术方案:一种基于喷砂的扁平封装件制作工艺,具体按照以下步骤进行:
第一步、减薄:减薄厚度为50μm~200μm,粗糙度Ra 0.10um~0.30um;
第二步、划片:厚度在150μm以上晶圆采用普通QFN划片工艺,厚度在150μm以下晶圆,使用双刀划片机及其工艺;
第三步、上芯:采用粘片胶上芯;
第四步、压焊;
第五步、一次塑封:用传统塑封料进行塑封;
第六步、后固化;
第七步、框架背面蚀刻凹槽:使用框架,用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内;
第八步、喷砂、刷绿漆;
第九步、后固化、磨胶、锡化、打印、产品分离、检验、包装。
所述的步骤中第三步可采用胶膜片(DAF)代替粘片胶;所述的步骤中第四步、第五步、第六步、第九步均与常规AAQFN工艺相同。
本发明的有益效果:使用框架,在生产流程中能够很大程度上的简化生产工艺,降低成本以及减少报废率,然后在框架上用腐蚀的方法形成凹槽,再用先喷砂后刷绿漆的方法填充,并能在一次塑封的塑封料和框架间形成更加有效的防拖拉结构,显著提高封装件的可靠性,且此法易行,生产效率高。
附图说明
图1  引线框架剖面图;
图2  上芯后产品剖面图;
图3  压焊后产品剖面图;
图4  一次塑封后产品剖面图;
图5  框架背面蚀刻后产品剖面图;
图6  喷砂刷绿漆后产品剖面图。
图中:1-引线框架、2-粘片胶、3-芯片、4-键合线、5-塑封体、6-蚀刻凹槽。
具体实施方式
下面结合附图和实施例对本发明做进一步说明,以方便技术人员理解。
如图1-6所示:采用本发明所述的方法用于单芯片封装,产品包括引线框架1、粘片胶2、芯片3、键合线4、塑封体5、蚀刻凹槽6;其中芯片3与引线框架1通过粘片胶2相连,键合线4直接从芯片3打到引线框架1上,引线框架1上是粘片胶2,粘片胶2上是芯片3,芯片3上的焊点与内引脚间的焊线是键合线4,塑封体5包围了引线框架1、粘片胶2、芯片3、键合线4、蚀刻凹槽6并一起构成了电路的整体,塑封体5对芯片3的键合线4起到了支撑和保护作用,芯片3、键合线4、引线框架1构成了电路的电源和信号通道。
一种基于喷砂的扁平封装件制作工艺,具体按照以下步骤进行:
实施例1
第一步、减薄:减薄厚度为100μm,粗糙度Ra 0.10um;
第二步、划片:采用厚度为100μm的晶圆,使用双刀划片机及其工艺;
第三步、上芯:采用粘片胶2上芯;
第四步、压焊:与常规AAQFN工艺相同;
第五步、一次塑封:用传统塑封料9920进行塑封,与常规AAQFN工艺相同;
第六步、后固化:与常规AAQFN工艺相同;
第七步、框架背面蚀刻凹槽:使用框架,用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内;
第八步、喷砂、刷绿漆;
第九步、后固化、磨胶、锡化、打印、产品分离、检验、包装与常规AAQFN工艺相同。
实施例2
第一步、减薄:减薄厚度为130μm,粗糙度Ra 0.20um;
第二步、划片:采用厚度为130μm的晶圆,使用双刀划片机及其工艺;
第三步、上芯:采用粘片胶2上芯;
第四步、压焊:与常规AAQFN工艺相同;
第五步、一次塑封:用传统塑封料9920进行塑封,与常规AAQFN工艺相同;
第六步、后固化:与常规AAQFN工艺相同;
第七步、框架背面蚀刻凹槽:使用框架,用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内;
第八步、喷砂、刷绿漆;
第九步、后固化、磨胶、锡化、打印、产品分离、检验、包装与常规AAQFN工艺相同。
实施例3
第一步、减薄:减薄厚度为170μm,粗糙度Ra 0.30um;
第二步、划片:采用厚度为170μm的晶圆,同普通QFN划片工艺相同;
第三步、上芯:采用粘片胶2上芯;
第四步、压焊:与常规AAQFN工艺相同;
第五步、一次塑封:用传统塑封料9920进行塑封,与常规AAQFN工艺相同;
第六步、后固化:与常规AAQFN工艺相同;
第七步、框架背面蚀刻凹槽:使用框架,用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内;
第八步、喷砂、刷绿漆;
第九步、后固化、磨胶、锡化、打印、产品分离、检验、包装与常规AAQFN工艺相同。
本发明通过具体实施过程进行说明的,在不脱离本发明范围的情况下,还可以对本发明专利进行各种变换及等同代替,因此,本发明专利不局限于所公开的具体实施过程,而应当包括落入本发明专利权利要求范围内的全部实施方案。

Claims (3)

1.一种基于喷砂的扁平封装件制作工艺,其特征在于:具体按照以下步骤进行:
第一步、减薄:减薄厚度为50μm~200μm,粗糙度Ra 0.10um~0.30um;
第二步、划片:150μm以上晶圆采用普通QFN划片工艺,厚度在150μm以下晶圆,使用双刀划片机及其工艺;
第三步、上芯:采用粘片胶上芯;
第四步、压焊;
第五步、一次塑封:用传统塑封料进行塑封;
第六步、后固化;
第七步、框架背面蚀刻凹槽:使用框架,用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内;
第八步、喷砂、刷绿漆;
第九步、后固化、磨胶、锡化、打印、产品分离、检验、包装。
2.根据权利要求1所述的一种基于喷砂的扁平封装件制作工艺,其特征在于:所述的步骤中第三步可采用胶膜片(DAF)代替粘片胶。
3.根据权利要求1所述的一种基于喷砂的扁平封装件制作工艺,其特征在于:所述的步骤中第四步、第五步、第六步、第九步均与常规AAQFN工艺相同。
CN2012105274009A 2012-12-10 2012-12-10 一种基于喷砂的扁平封装件制作工艺 Pending CN103021885A (zh)

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CN106356351A (zh) * 2015-07-15 2017-01-25 恒劲科技股份有限公司 基板结构及其制作方法

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CN102738015A (zh) * 2012-06-05 2012-10-17 华天科技(西安)有限公司 一种基于腐蚀、喷砂的aaqfn产品的二次塑封制作工艺
CN102738017A (zh) * 2012-06-13 2012-10-17 华天科技(西安)有限公司 一种基于喷砂的aaqfn产品的二次塑封制作工艺

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CN101697348A (zh) * 2009-10-11 2010-04-21 天水华天科技股份有限公司 一种小载体四面扁平无引脚封装件及其制备方法
CN102386106A (zh) * 2010-09-03 2012-03-21 宇芯(毛里求斯)控股有限公司 部分图案化的引线框以及在半导体封装中制造和使用其的方法
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CN102738017A (zh) * 2012-06-13 2012-10-17 华天科技(西安)有限公司 一种基于喷砂的aaqfn产品的二次塑封制作工艺

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106356351A (zh) * 2015-07-15 2017-01-25 恒劲科技股份有限公司 基板结构及其制作方法
CN106356351B (zh) * 2015-07-15 2019-02-01 凤凰先驱股份有限公司 基板结构及其制作方法

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