CN1905142A - 新型qfn芯片封装工艺 - Google Patents

新型qfn芯片封装工艺 Download PDF

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CN1905142A
CN1905142A CNA2006100296379A CN200610029637A CN1905142A CN 1905142 A CN1905142 A CN 1905142A CN A2006100296379 A CNA2006100296379 A CN A2006100296379A CN 200610029637 A CN200610029637 A CN 200610029637A CN 1905142 A CN1905142 A CN 1905142A
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chip
gold thread
packaging
lead frame
plastic packaging
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CN100409418C (zh
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谭小春
李云芳
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Shanghai Kaihong Sci & Tech Electronic Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本发明提供一种新型QFN芯片封装工艺，该封装工艺过程是：a.冲压金属薄板，制成引线框架，取代PPF框架；b.在引线框架表面上有芯片座和金线键合点；c.在芯片垫板上涂银胶；d.将芯片粘结到芯片垫板上，并完成后固化作业；e.用金线对芯片和金线键合点进行键合；f.在引线框架的表面用塑封料进行注模，塑封芯片和金线；g.塑封后剥离固定引线框架的金属薄板；h.将封装完成的产品阵列，进行激光打印；i.将打印好的器件陈列，背面贴上蓝膜，进行切割，切割后的产品剥离蓝膜，分成独立的器件；j.测试，包装成品。其优点在于：成本低廉，焊接性能强，品质优良，增长切割刀片寿命，不会产生金属毛刺。

Description

新型QFN芯片封装工艺
技术领域
本发明涉及一种新型QFN芯片的封装工艺，特别是一种高性能的新型QFN封装工艺，属集成电路或分立元件封装技术领域。
背景技术
传统的QFN封装，其封装型式主要通过单元阵列式的框架封装后经过切割成为独立的单元，其基板为蚀刻背面贴膜的框架。主要存在以下不足：
1.框架背面需贴专用耐高温膜，使用过程中由于高温加热，背面贴膜会散发出有害化学物质，造成框架和芯片打线区域的污染，影响焊线工艺质量，影响产品品质。
2.背面膜的成本高，框架使用PPF工艺，从而导致了框架的价格比一般的框架高，从而提高了整体封装的成本。
3.使用切割刀切割分离器件，切割过程中切割刀在切割塑封料的同时也会切到金属。造成产品引脚边缘卷边，减少刀片寿命，影响产品品质和SMT质量。
4.塑封时，框架引脚和塑封料的底部一样平，在表面贴装时焊接能力表现不好。
发明内容
本发明的目的在于解决上述芯片封装工艺存在的不足，提供一种成本低廉，焊接性能强，品质优良，增长切割刀片寿命的新型QFN芯片封装工艺。该封装工艺过程是：
a、冲压金属薄板，制成引线框架，取代PPF框架；并用薄板配合固定框架取代背面高温贴膜；在引线框架表面上有芯片座和金线键合点；
b、在芯片座上涂银胶；
c、将芯片粘结到芯片座上，并完成后固化作业；
d、用金线对芯片和金线键合点进行键合；
e、在引线框架的表面用塑封料进行注模，塑封芯片和金线；
f、塑封后剥离固定引线框架的金属薄板；
g、将封装完成的产品阵列，进行激光打印；
h、将打印好的器件陈列，背面贴上蓝膜，进行切割，切割后的产品剥离蓝膜，分成独立的器件；
j、测试，包装成品。
引线框架的金属薄板厚度在0.05至0.30mm之间，金属薄板由铜合金材料组成。在键合芯片时，不存在背面高温贴膜。塑封不包括对固定引线框架的薄板塑封。
本发明的特点在于，首先，新型框架取代贴膜PPF框架。新型框架采用特殊冲压框架，用金属薄板取代原来的背面贴膜来固定各个独立的框架单元。而框架内部设计相应独立，无相连的筋连接每一个单元之间，在塑封后减少了器件切割时切割刀切割金属造成的磨损及刀片寿命的减少及相应的缺陷。由于框架背面不存在贴膜，化学物质污染框架和芯片的情况将被杜绝，由此产生的焊线质量问题将不复存在。
其次，将完成金线键合作业的框架进行塑封作业时由于金属薄板取代背面贴膜，塑封完成后需要将引线框架的金属薄板剥离，此时引脚外露的阵列式塑封器件集合体便产生了。
再次，将完成薄板剥离作业的塑封体反贴到UV膜上，利用切割机器将胶体分割开来时，由于器件之间没有金属筋相连，故切割刀切割时只会切到塑封料，不会切割到金属，从而延长了切割刀的寿命，金属毛刺的缺点也彻底解决。
上述工艺过程与传统的QFN封装相比具有如下优点：
1.不需使用专用高温贴膜，减少有害气体对金线键合品质的影响，材料成本低。
2.新型封装体进行切割时，切割刀只会切到胶体，不会切到金属框架，不会造成切割刀寿命的减少，也没有造成金属毛刺的现象。
3.引脚外露方便器件表面贴装，提高焊接质量。
附图说明
附图1(包括附图1a、附图1b、1c)是本实用新型的框架结构图。
附图2是在芯片垫板上涂上银胶。
附图3是芯片粘结于银胶上后固化。
附图4在芯片上进行金线键合。
附图5是对键合后的芯片进行塑封。
附图6是剥离框架背面的金属薄板后的产品示意图。
附图7是对产品进行切割的示意图。
附图8(包括附图8a、8b、8c、8d)是切割成独立器件的产品示意图。
附图中标号说明
1-芯片垫板          2-银胶
3-芯片              4-金线
5-外层塑封料        6-引线框架
具体实施方式
参阅附图1所示，图1a是新型框架的俯视图，图1b是框架的背面视图，图1c是框架的截面视图；图1a中的标号1是芯片垫板。附图2是在芯片垫板1上涂上银胶2。附图3是在银胶2上，粘贴芯片3，然后完成固化作业。附图4是根据产品的特性进行金线4键合。附图5是将键合好的产品，依据塑封料的特性进行塑封作业，5是外层塑封料，封装后需要将金属引线框架6剥离，使底层引脚金属外露，如附图6所示。
参阅附图8所示，其中：图8a是切割成独立器件后，产品的俯视图；图8b是图8a的背面视图；图8c是独立的产品器件内部结构图；图8d是截面视图。

Claims (5)

1、一种新型QFN芯片封装工艺，其特征在于：其封装工艺的过程是：
a、冲压金属薄板，制成引线框架，取代PPF框架；
b、在引线框架表面上有芯片座和金线键合点；
c、在芯片座上涂银胶；
d、将芯片粘结到芯片座上，并完成后固化作业；
e、用金线对芯片和金线键合点进行键合；
f、在引线框架的表面用塑封料进行注模，塑封芯片和金线；
g、塑封后剥离固定引线框架的金属薄板；
h、将封装完成的产品阵列，进行激光打印；
i、将打印好的器件陈列，背面贴上蓝膜，进行切割，切割后的产品剥离蓝膜，分成独立的器件；
j、测试，包装成品。
2、根据权利要求1所述的新型QFN芯片封装工艺，其特征在于：所述的固定引线框架的金属薄板厚度在0.05至0.30mm之间。
3、根据权利要求1所述的新型QFN芯片封装工艺，其特征在于：所述的金属薄板由铜合金材料组成。
4、根据权利要求1所述的新型QFN芯片封装工艺，其特征在于：在键合芯片时，不能有耐高温贴膜的存在。
5、根据权利要求1所述的新型QFN芯片封装工艺，其特征在于：塑封不包括对固定引线框架薄板的塑封。
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CN100568477C (zh) * 2008-07-30 2009-12-09 江苏长电科技股份有限公司 金属平板式半导体封装方法
CN100568476C (zh) * 2008-07-30 2009-12-09 江苏长电科技股份有限公司 凹槽金属板式半导体封装方法
CN102082100A (zh) * 2009-11-30 2011-06-01 万国半导体有限公司 一种用于引脚凸出的半导体器件的封装方法
CN102244058A (zh) * 2010-05-13 2011-11-16 群丰科技股份有限公司 四方扁平无导脚的半导体封装件及制法及该制造用金属板
CN102290358A (zh) * 2011-08-26 2011-12-21 上海凯虹电子有限公司 四方扁平无引脚封装体及其制造方法
CN102544262A (zh) * 2012-01-17 2012-07-04 成都泰鼎科技有限公司 一种led芯片封装工艺
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CN100568476C (zh) * 2008-07-30 2009-12-09 江苏长电科技股份有限公司 凹槽金属板式半导体封装方法
CN100568477C (zh) * 2008-07-30 2009-12-09 江苏长电科技股份有限公司 金属平板式半导体封装方法
CN101697348B (zh) * 2009-10-11 2013-06-26 天水华天科技股份有限公司 一种小载体四面扁平无引脚封装件及其制备方法
CN102074534B (zh) * 2009-11-24 2013-05-29 上海长丰智能卡有限公司 一种微型pcb射频模块及其封装方法
CN102082100B (zh) * 2009-11-30 2013-05-15 万国半导体有限公司 一种用于引脚凸出的半导体器件的封装方法
CN102082100A (zh) * 2009-11-30 2011-06-01 万国半导体有限公司 一种用于引脚凸出的半导体器件的封装方法
CN102244058A (zh) * 2010-05-13 2011-11-16 群丰科技股份有限公司 四方扁平无导脚的半导体封装件及制法及该制造用金属板
CN102290358A (zh) * 2011-08-26 2011-12-21 上海凯虹电子有限公司 四方扁平无引脚封装体及其制造方法
CN102544262A (zh) * 2012-01-17 2012-07-04 成都泰鼎科技有限公司 一种led芯片封装工艺
CN102779763A (zh) * 2012-06-05 2012-11-14 华天科技（西安）有限公司 一种基于腐蚀的aaqfn产品的二次塑封制作工艺
CN108649020A (zh) * 2018-05-18 2018-10-12 上海凯虹科技电子有限公司 堆叠芯片的封装方法及采用该方法制造的封装体
CN109326529A (zh) * 2018-09-29 2019-02-12 中电智能卡有限责任公司 一种dfn/qfn生产工艺
CN113507785A (zh) * 2021-06-08 2021-10-15 广州致远电子有限公司 一种基于变压器的封装模块制备方法

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