CN101697348B - 一种小载体四面扁平无引脚封装件及其制备方法 - Google Patents
一种小载体四面扁平无引脚封装件及其制备方法 Download PDFInfo
- Publication number
- CN101697348B CN101697348B CN2009101175093A CN200910117509A CN101697348B CN 101697348 B CN101697348 B CN 101697348B CN 2009101175093 A CN2009101175093 A CN 2009101175093A CN 200910117509 A CN200910117509 A CN 200910117509A CN 101697348 B CN101697348 B CN 101697348B
- Authority
- CN
- China
- Prior art keywords
- carrier
- pin
- chip
- bonding
- packaging part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
一种小载体四面扁平无引脚封装件,包括引线框架载体、粘片胶、IC芯片、IC芯片上的焊盘、键合线及塑封体,其特征在于在切割分离前,所有内引脚向内延伸与所述载体相连,载体与内引脚之间设有凹槽,内引脚底部设有凹槽,载体背面设有一圈防溢料凹槽。经过减薄、划片、上芯、压焊、塑封、电镀、切割等工艺程序加工生产。本发明的小载体四面扁平无引脚封装的特点是载体缩小,在切割分离前,内引脚向内延伸与载体相连,内引脚与载体相连处有0.10mm的凹坑,凹坑外的引脚长度比普通QFN引脚长1mm,并且载体下部有一圈防溢料槽,可避免溢料继续向载体背面扩散。
Description
技术领域
本发明涉及电子信息自动化元器件制造技术领域,尤其涉及到一种小载体四面扁平无引脚封装件,本发明还包括该封装件的制备方法。
背景技术
近年来,移动通信和移动计算机领域的便捷式电子机器市场火爆,直接推动了小型封装和高密度组装技术的发展。同时,也对小型封装技术提出了一系列严格要求,诸如,要求封装外形尺寸尽量缩小,尤其是封装高度小于1mm;封装后的产品可靠性尽可能提高,为了保护环境适应无铅化焊接,及力图降低成本。小型化封装结构已有多种,如球栅阵列BGA封装等,但是,其内部的布线成本高,远不如QFP可实现低成本化。然而现行的QFP结构内部引出的引线呈羽翼状扇出,占用较大装配面积(手机内装面积十分有限),不能满足要求。2000年JEDEC制定出一种改进型规格,叫做QFN(Quad Flat Non-LeadedPackage),顾名思义,QFN把QFP扇出的引出线折回到封装底部(变成条状接触线),故可节省装配面积,进一步实现小型化。但是目前QFN(0707×0.75-0.50)载体较大,内引脚长度固定,而当IC芯片较小,致使焊线长度长,造成焊线成本较高,制约了产品的利润空间。
发明内容
本发明的目的就是针对上述QFN缺点,提供一种缩小了载体尺寸,在分离切割前所有的内引脚与载体相连的四面扁平无引脚封装件,从芯片上的焊盘(PAD)到内引脚的距离缩短。相应,从芯片焊盘到内引脚的焊线长度缩短,可降低焊线成本,适合于小芯片四面扁平无引脚产品封装。本发明还包括该封装件的生产方法。
本发明的目的通过下述技术方案实现:
一种小载体四面扁平无引脚封装件,包括引线框架载体、粘片胶、IC芯片、IC芯片上的焊盘、键合线及塑封体,其特征在于在切割分离前,所有内引脚向内延伸与所述载体相连,载体与内引脚之间设有凹槽,内引脚底部设有凹槽。
其封装生产按下述方法和步骤进行:
其封装生产按下述方法和步骤进行:
a、减薄
减薄厚度50μm~200μm,粗糙度Ra 0.10mm~0.05mm;
b、划片
150μm以上晶圆同普通QFN划片工艺,但厚度在150μm以下晶圆,使用双刀划片机及其工艺;
c、上芯(粘片)
d、压焊
e、塑封
f、电镀
g、切割
g1、先从切割线处切开内引线脚和内引线脚间的连接部分,切割深度为0.11μm+0.015μm;
g2、按正常工艺将矩阵式框架封装的单元产品切割成单个产品,机器自动检测合格后放入料盘。
所述封装工艺为芯片堆叠封装时,减薄厚度50μm~100μm。
所述芯片堆叠封装的上芯、粘片工序,底层采用膨胀系数80~195PPM/℃、吸水率<0.15%的导电胶或绝缘胶,上层采用绝缘胶膜片或绝缘胶。
所述绝缘胶膜片上芯,使用胶膜片上芯机及其烘烤工艺。
所述芯片堆叠封装的压焊工序,根据焊线直径和芯片焊盘尺寸大小,选择相匹配的柱状劈刀,采用高低弧和低弧反打键合方式。
所述芯片堆叠封装的塑封工序,选择低应力膨胀系数a1≤1.0、a2≤3.5、吸水率小于0.15%流动长度90cm~120cm的塑封料,并采用防离层塑封工艺。
本发明的小载体四面扁平无引脚封装的特点是载体缩小,在切割分离前,内引脚向内延伸与载体相连,内引脚与载体相连处有0.10mm的凹坑,凹坑外的引脚长度比普通QFN引脚长1mm,并且载体下部有一圈防溢料槽。
附图说明
图1为本发明切割前的剖视图;
图2为本发明切割后的剖视图;
图3为本发明仰视图。
具体实施方式
下面结合附图对本发明进行详细说明:
本发明包括引线框架载体1,粘片胶2,IC芯片3,芯片3上的焊盘,内引线脚4,键合线5,塑封体6,在切割分离前,所有内引脚4向内延伸与载体1相连,载体1与内引脚4之间设有凹槽7,引线和载体相连处设有切割线10。引线框架载体1上是粘片胶2,粘片胶2为导电胶或绝缘胶,粘片胶2上是IC芯片3,IC芯片3上的焊盘上的键合线5与内引脚4相连,构成了电路的电流和信号通道。塑封料6包围了引线框架载体1、粘片胶2、IC芯片3、IC芯片3上的焊盘与内引脚4连接的键合线5、凹槽7,及内引脚4背面的凹槽9,构成电路整体,对IC芯片3和键合线5起到支撑和保护作用。载体1底部有一圈防溢料凹槽8,防溢料凹槽8接收了流出的溢料,可避免溢料继续向载体1背面扩散。
本发明的生产方法如下:
a、减薄
减薄厚度50μm~200μm,粗糙度Ra 0.10mm~0.05mm;
b、划片
厚度在150μm以上的晶圆同普通QFN划片工艺,厚度在150μm以下晶圆,使用双刀划片机及其工艺;
c、上芯、粘片
粘片材料:选用8200系列、8352系列、84-3J等系列,芯片堆叠上芯采用粘接胶膜片,使使用胶膜片上芯机及其烘烤工艺。
d、压焊
压焊选用ESEC3100和Eagle60键合机,焊线材料选用金线和铜线两种,由于封装厚度0.75,压焊采用低弧度和超低线弧(芯片堆叠)压焊工艺,高低弧正反打线方式,避免交丝和断丝现象,焊线温度控制在180℃~210℃。
e、塑封
塑封设备采用通用QFN自动包封系统,塑封料选用低应力、低吸水率的CEL9220系列环保塑封料,模温165℃~180℃,注塑压力(30~35)Kgf/C m2,使用自动包封系统的多段注塑程序,调整控制塑封过程,防止冲线和芯片表面等分层。后固化使用带螺旋加压装置的专用防翘曲固化夹具。
f、电镀
选用自动电镀线无铅防离层电镀工艺生产,严格控制电流大小(110~130)A和酸洗时间(35~40)S,一般镀层厚度控制在(11.5±3)μm,镀层均匀,无氧化、无残余溢料,符合检验标准,电镀后烘烤同普通QFN。
g、切割
g1、设备,刀具,夹具选择:
切割机选择:DAD3350,清洗机:DCS1440,手工贴膜机QFN双焊点切割夹具。UV照射机UV-956.
g2、切割引线:
先将半成品引线框架的塑封体朝上,引脚朝下贴上UV胶膜,然后把贴好胶的半成品框架引脚朝上,固定在切割机的工作台上,调整夹具角度,校准对正每排左右端两个产品的切割位置,再旋转调整左右两端上下产品切割位置。最后让机器自动快速检测整条产品的切割位置,确定无误后,设定切割速度和切割深度。一般切割速度控制在50μm~70μm/s,每次切割进刀深度控制在0.03mm。切割总深度一般控制在:0.11μm+0.015μm,即切透引脚厚度为准,防止载体和引脚连在一起,造成短路。
g3、分离产品:
在已切割开引脚的产品上,将矩阵式框架封产品按产品设计规格切割成单个电路,经检查UV照射后,放入料盘。
按常规工艺将矩阵式框架封装的单元产品切割成单个产品,机器自动检测合格后放入料盘。
本发明的封装工艺为芯片堆叠封装时:
减薄厚度50μm~100μm;
上芯工序,底层粘片采用膨胀系数80~195PPM/℃、低吸水率<0.15%的导电胶或绝缘胶,上层采用绝缘胶膜片或绝缘胶。
绝缘胶膜片上芯时,使用胶膜片上芯机及其烘烤工艺;堆叠封装的压焊工序,根据焊线直径和芯片焊盘尺寸大小,选择相匹配的柱状劈刀,采用高低弧和低弧反打键合方式。
塑封工序,采用膨胀系数α1≤1、α1≤3.5、吸水率<0.40%、高粘度,流动长度90~120cm的塑封料,采用防离层工艺,后固化采用带螺旋夹紧装置的QFN专用固化夹具固化,防止翘曲。
实施例1
1、减薄、划片
减薄厚度50μm,堆叠封装,粗糙度Ra 0.10mm。
8″晶圆厚度减薄:贴片机用DR3000III/NITI0,
8″减薄机:PG300RM/TSN.测厚仪DH151/TSK;
8″划片机:WD300TXB,贴片用DR3000III/TSK。
采用防离层,防碎片工艺划片。
2.上芯
8″选用AD829或AD889上芯机;
粘片材料采用粘接胶膜片,引线框架选用双排引脚的四面扁平无引脚框架,使用胶膜片烘烤工艺。
3.压焊
选用ESEC3100和Eagle60键合机,焊线材料选用金线,由于封装厚度0.75,压焊采用超低线弧压焊工艺,高低弧正反打线方式,避免交丝和断丝现象,焊线温度180℃。里面一排内引脚采用低弧焊线,外面一排内引脚采用较高弧度焊线。
4.塑封
塑封采用QFN自动包封系统,塑封料选用低应力、低吸水率的CEL9220系列环保塑封料,模温165℃,注塑压力30Kgf/C m2。
后固化时,使用带螺旋加压装置的专用防翘曲固化夹具。
5.电镀
选用自动电镀线无铅防离层电镀工艺,控制电流120A和酸洗时间38S,镀层厚度11.5μm,镀层均匀,无氧化、无残余溢料,符合检验标准,电镀后烘烤同普通QFN。
6、切割
(1)切割引线
切割机选用DAD3350,清洗机选用DCS1440,手工贴膜机选用QFN双焊点切割夹具。UV照射机UV-956。
先将半成品引线框架的塑封体朝上,引脚朝下贴上UV胶膜,然后把贴好胶的半成品框架引脚朝上,固定在切割机的工作台上,调整夹具角度,校准对正每排左右端两个产品的切割位置,再旋转调整左右两端上下产品切割位置。最后让机器自动快速检测整条产品的切割位置,确定无误后,设定切割速度在50μm/s,每次切割进刀深度0.03mm,总切割深度为0.11μm,即切透引脚厚度为准,防止引脚和引脚连在一起,造成短路。
(2)分离产品
在已切割开引脚的产品上,将矩阵式框架封装产品按产品设计规格切割成单个电路,经检查UV照射后,放入料盘。
实施例2
1、减薄、划片
减薄厚度200μm堆叠封装,粗糙度Ra 0.05mm。
12″晶圆厚度减薄:贴片机用DR3000III/NITIO,
12″减薄机:PG300RM/TSN.测厚仪DH151/TSK;
12″划片机:WD300TXB,贴片用DR3000III/TSK,
采用防离层,防碎片工艺划片。
2.上芯
12″选用DB-700FC/巨沛粘片机。
粘片材料:采用绝缘胶膜片,引线框架选用双排引脚的四面扁平无引脚框架,使用胶膜片烘烤工艺。
3.压焊
压焊选用Eagle60键合机,焊线材料选用铜线,压焊采用超低线弧压焊工艺,高低弧正反打线方式,避免交丝和断丝现象,焊线温度210℃,里面一排内引脚采用低弧焊线,外面一排内引脚采用较高弧度焊线。
4.塑封
塑封设备采用通用QFN自动包封系统,塑封料选用低应力、低吸水率的CEL9220系列环保塑封料,模温180℃,注塑压力35Kgf/C m2,并使用自动包封系统的多段注塑程序,调整控制塑封过程,防止冲线和芯片表面等分层。
后固化时,使用带螺旋加压装置的专用防翘曲固化夹具。
5.电镀
选用自动电镀线无铅防离层电镀工艺,电流115A和酸洗时间35S,镀层厚度控制在14.5μm,镀层均匀,无氧化、无残余溢料,符合检验标准,电镀后烘烤同普通QFN。
6、切割
(1)切割引线:
切割机选择:DAD3350,清洗机:DCS1440,手工贴膜机QFN双焊点切割夹具,
UV照射机UV-956。
先将半成品引线框架的塑封体朝上,引脚朝下贴上UV胶膜,然后把贴好胶的半成品框架引脚朝上,固定在切割机的工作台上,调整夹具角度,校准对正每排左右端两个产品的切割位置,再旋转调整左右两端上下产品切割位置。最后让机器自动快速检测整条产品的切割位置,确定无误后,设定切割速度和切割深度。切割速度70μm/s,每次切割进刀深度0.04mm,总切割深度0.12mm,即切透引脚厚度为准。
(2)分离产品
按正常工艺将矩阵式框架封装的单元产品切割成单个产品,机器自动检测合格后放入料盘。
实施例3
1.减薄、划片
根据封装产品厚度确定减薄厚度100μm,粗糙度控制在Ra 0.08mm。
8″晶圆厚度减薄:贴片机用DR3000III/NITIO,
8″减薄机:PG300RM/TSN.测厚仪DH151/TSK;
8″划片机:WD300TXB,贴片用DR3000III/TSK。
采用防离层,防碎片工艺划片。
其它工艺同实施例1。
Claims (8)
1.一种小载体四面扁平无引脚封装件,包括引线框架载体、粘片胶、IC芯片、IC芯片上的焊盘、内引脚、键合线及塑封体,其特征在于在切割分离前,所有内引脚(4)向内延伸与所述引线框架载体(1)相连,载体(1)与内引脚(4)之间设有凹槽(7),内引脚(4)底部设有凹槽(9)。
2.根据权利要求1所述的小载体四面扁平无引脚封装件,其特征在于所述载体(1)背面设有一圈防溢料凹槽(8)。
3.一种生产如权利要求1所述小载体四面扁平无引脚封装件的方法,其特征在于按下述方法和步骤封装:
a、减薄
减薄厚度50μm~200μm,粗糙度Ra 0.10mm~0.05mm;
b、划片
厚度在150μm以上的晶圆同普通QFN划片工艺,厚度在150μm以下晶圆,使用双刀划片机划片;
c、上芯、粘片
d、压焊
e、塑封
f、电镀
g、切割
g1、先从切割线(10)处切开内引线脚(4)和载体(1)间的连接部分,切割深度为0.11μm+0.015μm;
g2、按常规工艺将矩阵式框架封装的单元产品切割成单个产品,机器自动检测合格后放入料盘。
4.根据权利要求3所述的生产方法,其特征在于所述封装工艺为芯片堆叠封装,减薄厚度50μm~100μm。
5.根据权利要求4所述的生产方法,其特征在于所述芯片堆叠封装的上芯工序,底层粘片采用膨胀系数80~195PPM/℃、吸水率<0.15%的导电胶或绝缘胶,上层采用绝缘胶。
6.根据权利要求5所述的生产方法,其特征在于所述绝缘胶膜片上芯使用胶膜片上芯机上芯烘烤。
7.根据权利要求4所述的生产方法,其特征在于所述芯片堆叠封装的压焊工序,根据焊线直径和芯片焊盘尺寸大小,选择相匹配的柱状劈刀,采用高低弧和低弧反打键合方式。
8.根据权利要求4所述的生产方法,其特征在于所述芯片堆叠封装的塑封工序,采用膨胀系数α1≤1、α1≤3.5、吸水率<0.40%、高粘度,流动长度90~120cm的塑封料,采用防离层工艺,后固化采用带螺旋夹紧装置的QFN专用固化夹具固化,防止翘曲。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2009101175093A CN101697348B (zh) | 2009-10-11 | 2009-10-11 | 一种小载体四面扁平无引脚封装件及其制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2009101175093A CN101697348B (zh) | 2009-10-11 | 2009-10-11 | 一种小载体四面扁平无引脚封装件及其制备方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101697348A CN101697348A (zh) | 2010-04-21 |
CN101697348B true CN101697348B (zh) | 2013-06-26 |
Family
ID=42142445
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2009101175093A Active CN101697348B (zh) | 2009-10-11 | 2009-10-11 | 一种小载体四面扁平无引脚封装件及其制备方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101697348B (zh) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8519525B2 (en) | 2010-07-29 | 2013-08-27 | Alpha & Omega Semiconductor, Inc. | Semiconductor encapsulation and method thereof |
CN102403295B (zh) * | 2010-09-07 | 2014-08-06 | 万国半导体股份有限公司 | 金属键接的半导体封装及其方法 |
TWI455269B (zh) | 2011-07-20 | 2014-10-01 | Chipmos Technologies Inc | 晶片封裝結構及其製作方法 |
CN102263081A (zh) * | 2011-07-29 | 2011-11-30 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法 |
CN102263080B (zh) * | 2011-07-29 | 2015-06-17 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚三ic芯片封装件及其生产方法 |
CN102344110B (zh) * | 2011-10-31 | 2015-07-15 | 嘉盛半导体(苏州)有限公司 | 微机电系统器件的方形扁平无引脚封装结构及方法 |
CN102543928A (zh) * | 2011-12-27 | 2012-07-04 | 上海艾为电子技术有限公司 | Qfn封装结构 |
CN102522392B (zh) * | 2011-12-31 | 2014-11-05 | 天水华天科技股份有限公司 | 一种具有接地环的e/LQFP平面封装件及其生产方法 |
CN102522391B (zh) * | 2011-12-31 | 2014-11-05 | 天水华天科技股份有限公司 | 一种具有接地环的e/LQFP堆叠封装件及其生产方法 |
CN102779763A (zh) * | 2012-06-05 | 2012-11-14 | 华天科技(西安)有限公司 | 一种基于腐蚀的aaqfn产品的二次塑封制作工艺 |
CN102738018A (zh) * | 2012-06-13 | 2012-10-17 | 华天科技(西安)有限公司 | 一种基于框架载体开孔和锡球贴膜的aaqfn产品的二次塑封制作工艺 |
CN102738019A (zh) * | 2012-06-13 | 2012-10-17 | 华天科技(西安)有限公司 | 一种基于框架载体开孔和模具贴膜的aaqfn产品的二次塑封制作工艺 |
CN102738010A (zh) * | 2012-06-15 | 2012-10-17 | 华天科技(西安)有限公司 | 一种基于喷砂的aaqfn框架产品扁平封装件制作工艺 |
CN103021884A (zh) * | 2012-12-10 | 2013-04-03 | 华天科技(西安)有限公司 | 一种基于薄型框架的扁平封装件制作工艺 |
CN103021885A (zh) * | 2012-12-10 | 2013-04-03 | 华天科技(西安)有限公司 | 一种基于喷砂的扁平封装件制作工艺 |
TWI480995B (zh) * | 2013-06-21 | 2015-04-11 | 矽品精密工業股份有限公司 | 四方扁平無接腳封裝件及其製法 |
CN103400805A (zh) * | 2013-07-03 | 2013-11-20 | 华天科技(西安)有限公司 | 一种基于框架采用切割刀优化技术的扁平封装件的制作工艺 |
US9601415B2 (en) * | 2014-03-27 | 2017-03-21 | Renesas Electronics Corporation | Method of manufacturing semiconductor device and semiconductor device |
US10204842B2 (en) * | 2017-02-15 | 2019-02-12 | Texas Instruments Incorporated | Semiconductor package with a wire bond mesh |
CN109817785A (zh) * | 2018-12-25 | 2019-05-28 | 广东晶科电子股份有限公司 | 一种发光二极管及其制作方法 |
CN111370384A (zh) * | 2020-05-09 | 2020-07-03 | 天水华洋电子科技股份有限公司 | 抗分层引线框架结构设计 |
CN112331568B (zh) * | 2020-11-04 | 2022-12-23 | 青岛歌尔微电子研究院有限公司 | 芯片防溢胶封装方法 |
CN113192920A (zh) * | 2021-05-21 | 2021-07-30 | 南京矽邦半导体有限公司 | 一种qfn封装的引脚结构 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1905142A (zh) * | 2006-08-01 | 2007-01-31 | 上海凯虹科技电子有限公司 | 新型qfn芯片封装工艺 |
CN101442035A (zh) * | 2008-12-14 | 2009-05-27 | 天水华天科技股份有限公司 | 一种扁平无引线封装件及其生产方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201523004U (zh) * | 2009-10-11 | 2010-07-07 | 天水华天科技股份有限公司 | 一种小载体四面扁平无引脚封装件 |
-
2009
- 2009-10-11 CN CN2009101175093A patent/CN101697348B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1905142A (zh) * | 2006-08-01 | 2007-01-31 | 上海凯虹科技电子有限公司 | 新型qfn芯片封装工艺 |
CN101442035A (zh) * | 2008-12-14 | 2009-05-27 | 天水华天科技股份有限公司 | 一种扁平无引线封装件及其生产方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101697348A (zh) | 2010-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101697348B (zh) | 一种小载体四面扁平无引脚封装件及其制备方法 | |
CN101694837B (zh) | 一种双排引脚的四面扁平无引脚封装件及其生产方法 | |
CN101442035B (zh) | 一种扁平无引线封装件及其生产方法 | |
CN102629604B (zh) | 一种bt基板的悬梁式ic芯片堆叠封装件及其生产方法 | |
CN102222657B (zh) | 多圈排列双ic芯片封装件及其生产方法 | |
CN102437147B (zh) | 密节距小焊盘铜线键合双ic芯片堆叠封装件及其制备方法 | |
CN101562191B (zh) | 带腔体的光电封装件及其生产方法 | |
WO2012068763A1 (zh) | 一种无载体栅格阵列ic芯片封装件及其制备方法 | |
CN102522383B (zh) | 一种中心布线双圈排列ic芯片堆叠封装件及其生产方法 | |
CN102163591B (zh) | 一种球型光栅阵列ic芯片封装件及其生产方法 | |
CN102231372B (zh) | 多圈排列无载体ic芯片封装件及其生产方法 | |
CN102231376B (zh) | 多圈排列无载体双ic芯片封装件及其生产方法 | |
CN102263080B (zh) | 带双凸点的四边扁平无引脚三ic芯片封装件及其生产方法 | |
CN101694838A (zh) | 一种双扁平无引脚封装件及其生产方法 | |
CN102222658B (zh) | 多圈排列ic芯片封装件及其生产方法 | |
CN104091791A (zh) | 一种引线框架的宝塔式ic芯片堆叠封装件及其生产方法 | |
CN102263077A (zh) | 一种双扁平无载体无引脚的ic芯片封装件 | |
CN103094235A (zh) | 一种应用电镀工艺的aaqfn封装件及其制作工艺 | |
CN102543931B (zh) | 一种中心布线双圈排列单ic芯片封装件的制备方法 | |
CN103050451A (zh) | 一种双排引脚四面扁平无引脚封装件及其绝缘处理方法 | |
CN102254893A (zh) | 一种带双凸点的四边扁平无引脚封装件及其生产方法 | |
CN202196776U (zh) | 一种扁平无载体无引线引脚外露封装件 | |
CN102263081A (zh) | 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法 | |
CN106935520A (zh) | 一种内绝缘封装结构及其制造工艺 | |
CN201523005U (zh) | 一种双排引脚的四面扁平无引脚封装件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |