CN101847614A - 一种qfn/dfn无基岛芯片封装结构 - Google Patents
一种qfn/dfn无基岛芯片封装结构 Download PDFInfo
- Publication number
- CN101847614A CN101847614A CN 201010126536 CN201010126536A CN101847614A CN 101847614 A CN101847614 A CN 101847614A CN 201010126536 CN201010126536 CN 201010126536 CN 201010126536 A CN201010126536 A CN 201010126536A CN 101847614 A CN101847614 A CN 101847614A
- Authority
- CN
- China
- Prior art keywords
- lead
- pin
- edge
- crystal grain
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
一种QFN/DFN无基岛芯片封装结构,包括晶粒、导电焊盘、金线以及环氧树脂,所述导电焊盘中间区域设有至少一个中间引脚,该中间引脚位于所述晶粒正下方,与所述晶粒之间涂有绝缘胶层,该中间引脚与位于所述导电焊盘内并延伸到其边缘的导电连茎的一端连接,该导电连茎下部设有下部半腐蚀缺口,导电连茎的另一端与晶粒通过金线连接;所述导电焊盘边缘区域设有至少一个边缘引脚。本发明扩增引脚数量,提高引脚数量和芯片尺寸比例,从而有利于芯片封装结构的缩小和芯片功能的扩展。
Description
技术领域
本发明涉及半导体器件的封装技术领域,特别涉及一种QFN/DFN半导体芯片封装结构[QFN/DFN(Quad Flat No lead)(Dual Flat No lead)]。
背景技术
随着电子产品向小型化方向发展,在手提电脑、CPU电路、微型移动通信电路(手机等)、数字音视频电路、通信整机、数码相机等消费类电子领域的大规模IC和VLSI(超大规模IC)应用电路中,要求半导体芯片的外形做得更小更薄。
现有技术中,QFN(Quad Flat No lead)是一种方形扁平无引脚半导体芯片封装结构,其俯视构造如图1所示,截面剖视构造如图2所示。从这两个视图中可以看出,封装结构是:在芯片封装空间的下部由中央的基岛和围绕基岛布置的导电焊盘构成,基岛上放置晶粒,晶粒上的各导电部分别通过金线与各导电焊盘电连接,其余封装空间填充环氧树脂。DFN(Dual Flat Nolead)是一种矩形扁平无引脚半导体芯片封装结构,其中矩形指的是该芯片在俯视状态下为长方形,其封装结构与QFN相同。一方面,在QFN和DFN的封装结构中都需要基岛来放置晶粒,基岛为引线框的一部分,由金属材料制成,其作用一是在封装中作为晶粒的安置基座,二是具有散热功能,三是可以作为接地端使用,但是由于基岛在俯视状态下的尺寸要大于晶粒的尺寸。另一方面,现有的封装结构引脚分布只能分布在芯片四周,引脚数量和芯片尺寸比例较小,而且受到引脚间距的约束。因此限制了芯片的封装尺寸的缩小和芯片功能的扩展。如何解决这一问题便成为本发明研究的课题。
发明内容
本发明提供一种QFN/DFN无基岛芯片封装结构,其目的是要扩增引脚数量,提高引脚数量和芯片尺寸比例,从而有利于芯片封装结构的缩小和芯片功能的扩展。
为达到上述目的,本发明采用的技术方案是:一种QFN/DFN无基岛芯片封装结构,包括晶粒、导电焊盘、金线以及环氧树脂,所述导电焊盘中间区域设有至少一个中间引脚,其上部设有上部半腐蚀缺口,该中间引脚位于所述晶粒正下方,与所述晶粒之间涂有绝缘胶层,该中间引脚与位于所述导电焊盘内并延伸到其边缘的导电连茎的一端连接,导电连茎的另一端与晶粒通过金线连接,该导电连茎下部设有下部半腐蚀缺口;
所述导电焊盘边缘区域设有至少一个边缘引脚,该边缘引脚与所述晶粒之间涂有绝缘胶层,且通过金线与所述晶粒连接,其余封装空间中填充所述环氧树脂。
上述技术方案中的有关内容解释如下:
上述方案中,所述边缘引脚上部设有上部半腐蚀缺口,该边缘引脚与位于所述导电焊盘内并延伸到其边缘的导电连茎连接,该导电连茎下部设有下部半腐蚀缺口。
由于上述技术方案运用,本发明与现有技术相比具有下列优点:
1、首先,引脚数量与芯片尺寸比例大大增加。
2、其次,同样的芯片尺寸可以有更多的输进点、输入点,增加芯片的功能,可以用更少的芯片达到更多的功能;更有利于在终端产品的小型化,在手提电脑、CPU电路、微型移动通信电路(手机等)、数字音视频电路、通信整机、数码相机等消费类电子领域的大规模IC和VLSI(超大规模IC)应用电路中,大大提高安装精度,减少体积,提高了可靠性。
3、再次,引脚上部设有上部半腐蚀缺口,导电连茎下部设有下部半腐蚀缺口,上部半腐蚀缺口与下部半腐蚀缺口配合能减小芯片的封装体积;而且引脚上部设有上部半腐蚀缺口,可相应的增加引脚底部的面积,从而有利于与PCB焊接。
附图说明
附图1为现有方形扁平无引脚半导体芯片封装结构俯视图;
附图2为现有方形扁平无引脚半导体芯片封装结构截面剖视图;
附图3为本发明无晶粒的透视示意图;
附图4为本发明芯片封装结构的透视示意图;
附图5为本发明芯片封装结构底部示意图;
附图6为附图4芯片封装结构的A-A剖面图;
附图7为附图4芯片封装结构的B-B剖面图。
以上附图中:1、晶粒;2、导电焊盘;3、金线;4、环氧树脂;5、中间引脚;6、绝缘胶层;7、导电连茎;8、下部半腐蚀缺口;9、边缘引脚;10、上部半腐蚀缺口。
具体实施方式
下面结合附图及实施例对本发明作进一步描述:
实施例:一种QFN/DFN无基岛芯片封装结构
一种QFN/DFN无基岛芯片封装结构,参见附图3-7所示,包括晶粒1、导电焊盘2、金线3以及环氧树脂4,其特征在于:所述导电焊盘2中间区域设有至少一个中间引脚5,其上部设有上部半腐蚀缺口10,该中间引脚5位于所述晶粒1正下方,与所述晶粒1之间涂有绝缘胶层6,该中间引脚5与位于所述导电焊盘2内并延伸到其边缘的导电连茎7的一端连接,该导电连茎7的另一端与晶粒1通过金线3连接,该导电连茎7下部设有下部半腐蚀缺口8;
所述导电焊盘2边缘区域设有至少一个边缘引脚9,该边缘引脚9与所述晶粒1之间涂有绝缘胶层6,且通过金线3与所述晶粒1连接,其余封装空间中填充所述环氧树脂4,该边缘引脚9上部设有上部半腐蚀缺口10,该边缘引脚9与位于所述导电焊盘2内并延伸到其边缘的导电连茎7连接,该导电连茎7下部设有下部半腐蚀缺口8。
上述实施例只为说明本发明的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施,并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰,都应涵盖在本发明的保护范围之内。
Claims (2)
1.一种QFN/DFN无基岛芯片封装结构,包括晶粒(1)、导电焊盘(2)、金线(3)以及环氧树脂(4),其特征在于:所述导电焊盘(2)中间区域设有至少一个中间引脚(5),该中间引脚上部设有上部半腐蚀缺口(10),该中间引脚(5)位于所述晶粒(1)正下方,与所述晶粒(1)之间涂有绝缘胶层(6),该中间引脚(5)与位于所述导电焊盘(2)内并延伸到其边缘的导电连茎(7)的一端连接,该导电连茎(7)的另一端与晶粒(1)通过金线(3)连接,该导电连茎(7)下部设有下部半腐蚀缺口(8);
所述导电焊盘(2)边缘区域设有至少一个边缘引脚(9),该边缘引脚(9)与所述晶粒(1)之间涂有绝缘胶层(6),且通过金线(3)与所述晶粒(1)连接,其余封装空间中填充所述环氧树脂(4)。
2.根据权利要求1所述的芯片封装结构,其特征在于:所述边缘引脚(9)上部设有上部半腐蚀缺口(10),该边缘引脚(9)与位于所述导电焊盘(2)内并延伸到其边缘的导电连茎(7)连接,该导电连茎(7)下部设有下部半腐蚀缺口(8)。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 201010126536 CN101847614B (zh) | 2010-03-11 | 2010-03-11 | 一种qfn/dfn无基岛芯片封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 201010126536 CN101847614B (zh) | 2010-03-11 | 2010-03-11 | 一种qfn/dfn无基岛芯片封装结构 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101847614A true CN101847614A (zh) | 2010-09-29 |
CN101847614B CN101847614B (zh) | 2012-10-17 |
Family
ID=42772160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 201010126536 Active CN101847614B (zh) | 2010-03-11 | 2010-03-11 | 一种qfn/dfn无基岛芯片封装结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101847614B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102074541A (zh) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 |
CN102270620A (zh) * | 2011-04-08 | 2011-12-07 | 日月光半导体制造股份有限公司 | 在边缘引脚具有凹槽的半导体封装结构 |
CN104064560A (zh) * | 2014-07-08 | 2014-09-24 | 苏州卓能微电子技术有限公司 | 一种适合于大功率led照明驱动电路应用的多芯片qfn封装 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010027821A (ja) * | 2008-07-18 | 2010-02-04 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
CN201417765Y (zh) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | 无基岛半导体芯片封装结构 |
CN201623156U (zh) * | 2010-03-11 | 2010-11-03 | 苏州固锝电子股份有限公司 | 一种qfn/dfn无基岛芯片封装结构 |
-
2010
- 2010-03-11 CN CN 201010126536 patent/CN101847614B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010027821A (ja) * | 2008-07-18 | 2010-02-04 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
CN201417765Y (zh) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | 无基岛半导体芯片封装结构 |
CN201623156U (zh) * | 2010-03-11 | 2010-11-03 | 苏州固锝电子股份有限公司 | 一种qfn/dfn无基岛芯片封装结构 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102074541A (zh) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 |
WO2012068763A1 (zh) * | 2010-11-26 | 2012-05-31 | 天水华天科技股份有限公司 | 一种无载体栅格阵列ic芯片封装件及其制备方法 |
US9136231B2 (en) | 2010-11-26 | 2015-09-15 | Tianshui Huatian Technology Co., Ltd. | Carrier-free land grid array IC chip package and preparation method thereof |
CN102270620A (zh) * | 2011-04-08 | 2011-12-07 | 日月光半导体制造股份有限公司 | 在边缘引脚具有凹槽的半导体封装结构 |
CN104064560A (zh) * | 2014-07-08 | 2014-09-24 | 苏州卓能微电子技术有限公司 | 一种适合于大功率led照明驱动电路应用的多芯片qfn封装 |
Also Published As
Publication number | Publication date |
---|---|
CN101847614B (zh) | 2012-10-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101506975B (zh) | 堆叠管芯封装 | |
US8138024B2 (en) | Package system for shielding semiconductor dies from electromagnetic interference | |
CN102280418B (zh) | 带有散热装置的半导体封装 | |
KR101563911B1 (ko) | 반도체 패키지 | |
CN201417765Y (zh) | 无基岛半导体芯片封装结构 | |
US20090156001A1 (en) | Structure for reducing stress for vias and fabricating method thereof | |
CN201623156U (zh) | 一种qfn/dfn无基岛芯片封装结构 | |
US9123629B2 (en) | Chip package and method for forming the same | |
CN101847614B (zh) | 一种qfn/dfn无基岛芯片封装结构 | |
CN101339929B (zh) | 半导体元件、超薄晶粒封装体与半导体晶粒封装体 | |
CN104282634A (zh) | 半导体装置 | |
KR101737053B1 (ko) | 반도체 패키지 | |
US8853834B2 (en) | Leadframe-type semiconductor package having EMI shielding layer connected to ground | |
US9659880B2 (en) | Semiconductor device | |
US8587100B2 (en) | Lead frame and semiconductor package using the same | |
CN103354228A (zh) | 半导体封装件及其制造方法 | |
CN205122576U (zh) | 用于无引脚封装结构的引线框架及封装结构 | |
CN204577415U (zh) | 生物识别模组 | |
CN201829483U (zh) | 倒装薄的四边无引线封装的引线框及其封装结构 | |
US10153221B1 (en) | Face down dual sided chip scale memory package | |
US7504714B2 (en) | Chip package with asymmetric molding | |
TWI466262B (zh) | 電磁干擾遮蔽層連接至接地訊號之導線架型半導體封裝構造 | |
CN203932043U (zh) | 一种贴片封装的功率器件 | |
US20050179119A1 (en) | Miniaturized chip scale package structure | |
CN202384314U (zh) | 小尺寸半导体封装结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |