CN104103603B - 半导体装置以及半导体模块 - Google Patents

半导体装置以及半导体模块 Download PDF

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CN104103603B
CN104103603B CN201410131059.4A CN201410131059A CN104103603B CN 104103603 B CN104103603 B CN 104103603B CN 201410131059 A CN201410131059 A CN 201410131059A CN 104103603 B CN104103603 B CN 104103603B
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semiconductor
chip
semiconductor device
chip carrier
semiconductor chip
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CN104103603A (zh
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米山玲
冈部浩之
西田信也
小原太
小原太一
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Mitsubishi Electric Corp
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Abstract

本发明的目的是提供一种使芯片座和半导体芯片的剥离得到抑制的半导体装置。本实施方式中的半导体装置(100)的特征在于,具有:引线框,其具有芯片座(1)和电极端子(5);以及半导体芯片(3),其粘接在芯片座(1)的表面,半导体芯片(3)和除了底面之外的引线框由封装树脂(4)封装,在芯片座(1)的表面和半导体芯片(3)之间的粘接界面上形成有凹凸。

Description

半导体装置以及半导体模块
技术领域
本发明涉及一种半导体装置以及半导体模块,特别地,涉及一
种树脂封装后的半导体装置。
背景技术
作为半导体芯片用的封装件,已知QFN(quad flat no-leads)及SON(smalloutline no-leads)等无引脚型的封装件。在通常的无引脚型的封装件中,在引线框的芯片座上通过芯片接合树脂而粘接有半导体芯片。半导体芯片的端子和引线框的电极端子,通过导线接合而连接。引线框、半导体芯片以及导线通过传递模塑法,使用模塑树脂(封装树脂)进行封装。在封装件下表面,芯片座以及电极端子露出。
在具有上述结构的半导体封装件中,如果由于外部环境的温度变化及半导体芯片自身的温度变化而反复进行发热、冷却的温度循环,则存在芯片接合树脂从芯片座或者半导体芯片剥离,从而使芯片座和半导体芯片剥离的情况。另外,有时由于芯片座和半导体芯片剥离而在模塑树脂上产生裂缝。如果产生剥离、裂缝,则半导体封装件的可靠性降低、寿命降低。
上述的剥离及裂缝由于在半导体芯片、引线框、芯片接合树脂、模塑树脂之间线膨胀系数不同而产生。例如,在半导体芯片由硅形成,引线框由铜形成的情况下,与半导体芯片的线膨胀系数相比,引线框的线膨胀系数较大。在此情况下,在常温下,半导体封装件的形状是扁平的,但在低温时,由于热应力而产生向上凸出的翘曲。另外,在高温时,由于热应力而产生向下凸出的翘曲。由于这种翘曲而产生上述的剥离、裂缝。
如果剥离、裂缝到达封装件外部,则可能引起耐湿性、绝缘性的降低,半导体封装件的可靠性以及寿命降低。另外,如果在半导体芯片的下方产生剥离、裂缝,则引起半导体芯片的散热性的降低、电连接的劣化,半导体封装件的可靠性以及寿命降低。
例如,在专利文献1中,通过在芯片座和模塑树脂(树脂封装体)之间的界面上设置凹凸形状,从而抑制模塑树脂从芯片座剥离。
专利文献1:日本特开平6-85132号公报
如上所述,存在下述问题,即,由于在半导体封装件内部产生的剥离、裂缝,而引起半导体封装件的可靠性降低以及寿命降低。另外,上述专利文献1所记载的技术是抑制芯片座和模塑树脂的剥离的技术,无法抑制芯片座和半导体芯片的剥离。
发明内容
本发明就是为了解决上述课题而提出的,其目的是提供一种使芯片座和半导体芯片的剥离得到抑制的半导体装置以及具有该半导体装置的半导体模块。
本发明所涉及的半导体装置的特征在于,具有:引线框,其具有芯片座和电极端子;以及半导体芯片,其粘接在芯片座表面,半导体芯片和除了底面之外的引线框由封装树脂封装,在芯片座表面和半导体芯片之间的粘接界面上形成有凹凸。
另外,本发明所涉及的半导体装置的特征在于,具有:引线框,其具有芯片座和电极端子;以及半导体芯片,其粘接在芯片座表面,半导体芯片和除了底面之外的引线框由封装树脂封装,芯片座和上述半导体芯片局部地粘接。
另外,本发明所涉及的半导体模块具有半导体装置和功率半导体芯片。
发明的效果
根据本发明,通过在芯片座和半导体芯片之间的粘接界面上形成凹凸,从而使粘接界面的面积增大,使粘接更牢固,因此,即使在芯片座和半导体芯片之间的粘接界面上产生热应力,粘接界面也难以剥离。因此,能够提高半导体装置的可靠性以及寿命。
另外,根据本发明,通过使芯片座和半导体芯片局部地粘接,从而粘接界面的面积减小,因此,由于芯片座和半导体芯片之间的线膨胀系数的差产生的翘曲减轻。由于翘曲减轻,所以可以抑制芯片接合树脂的剥离及在封装树脂上产生的裂缝等。因此,可以提高半导体装置的可靠性以及寿命。
附图说明
图1是实施方式1所涉及的半导体装置的剖面图。
图2是实施方式2所涉及的半导体装置的剖面图。
图3是实施方式3所涉及的半导体装置的剖面图。
图4是实施方式4所涉及的半导体装置的剖面图。
图5是实施方式5所涉及的半导体装置的剖面图。
图6是实施方式6所涉及的半导体装置的剖面图。
图7是实施方式7所涉及的半导体装置的剖面图。
图8是实施方式8所涉及的半导体装置的剖面图。
图9是实施方式9所涉及的半导体装置的剖面图。
标号的说明
1芯片座,1a凹凸部,1b凸起,1c凹部,2芯片接合树脂,3半导体芯片,3a凹凸部,4封装树脂,5电极端子,6导线,24功率半导体芯片,100、200、300、400、500、600、700、800半导体装置,900半导体模块。
具体实施方式
<实施方式1>
<结构>
在图1中示出本实施方式中的半导体装置100的剖面图。半导体装置100是QFN或SON等无引脚型的封装件。引线框由芯片座1和电极端子5构成。在芯片座1上,经由芯片接合树脂2而粘接有半导体芯片3。
半导体芯片3上表面的各端子(未图示),经由导线6与电极端子5连接。引线框、半导体芯片3、导线6由封装树脂4封装。此外,引线框的底面没有被封装,而是露出在外部。在半导体装置100中,在芯片座1和半导体芯片3之间的粘接界面上形成有凹凸。更具体地说,粘接界面的凹凸是通过在芯片座1的表面形成凹凸部1a而形成的。
关于在芯片座1的表面形成凹凸部1a的方法,使用冲压(punch)加工或激光加工等机械方法、或蚀刻等化学方法。
此外,作为半导体芯片3,也可以使用SiC或GaN等宽带隙半导体。通常,与硅制的半导体芯片相比,由SiC或GaN等形成的半导体芯片能够在高温下动作,但由此,由于使用温度环境及自身发热引起的温度循环的幅度变大,由热应力增大引起的剥离及裂缝等成为问题。在本实施方式中,通过在粘接界面上形成凹凸,从而使半导体芯片3和芯片座1之间的粘接更牢固,因此,可以抑制由热应力增大引起的剥离及裂缝等。
另外,在本实施方式中,也可以将半导体芯片3的厚度设为比芯片座1的厚度小。半导体芯片3与其他结构部件(引线框、封装树脂4、芯片接合树脂2)相比,线膨胀系数小。引线框由铜等线膨胀系数较大的金属构成,所以在半导体芯片3的厚度比芯片座1的厚度大的情况下,结构部件之间的膨胀的差值变大,由热应力引起的变形(翘曲)变大。另一方面,如果将半导体芯片3的厚度设为比芯片座1的厚度小,则结构部件间的膨胀的差值变小,因此,能够减小由热应力引起的变形。通过减小由热应力引起的变形,从而可以抑制剥离和裂缝的产生等。
另外,在本实施方式中,如果封装树脂4的厚度较薄,则封装件自身的刚性变低,翘曲变形量变大。另一方面,通过将封装树脂4设得较厚,即在图1中将封装树脂4的高度设得较高,从而使封装件自身的刚性变高,因此,可以抑制由热应力引起的翘曲。因此,可以抑制剥离和裂缝的产生。
<效果>
本实施方式中的半导体装置100的特征在于,具有:引线框,其具有芯片座1和电极端子5;以及半导体芯片3,其粘接在芯片座1的表面,半导体芯片3和除了底面之外的引线框由封装树脂4封装,在芯片座1的表面和半导体芯片3之间的粘接界面上形成有凹凸。
因此,通过在芯片座1和半导体芯片3之间的粘接界面上形成凹凸,从而使粘接界面的面积增大,使芯片接合树脂2的粘接更牢固,因此,即使在芯片座1和半导体芯片3之间的粘接界面产生热应力,粘接界面也难以剥离。因此,可以提高半导体装置100的可靠性以及寿命。
另外,在本实施方式的半导体装置100中,其特征在于,通过在芯片座1的表面形成凹凸部1a,从而形成有粘接界面的凹凸。
因此,通过在芯片座1的表面形成凹凸部1a,从而使芯片座1的表面和芯片接合树脂2之间的粘接界面的面积增大,因此,芯片接合树脂2难以从芯片座1剥离。因此,可以提高半导体装置100的可靠性以及寿命。
另外,在本实施方式的半导体装置100中,其特征在于,与芯片座1的厚度相比,半导体芯片3的厚度较小。
因此,通过使半导体芯片3的厚度减小而使体积减小,因此,能够降低芯片座1和半导体芯片3之间的粘接的热应力。因此,可以抑制产生粘接界面的剥离及封装树脂4的裂缝。
另外,在本实施方式的半导体装置100中,其特征在于,半导体芯片3包含宽带隙半导体。
因此,即使在将半导体芯片3设为在高温下动作的宽带隙半导体的情况下,由于粘接界面的凹凸形状而使芯片接合树脂2的粘接变得更牢固,因此,可以抑制由热应力引起的剥离等。
<实施方式2>
在图2中示出本实施方式的半导体装置200的剖面图。在半导体装置200中,在芯片座1和半导体芯片3之间的由芯片接合树脂2形成的粘接界面上形成有凹凸。更具体地说,粘接界面的凹凸是通过在半导体芯片3的下表面形成凹凸部3a而形成的。
关于在半导体芯片3下表面形成凹凸部3a的方法,使用激光加工等机械方法或蚀刻等化学方法。此外,如果在半导体晶圆工艺的背面处理工序中形成该凹凸部3a,则可以抑制工序数量的增加。
<效果>
在本实施方式的半导体装置200中,其特征在于,通过在半导体芯片3上形成凹凸部3a,从而形成有粘接界面的凹凸。
因此,通过在半导体芯片3上形成凹凸部3a,从而使半导体芯片3底面和芯片接合树脂2之间的粘接界面的面积增大,因此,芯片接合树脂2难以从半导体芯片3剥离。因此,可以提高半导体装置100的可靠性以及寿命。
<实施方式3>
在图3中示出本实施方式的半导体装置300的剖面图。在半导体装置300中,芯片座1和半导体芯片3通过芯片接合树脂2而局部地粘接。其他结构与实施方式1相同,因此,省略说明。
此外,与实施方式1相同地,作为半导体芯片3,也可以使用SiC、GaN等宽带隙半导体。
另外,在本实施方式中,与实施方式1相同地,也可以将半导体芯片3的厚度设为比芯片座1的厚度小。如果减小半导体芯片3的厚度,则结构部件间的膨胀的差值变小,因此,可以减小由热应力引起的变形。
另外,在本实施方式中,与实施方式1相同地,也可以将封装树脂4设计得较厚。通过将封装树脂4增厚,从而使封装件自身的刚性变高,因此,可以抑制由热应力引起的翘曲。因此,可以抑制剥离、裂缝的产生。
<效果>
本实施方式的半导体装置300的特征在于,具有:引线框,其具有芯片座1和电极端子5;以及半导体芯片3,其粘接在芯片座1表面,半导体芯片3和除了底面之外的引线框由封装树脂4封装,芯片座1和半导体芯片3局部地粘接。
因此,通过将芯片座1和半导体芯片3局部地粘接,从而使粘接界面的面积减小,因此,因芯片座1和半导体芯片3之间的线膨胀系数之差而产生的翘曲减轻。由于翘曲减轻,所以可以抑制芯片接合树脂2的剥离及在封装树脂4上产生的裂缝等。因此,可以提高半导体装置300的可靠性以及寿命。所谓可靠性,是特别地针对耐湿性而言的,所谓寿命,是特别地针对温度循环而言的。
<实施方式4>
<结构>
在图4(a)、(b)分别示出本实施方式的半导体装置400的剖面图和俯视图。在本实施方式的半导体装置400中,相对于实施方式1中的半导体装置100(图1),进一步在芯片座1的表面形成有俯视观察时包围半导体芯片3的凸起1b。其他结构与实施方式1(图1)相同,因此,省略说明。
在芯片座1的表面形成的凸起1b,例如是通过进行冲压加工使芯片座1局部地隆起等机械加工而形成的。
另外,芯片座1和凸起1b也可以由不同部件构成。即,也可以单独准备对半导体芯片3的周围进行包围的形状的部件,安装在芯片座1的表面。
此外,芯片座1和半导体芯片3之间的粘接界面,也可以按照实施方式2(即,图2的半导体装置200)或者实施方式3(即,图3的半导体装置300)的方式构成。
<效果>
在本实施方式的半导体装置400中,其特征在于,在芯片座1的表面形成有俯视观察时包围半导体芯片3的凸起1b。
因此,即使在芯片座1和半导体芯片之间的粘接界面中产生剥离、裂缝,也能够通过凸起1b而抑制其发展。由此,可以对剥离、裂缝到达封装件外部这一情况进行抑制,因此,可以提高半导体装置400的可靠性以及寿命。
另外,在本实施方式的半导体装置400中,其特征在于,凸起1b和芯片座1由不同的部件形成。
因此,通过将凸起1b和芯片座1设为不同的部件,从而不需要冲压加工等机械加工,可以在期望的位置设置期望形状的凸起1b。
<实施方式5>
在图5(a)、(b)分别示出本实施方式的半导体装置500的剖面图和俯视图。在本实施方式的半导体装置500中,与实施方式4(图4(a)、(b))相同地,在芯片座1的表面形成有俯视观察时包围半导体芯片3的凸起1b。凸起1b通过导线接合而形成。其他结构与实施方式4(图4(a)、(b))相同,因此,省略说明。
如果将在芯片座1的表面形成的凸起1b的原材料设为金丝(gold wire),则能够在通过导线接合而安装导线6的工序中同时形成凸起1b。因此,无需增加工序数量就能够设置凸起1b。
另外,也可以使用比金丝粗的铝线形成凸起1b。通过将凸起1b设为铝线,从而可以将凸起1b的高度设得更高。
<效果>
在本实施方式的半导体装置500中,其特征在于,凸起1b由经过导线接合而设置的导线形成。
因此,即使通过导线接合而形成凸起1b,也可以得到与实施方式4所述的效果相同的效果。另外,如果在通过导线接合安装导线6的工序中同时形成凸起1b,则无需增加工序数量就能够形成凸起1b。
另外,在本实施方式的半导体装置500中,凸起1b是经过导线接合而设置的铝线。
因此,通过由铝线形成凸起1b,从而与由金丝形成凸起1b的情况相比,可以使导线更粗。因此,可以使凸起1b的高度更高,因此,可以进一步对剥离、裂缝到达封装件外部这一情况进行抑制。
<实施方式6>
在图6中示出本实施方式的半导体装置600的剖面图。在本实施方式的半导体装置600中,与实施方式4(图4(a)、(b))相同地,在芯片座1的表面形成有俯视观察时包围半导体芯片3的凸起1b。凸起1b是通过对芯片座1的表面进行切削而形成的。其他结构与实施方式4(图4(a)、(b))相同,因此,省略说明。
凸起1b是通过蚀刻等化学处理或冲压加工、激光加工等机械处理,将芯片座1的表面的除了凸起1b以外的部分削去而形成的。另外,通过对芯片座1的表面进行切削,从而使芯片座1的厚度变薄,因此,降低在半导体芯片3和芯片座1之间产生的热应力。
<效果>
在本实施方式的半导体装置600中,其特征在于,凸起1b是通过对芯片座1的表面进行切削而形成的。
因此,通过形成凸起1b,从而可以得到与实施方式4中所述的效果相同的效果。另外,通过对芯片座1的表面进行切削而形成凸起1b,使芯片座1的厚度减小与凸起1b的高度相当的量,因此使得在半导体芯片3和芯片座1之间产生的热应力减小。由此,可以抑制芯片接合树脂2的剥离、在封装树脂4上产生的裂缝等。
<实施方式7>
<结构>
在图7中示出本实施方式的半导体装置700的剖面图。在本实施方式的半导体装置700中,相对于实施方式1的半导体装置100(图1),进一步在芯片座1的底面形成凹部1c。其他结构与实施方式1(图1)相同,因此,省略说明。
凹部1c形成为,在俯视观察时至少一部分与半导体芯片3重合。即,凹部1c位于半导体芯片3和芯片座1之间的粘接界面的下方。通过形成凹部1c,从而在粘接界面的下方减小芯片座1的体积,因此,能够降低在半导体芯片3和芯片座1之间产生的热应力。此外,在凹部1c中填充封装树脂4。
此外,在本实施方式中,与实施方式1相同地,作为半导体芯片3,也可以使用SiC、GaN等宽带隙半导体。
另外,在本实施方式中,与实施方式1相同地,也可以将半导体芯片3的厚度设为比芯片座1的厚度小。如果减小半导体芯片3的厚度,则结构部件间的膨胀的差值变小,因此,能够减小由热应力引起的变形。
另外,在本实施方式中,与实施方式1相同地,也可以将封装树脂4设计得较厚。通过使封装树脂4变厚,从而使封装件自身的刚性变高,因此,可以抑制由热应力引起的翘曲。由此,可以抑制剥离、裂缝的产生。
<效果>
在本实施方式的半导体装置700中,其特征在于,在芯片座的底面形成有凹部1c,凹部1c的至少一部分在俯视观察时与半导体芯片3重合。
因此,在半导体芯片3和芯片座1的粘接界面的下方,芯片座1的体积减小,因此,在半导体芯片3和芯片座1之间产生的热应力降低。由于热应力的降低,所以可以抑制芯片接合树脂2的剥离及在封装树脂4上产生的裂缝等。因此,可以提高半导体装置700的可靠性以及寿命。所谓可靠性,是特别地针对耐湿性而言的,所谓寿命,是特别地针对温度循环而言的。
<实施方式8>
<结构>
在图8中示出本实施方式的半导体装置800的剖面图。本实施方式的半导体装置800具有多个半导体芯片3。另外,引线框具有多个芯片座1。半导体芯片3和芯片座1分别与实施方式1(图1)相同地,使用芯片接合树脂2进行粘接。其他结构与实施方式1相同,因此,省略说明。
在将多个半导体芯片接近地配置的情况下,存在下述问题,即,在高温下动作的半导体芯片由于热应力而产生翘曲的情况下,该半导体芯片周围的半导体芯片3等也受到由翘曲引起的变形的影响。特别地,在将硅制的半导体芯片3和SiC、GaN等能够在高温下动作的半导体芯片3接近地配置的情况下,上述问题尤为显著。
在本实施方式中,与实施方式1相同地,半导体芯片3和芯片座1更牢固地粘接,因此,即使在高温下动作的半导体芯片3和芯片座1之间产生热应力,也可以抑制剥离、裂缝的产生。另外,即使在与高温下动作的半导体芯片3接近的其他半导体芯片3和芯片座1之间产生翘曲,由于该半导体芯片3和芯片座1之间被牢固地粘接,所以可以抑制剥离、裂缝的产生。
此外,在本实施方式中,即使将芯片座1和半导体芯片3之间的粘接界面按照实施方式2(图2)的方式构成,也可以得到相同的效果。
另外,如果将芯片座1和半导体芯片3之间的粘接界面按照实施方式3(图3)的方式构成,则能够降低热应力自身,因此,能够抑制翘曲,能够将在高温下动作的半导体芯片3和在较低温度下动作的半导体芯片3接近地配置。
另外,也可以如实施方式4~6(图4~6)所示,以包围各半导体芯片3的方式,在芯片座1的表面形成凸起1b。另外,也可以如实施方式7(图7)所示,在芯片座1的底面设置凹部1c。
<效果>
在本实施方式的半导体装置800中,其特征在于,半导体芯片3为多个。由此,由于能够在各半导体芯片3中抑制剥离、裂缝等的产生,因此,即使将多个半导体芯片3相邻地配置,也可以维持可靠性。因此,能够将动作温度不同的半导体芯片接近地配置,提高设计的自由度。
<实施方式9>
<结构>
在图9中示出本实施方式的半导体模块900的剖面图。半导体模块900具有实施方式1中的半导体装置100以及功率半导体芯片24。半导体装置100的电极端子5,经由焊料11与控制基板13的焊盘(land)12连接。
控制基板13与中继端子14连接。另外,在控制基板13上,经由端子固定部件16而连接有外部端子15。中继端子14被埋入至半导体模块的壳体17中。
壳体17固定在基座板18上,在基座板18的上方经由焊料19配置绝缘基板21,该绝缘基板21双面形成有配线图案20、22。功率半导体芯片24经由焊料23与配线图案22连接。功率半导体芯片24、配线图案22、中继端子14、外部端子26通过导线25而适当连接。功率半导体芯片24、导线25、绝缘基板21由硅凝胶27封装。另外,壳体17的内部由盖部28密闭。
在本实施方式中,作为功率半导体芯片24,也可以使用SiC、GaN等宽带隙半导体。以SiC、GaN等宽带隙半导体为材料的半导体芯片,与硅制的半导体芯片相比能够在高温下动作,因此,由使用环境温度及自身发热引起的温度循环的幅度变大。半导体装置100能够如实施方式1中所述,抑制由热应力引起的剥离、裂缝,因此,也能够搭载于在这种温度环境下动作的半导体模块900上。
此外,也可以取代半导体装置100,而搭载半导体装置200、300、400、500、600、700、800。
<效果>
本实施方式中的半导体模块900具有半导体装置100以及功率半导体芯片24。
因此,如实施方式1中所述,半导体装置100具有能够抑制由热应力引起的剥离、裂缝的结构,因此,即使在由于功率半导体芯片24的发热而变为高温的半导体模块900内搭载有半导体装置100的情况下,也可以维持可靠性。另外,由于能够搭载无引脚型的半导体装置100,所以能够实现半导体模块900的小型化。
另外,在本实施方式的半导体模块900中,其特征在于,功率半导体芯片24包含宽带隙半导体。
因此,如果将功率半导体芯片24设为SiC、GaN等宽带隙半导体,则半导体模块900有时会在动作时温度变得更高,但由于半导体装置100具有能够抑制由热应力引起的剥离、裂缝的结构,所以也能够搭载在这种半导体模块900中。
此外,本发明可以在本发明的范围内将各实施方式自由地组合,或对各实施方式适当地进行变形、省略。

Claims (24)

1.一种半导体模块,其特征在于,具有:
半导体装置;以及
功率半导体芯片,
所述半导体装置和所述功率半导体芯片配置在相同的壳体内,
所述半导体装置具有:
引线框,其具有芯片座和电极端子;以及
半导体芯片,其粘接在所述芯片座的表面,
所述半导体芯片和除了底面之外的所述引线框,由封装树脂封装,
在所述芯片座的表面和所述半导体芯片之间的粘接界面上,形成有凹凸,
在所述芯片座的底面形成有凹部,
所述凹部的至少一部分在俯视观察时与所述半导体芯片重合。
2.根据权利要求1所述的半导体模块,其特征在于,
通过在所述芯片座的表面形成凹凸部,从而形成有所述粘接界面的凹凸。
3.根据权利要求1所述的半导体模块,其特征在于,
通过在所述半导体芯片上形成凹凸部,从而形成有所述粘接界面的凹凸。
4.根据权利要求1至3中任一项所述的半导体模块,其特征在于,
在所述芯片座的表面形成有俯视观察时包围所述半导体芯片的凸起。
5.根据权利要求4所述的半导体模块,其特征在于,
所述凸起和所述芯片座由不同部件形成。
6.根据权利要求4所述的半导体模块,其特征在于,
所述凸起由经过导线接合而设置的导线形成。
7.根据权利要求6所述的半导体模块,其特征在于,
所述凸起是经过导线接合而设置的铝线。
8.根据权利要求4所述的半导体模块,其特征在于,
所述凸起是通过对所述芯片座的表面进行切削而形成的。
9.根据权利要求1至3中任一项所述的半导体模块,其特征在于,
所述半导体芯片的厚度比所述芯片座的厚度小。
10.根据权利要求1至3中任一项所述的半导体模块,其特征在于,
所述半导体芯片包含宽带隙半导体。
11.根据权利要求1至3中任一项所述的半导体模块,其特征在于,
所述半导体芯片为多个。
12.根据权利要求1所述的半导体模块,其特征在于,
所述功率半导体芯片包含宽带隙半导体。
13.一种半导体装置,其特征在于,具有:
引线框,其具有芯片座和电极端子;以及
半导体芯片,其粘接在所述芯片座的表面,
所述半导体芯片和除了底面之外的所述引线框,由封装树脂封装,
所述半导体芯片相对于单个所述芯片座在多处局部地粘接。
14.根据权利要求13所述的半导体装置,其特征在于,
在所述芯片座的表面形成有俯视观察时包围所述半导体芯片的凸起。
15.根据权利要求14所述的半导体装置,其特征在于,
所述凸起和所述芯片座由不同部件形成。
16.根据权利要求14所述的半导体装置,其特征在于,
所述凸起由经过导线接合而设置的导线形成。
17.根据权利要求16所述的半导体装置,其特征在于,
所述凸起是经过导线接合而设置的铝线。
18.根据权利要求14所述的半导体装置,其特征在于,
所述凸起是通过对所述芯片座的表面进行切削而形成的。
19.根据权利要求13至18中任一项所述的半导体装置,其特征在于,
在所述芯片座的底面形成有凹部,
所述凹部的至少一部分在俯视观察时与所述半导体芯片重合。
20.根据权利要求13至18中任一项所述的半导体装置,其特征在于,
所述半导体芯片的厚度比所述芯片座的厚度小。
21.根据权利要求13至18中任一项所述的半导体装置,其特征在于,
所述半导体芯片包含宽带隙半导体。
22.根据权利要求13至18中任一项所述的半导体装置,其特征在于,
所述半导体芯片为多个。
23.一种半导体模块,其具有:
权利要求13至18中任一项所述的半导体装置;以及
功率半导体芯片。
24.根据权利要求23所述的半导体模块,其特征在于,
所述功率半导体芯片包含宽带隙半导体。
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8956920B2 (en) * 2012-06-01 2015-02-17 Nxp B.V. Leadframe for integrated circuit die packaging in a molded package and a method for preparing such a leadframe
US20160071787A1 (en) * 2014-09-08 2016-03-10 Sheila F. Chopin Semiconductor device attached to an exposed pad
US10184744B2 (en) 2014-10-08 2019-01-22 Smith & Wesson Corp. Quick connect for pistol suppressor
JP6560496B2 (ja) * 2015-01-26 2019-08-14 株式会社ジェイデバイス 半導体装置
US10541229B2 (en) * 2015-02-19 2020-01-21 Micron Technology, Inc. Apparatuses and methods for semiconductor die heat dissipation
CN107533984B (zh) * 2015-07-01 2020-07-10 三菱电机株式会社 半导体装置以及半导体装置的制造方法
US11037904B2 (en) 2015-11-24 2021-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Singulation and bonding methods and structures formed thereby
DE102016105781A1 (de) * 2016-03-30 2017-10-19 Infineon Technologies Ag Ein Leadframe, eine Elektronikkomponente und ein Verfahren zum Ausbilden der Elektronikkomponente
WO2018026592A1 (en) * 2016-08-03 2018-02-08 Soliduv, Inc. Strain-tolerant die attach with improved thermal conductivity, and method of fabrication
JP2018137287A (ja) * 2017-02-20 2018-08-30 株式会社村田製作所 化合物半導体基板及び電力増幅モジュール
US10586716B2 (en) 2017-06-09 2020-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor device package
DE102017117668B3 (de) * 2017-08-03 2018-09-27 Semikron Elektronik Gmbh & Co. Kg Leistungselektronische Anordnung mit einer Haftschicht sowie Verfahren zur Herstellung dieser Anordnung
US20190221502A1 (en) * 2018-01-17 2019-07-18 Microchip Technology Incorporated Down Bond in Semiconductor Devices
JP7056226B2 (ja) 2018-02-27 2022-04-19 Tdk株式会社 回路モジュール
US11177192B2 (en) * 2018-09-27 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including heat dissipation structure and fabricating method of the same
DE112020001452T5 (de) * 2019-03-26 2021-12-02 Rohm Co., Ltd. Elektronikbauteil und verfahren zum herstellen eines elektronikbauteils
CN110745772B (zh) * 2019-10-21 2023-10-20 重庆大学 一种mems应力隔离封装结构及其制造方法
CN115516611A (zh) 2020-05-18 2022-12-23 三菱电机株式会社 半导体装置及其制造方法以及电力转换装置
JP2022046334A (ja) 2020-09-10 2022-03-23 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
US11824037B2 (en) 2020-12-31 2023-11-21 International Business Machines Corporation Assembly of a chip to a substrate
US11545444B2 (en) 2020-12-31 2023-01-03 International Business Machines Corporation Mitigating cooldown peeling stress during chip package assembly
US20230047555A1 (en) * 2021-08-12 2023-02-16 Texas Instruments Incorporated Semiconductor devices and processes
JP2023045874A (ja) * 2021-09-22 2023-04-03 株式会社東芝 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184064B1 (en) * 2000-01-12 2001-02-06 Micron Technology, Inc. Semiconductor die back side surface and method of fabrication
CN101030570A (zh) * 2006-03-03 2007-09-05 三菱电机株式会社 半导体装置
CN101393900A (zh) * 2007-09-20 2009-03-25 株式会社瑞萨科技 半导体器件及其制造方法

Family Cites Families (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02127092A (ja) * 1988-11-08 1990-05-15 Hitachi Maxell Ltd Icカードモジユール
JPH02144954A (ja) * 1988-11-28 1990-06-04 Matsushita Electron Corp 半導体装置
US5164815A (en) * 1989-12-22 1992-11-17 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount
JPH04312933A (ja) * 1991-03-29 1992-11-04 Mitsubishi Electric Corp 半導体装置
JPH0547988A (ja) 1991-08-21 1993-02-26 Sony Corp 半導体装置
JPH0685132A (ja) 1992-09-07 1994-03-25 Mitsubishi Electric Corp 半導体装置
JPH06209054A (ja) * 1993-01-08 1994-07-26 Mitsubishi Electric Corp 半導体装置
US5554569A (en) * 1994-06-06 1996-09-10 Motorola, Inc. Method and apparatus for improving interfacial adhesion between a polymer and a metal
JPH113953A (ja) * 1997-06-10 1999-01-06 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
US5969461A (en) * 1998-04-08 1999-10-19 Cts Corporation Surface acoustic wave device package and method
JP3562311B2 (ja) 1998-05-27 2004-09-08 松下電器産業株式会社 リードフレームおよび樹脂封止型半導体装置の製造方法
JP2000031345A (ja) 1998-07-13 2000-01-28 Ricoh Co Ltd 半導体装置
SG92624A1 (en) * 1999-02-09 2002-11-19 Inst Of Microelectronics Lead frame for an integrated circuit chip (integrated circuit peripheral support)
US6256200B1 (en) * 1999-05-27 2001-07-03 Allen K. Lam Symmetrical package for semiconductor die
KR100335480B1 (ko) 1999-08-24 2002-05-04 김덕중 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지
JP3062192B1 (ja) * 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
JP3420153B2 (ja) 2000-01-24 2003-06-23 Necエレクトロニクス株式会社 半導体装置及びその製造方法
US6306684B1 (en) * 2000-03-16 2001-10-23 Microchip Technology Incorporated Stress reducing lead-frame for plastic encapsulation
JP2002110888A (ja) * 2000-09-27 2002-04-12 Rohm Co Ltd アイランド露出型半導体装置
US6762118B2 (en) * 2000-10-10 2004-07-13 Walsin Advanced Electronics Ltd. Package having array of metal pegs linked by printed circuit lines
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
TW533566B (en) * 2002-01-31 2003-05-21 Siliconware Precision Industries Co Ltd Short-prevented lead frame and method for fabricating semiconductor package with the same
CN1466201A (zh) * 2002-06-28 2004-01-07 矽品精密工业股份有限公司 芯片座具凹部的半导体封装件
JP4093818B2 (ja) * 2002-08-07 2008-06-04 三洋電機株式会社 半導体装置の製造方法
TW200425427A (en) 2003-05-02 2004-11-16 Siliconware Precision Industries Co Ltd Leadframe-based non-leaded semiconductor package and method of fabricating the same
US7049683B1 (en) * 2003-07-19 2006-05-23 Ns Electronics Bangkok (1993) Ltd. Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound
TWI257693B (en) * 2003-08-25 2006-07-01 Advanced Semiconductor Eng Leadless package
US7060535B1 (en) * 2003-10-29 2006-06-13 Ns Electronics Bangkok (1993) Ltd. Flat no-lead semiconductor die package including stud terminals
JP4030956B2 (ja) * 2003-12-16 2008-01-09 三菱電機株式会社 電力用半導体装置
WO2005091383A1 (ja) * 2004-03-24 2005-09-29 Renesas Yanai Semiconductor Inc. 発光装置の製造方法および発光装置
CN100466237C (zh) * 2004-07-15 2009-03-04 大日本印刷株式会社 半导体装置与半导体装置制造用基板及该基板的制造方法
CN1738041A (zh) * 2004-08-17 2006-02-22 自由度半导体公司 Qfn封装及其方法
JP4486451B2 (ja) * 2004-09-07 2010-06-23 スタンレー電気株式会社 発光装置、その発光装置に使用するリードフレーム、及びリードフレームの製造方法
US7166905B1 (en) * 2004-10-05 2007-01-23 Integrated Device Technology, Inc. Stacked paddle micro leadframe package
KR101037246B1 (ko) * 2004-10-18 2011-05-26 스태츠 칩팩, 엘티디. 멀티 칩 리드 프레임 패키지
JP4857594B2 (ja) * 2005-04-26 2012-01-18 大日本印刷株式会社 回路部材、及び回路部材の製造方法
KR20080027920A (ko) * 2005-07-08 2008-03-28 엔엑스피 비 브이 반도체 디바이스
TW200729444A (en) * 2006-01-16 2007-08-01 Siliconware Precision Industries Co Ltd Semiconductor package structure and fabrication method thereof
DE102006021959B4 (de) * 2006-05-10 2011-12-29 Infineon Technologies Ag Leistungshalbleiterbauteil und Verfahren zu dessen Herstellung
US7446424B2 (en) 2006-07-19 2008-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for semiconductor package
US20080135990A1 (en) * 2006-12-07 2008-06-12 Texas Instruments Incorporated Stress-improved flip-chip semiconductor device having half-etched leadframe
US20080308886A1 (en) * 2007-06-15 2008-12-18 Infineon Technologies Ag Semiconductor Sensor
US7825517B2 (en) * 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
US7838974B2 (en) * 2007-09-13 2010-11-23 National Semiconductor Corporation Intergrated circuit packaging with improved die bonding
US7808089B2 (en) 2007-12-18 2010-10-05 National Semiconductor Corporation Leadframe having die attach pad with delamination and crack-arresting features
CN101494175B (zh) * 2008-01-22 2012-05-23 北京机械工业自动化研究所 一种三层立体功率封装方法及其结构
TWI364820B (en) 2008-03-07 2012-05-21 Chipmos Technoligies Inc Chip structure
US7732901B2 (en) * 2008-03-18 2010-06-08 Stats Chippac Ltd. Integrated circuit package system with isloated leads
US8030674B2 (en) * 2008-04-28 2011-10-04 Lextar Electronics Corp. Light-emitting diode package with roughened surface portions of the lead-frame
US8178976B2 (en) * 2008-05-12 2012-05-15 Texas Instruments Incorporated IC device having low resistance TSV comprising ground connection
US7821113B2 (en) * 2008-06-03 2010-10-26 Texas Instruments Incorporated Leadframe having delamination resistant die pad
JP2009302209A (ja) 2008-06-11 2009-12-24 Nec Electronics Corp リードフレーム、半導体装置、リードフレームの製造方法および半導体装置の製造方法
US7911067B2 (en) * 2008-09-22 2011-03-22 Stats Chippac Ltd. Semiconductor package system with die support pad
TW201019453A (en) * 2008-11-05 2010-05-16 Windtop Technology Corp MEMS package
SG172749A1 (en) * 2009-03-06 2011-08-29 Kaixin Inc Leadless integrated circuit package having high density contacts
US7858443B2 (en) * 2009-03-09 2010-12-28 Utac Hong Kong Limited Leadless integrated circuit package having standoff contacts and die attach pad
US8044495B2 (en) * 2009-06-22 2011-10-25 Texas Instruments Incorporated Metallic leadframes having laser-treated surfaces for improved adhesion to polymeric compounds
CN106067511A (zh) * 2010-03-30 2016-11-02 大日本印刷株式会社 带树脂引线框、半导体装置及其制造方法
CN102859687B (zh) * 2010-05-12 2015-09-23 瑞萨电子株式会社 半导体器件及其制造方法
JP5613463B2 (ja) 2010-06-03 2014-10-22 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US8716873B2 (en) * 2010-07-01 2014-05-06 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US8586407B2 (en) * 2010-09-17 2013-11-19 ISC8 Inc. Method for depackaging prepackaged integrated circuit die and a product from the method
US8456021B2 (en) * 2010-11-24 2013-06-04 Texas Instruments Incorporated Integrated circuit device having die bonded to the polymer side of a polymer substrate
US8802553B2 (en) * 2011-02-10 2014-08-12 Infineon Technologies Ag Method for mounting a semiconductor chip on a carrier
US20120261813A1 (en) * 2011-04-15 2012-10-18 International Business Machines Corporation Reinforced via farm interconnect structure, a method of forming a reinforced via farm interconnect structure and a method of redesigning an integrated circuit chip to include such a reinforced via farm interconnect structure
JP5558405B2 (ja) * 2011-04-21 2014-07-23 三菱電機株式会社 半導体装置
US8633063B2 (en) * 2011-05-05 2014-01-21 Stats Chippac Ltd. Integrated circuit packaging system with pad connection and method of manufacture thereof
US8513788B2 (en) * 2011-12-14 2013-08-20 Stats Chippac Ltd. Integrated circuit packaging system with pad and method of manufacture thereof
JP5851888B2 (ja) * 2012-03-02 2016-02-03 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
KR101374145B1 (ko) * 2012-04-19 2014-03-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US8587099B1 (en) * 2012-05-02 2013-11-19 Texas Instruments Incorporated Leadframe having selective planishing
US9082759B2 (en) * 2012-11-27 2015-07-14 Infineon Technologies Ag Semiconductor packages and methods of formation thereof
US9515060B2 (en) * 2013-03-20 2016-12-06 Infineon Technologies Austria Ag Multi-chip semiconductor power device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184064B1 (en) * 2000-01-12 2001-02-06 Micron Technology, Inc. Semiconductor die back side surface and method of fabrication
CN101030570A (zh) * 2006-03-03 2007-09-05 三菱电机株式会社 半导体装置
CN101393900A (zh) * 2007-09-20 2009-03-25 株式会社瑞萨科技 半导体器件及其制造方法

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