CN101383293A - 一种微型引线框架半导体封装方法 - Google Patents

一种微型引线框架半导体封装方法 Download PDF

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CN101383293A
CN101383293A CN 200810156009 CN200810156009A CN101383293A CN 101383293 A CN101383293 A CN 101383293A CN 200810156009 CN200810156009 CN 200810156009 CN 200810156009 A CN200810156009 A CN 200810156009A CN 101383293 A CN101383293 A CN 101383293A
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陶少卿
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Phoenix Semiconductor Telecommunication Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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Abstract

微引线框架型半导体封装方法为：a.准备好微型引线框架型封装的引线框架，接着在这个引线框架的基片上贴上若干个单个的IC芯片，b.通过引线键合工艺用金线对芯片和引线框架进行电连接，c.接着进行成型，用环氧塑封料对引线框架上部、芯片、引线进行封装，使引线框架上的导线上部全部不向外露出，d.最后将成型完的微引线框架分离成若干个单个的IC元器件，分离后的单个IC元器件的引脚和连接筋全部被环氧塑封料覆盖。该封装方法是用压力设备的冲头分离出没有外露的引脚和连接筋以及它们之间的环氧塑封料的M.L.F型半导体封装IC元器件并且能够最大程度地减少冲压时产生的冲击力来提高M.L.F型半导体封装元器件的可靠性。

Description

一种微型引线框架半导体封装方法
技术领域
本发明属于半导体封装工艺技术领域，是一种关于能够有效控制利用压力设备的冲头在分离工程中发生环氧塑封料裂纹及环氧塑封料破碎性不良失效的新型封装制造方法。
背景技术
电子产品的体积逐渐小型化，用于电子产品中的半导体封装IC(集成电路)元器件的体积也逐渐小型化，M.L.F(微型引线框架)型半导体封装元器件就是其中之一。M.L.F型封装方式有两种，一种是用刀片切割进行分离，一种是用压力设备的冲头进行分离。当在利用压力设备的冲头进行分离，从引线框架上分离为若干个单独的IC元器件时，M.L.F型IC元器件是有未完全切除的引脚和连接筋，以及引脚和引脚之间、引脚和连接筋之间的环氧塑封料，并且在切割时对IC元器件产生很大的冲击力，可能会在引脚和引脚之间，引脚和连接筋之间的IC元器件表面环氧塑封料发生裂纹，严重时发生IC元器件破碎性不良，这些不良易导致外界湿气渗透到IC元器件中，从而使微引线框架型IC元器件的信赖性降低。本发明能够很好的改善这个技术难题，在构造上提供能够控制裂纹及环氧塑封料破碎性不良的M.L.F型半导体封装。
发明内容
技术问题：本发明是提供一种微引线框架型半导体封装方法，该封装方法是用压力设备的冲头分离出没有外露的引脚和连接筋以及它们之间的环氧塑封料的M.L.F型半导体封装IC元器件并且能够最大程度地减少冲压时产生的冲击力来提高M.L.F型半导体封装元器件的可靠性。
技术方案：本发明的微引线框架型半导体封装方法具体为：
a.准备好微型引线框架型封装的引线框架，接着在这个引线框架的基片上贴上若干个单个的IC芯片，
b.通过引线键合工艺用金线对芯片和引线框架进行电连接，
c.接着进行成型，用环氧塑封料对引线框架上部、芯片、引线进行封装，使引线框架上的导线上部全部不向外露出，
d.最后将成型完的微引线框架分离成若干个单个的IC元器件，分离后的单个IC元器件的引脚和连接筋全部被环氧塑封料覆盖。
所述将成型完的微引线框架分离成若干个单个的IC元器件的方法是使用装有冲击缓和物的金型中的冲头冲压完成。
为了更好地控制环氧塑封料裂纹及破碎性不良的发生，改善M.L.F型封装IC元器件的信赖性，需要在压力设备的上金型上设置冲击缓和物，这些冲击缓和物可以是上金型上设置的弹簧或上金型表面设置的覆膜物质。
有益效果：有效控制环氧塑封料裂纹及破碎性不良，阻止外界湿气渗透到时IC元器件的途径，可以改善利用压力设备的冲头分离微引线框架型半导体IC元器件时造成的信赖性不良。
附图说明
图1是现有技术的M.L.F型IC元器件封装的截面图，
图2是现有技术的M.L.F型封装IC元器件的平面图，
图3是本发明的实施例子M.L.F型封装IC元器件的截面图，
图4是本发明的实施例子M.L.F型封装IC元器件的平面图，
图5是本发明的实施例子M.L.F型封装IC元器件的背面图，
图6是说明本发明M.L.F型封装IC元器件的制造方法的截面图。
具体实施方式
图1是现有技术的M.L.F型IC元器件封装的截面图，图中表明现有技术M.L.F型半导体封装30，由用环氧塑封料20封装了粘贴芯片的基片部12及引脚14组成的微引线框架型引线框架10和基片上粘贴的芯片以及连接芯片16和引脚14之间的引线18组成。
图2是现有技术的M.L.F型封装IC元器件的平面图，引线框架10的引脚14的向外露出部分24，引线框架10的连接筋向外露出部分22，外露的引脚与引脚之间的环氧塑封料26。
图3是本发明的实施例子M.L.F型封装IC元器件的截面图，图中表明本发明的实施例子M.L.F型IC元器件封装30，由用环氧塑封料140封装了粘贴芯片的基片部114及引脚112组成的微引线框架型引线框架110和基片上粘贴的芯片以及连接芯片120和引脚112之间的引线130组成。
图4是本发明的实施例子M.L.F型封装IC元器件的平面图，图中有：方向标记142，起到表示引脚112的基准点的作用。
图5是本发明的实施例子M.L.F型封装IC元器件的背面图，图中有：封装元器件下面露出连接PCB(印刷电路板)的引脚112，粘贴芯片的基片114也是外露的构造，连接筋116。
图6是说明本发明M.L.F型封装IC元器件的制造方法的截面图，图中有：上部的金型210，下部的金型200，冲头220，冲击缓和物212，上部金型设置的覆膜物质214。
本发明是这样实现的，将芯片粘贴到引线框架的基片上面，再在芯片和引线框架之间用金线进行电连接，接着用环氧塑封料把芯片和金线以及引线框架上部进行封装，使引脚不露出，再进行分离，分离成单个的IC元器件的制造方法。
准备好M.L.F型封装的引线框架，接着在这个引线框架的基片上贴上芯片，通过引线键合工程用金线对芯片和引线框架进行电连接，接着进行成型工程，用环氧塑封料对引线框架上部，芯片，引线进行封装，使引线框架上的引脚上部全部不向外露出，最后在分离工程将上面成型完的引线框架分离成单个IC元器件。
在分离工程时，成型完的M.L.F型封装IC元器件固定在下部金型和上部金型之间，冲头在压力下下降，将微引线框架型半导体封装元器件分离成单个IC元器件。由于在上部金型设置了弹簧等冲击缓和物进行缓冲，能够减少施加到封装元器件上的冲击力，所以能够抑制发生在M.LF型封装IC元器件中的裂纹及破碎性不良。
上面使用的冲击缓和物可以变形为其他形态，只要能够把施加到M.LF型封装IC元器件上的冲击力最小化即可，可以在封装元器件接触的上部金型表面覆盖一层冲击缓和物，比如人造橡胶等。
本发明不限于上面的实施方式，在本发明所属的技术思想范围内可以进行更多的变化。

Claims (2)

1.一种微引线框架型半导体封装方法，其特征在于该方法为：
a.准备好微型引线框架型封装的引线框架，接着在这个引线框架的基片上贴上若干个单个的IC芯片，
b.通过引线键合工艺用金线对芯片和引线框架进行电连接，
c.接着进行成型，用环氧塑封料对引线框架上部、芯片、引线进行封装，使引线框架上的导线上部全部不向外露出，
d.最后将成型完的微引线框架分离成若干个单个的IC元器件，分离后的单个IC元器件的引脚和连接筋全部被环氧塑封料覆盖。
2.根据权利要求1所述的一种微引线框架型半导体封装方法，其特征在于所述将成型完的微引线框架分离成若干个单个的IC元器件的方法是使用装有冲击缓和物的金型中的冲头(220)冲压完成。
CN 200810156009 2008-09-26 2008-09-26 一种微型引线框架半导体封装方法 Expired - Fee Related CN101383293B (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446781A (zh) * 2011-12-08 2012-05-09 华中科技大学 相变存储器芯片的封装方法
CN105720034A (zh) * 2014-12-19 2016-06-29 新光电气工业株式会社 引线框架、半导体装置
CN110429075A (zh) * 2019-07-19 2019-11-08 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法
CN115841958A (zh) * 2023-02-20 2023-03-24 广州丰江微电子有限公司 提高引线框架与塑封料结合力的方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446781A (zh) * 2011-12-08 2012-05-09 华中科技大学 相变存储器芯片的封装方法
CN102446781B (zh) * 2011-12-08 2014-09-24 华中科技大学 相变存储器芯片的封装方法
CN105720034A (zh) * 2014-12-19 2016-06-29 新光电气工业株式会社 引线框架、半导体装置
CN105720034B (zh) * 2014-12-19 2019-07-05 新光电气工业株式会社 引线框架、半导体装置
CN110429075A (zh) * 2019-07-19 2019-11-08 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法
CN110429075B (zh) * 2019-07-19 2020-07-14 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法
WO2021012641A1 (zh) * 2019-07-19 2021-01-28 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法
US11088053B2 (en) 2019-07-19 2021-08-10 Guangdong Chippacking Technology Co., Ltd. Encapsulation structure with high density, multiple sided and exposed leads and method for manufacturing the same
CN115841958A (zh) * 2023-02-20 2023-03-24 广州丰江微电子有限公司 提高引线框架与塑封料结合力的方法

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