CN102446781A - 相变存储器芯片的封装方法 - Google Patents

相变存储器芯片的封装方法 Download PDF

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CN102446781A
CN102446781A CN2011104055438A CN201110405543A CN102446781A CN 102446781 A CN102446781 A CN 102446781A CN 2011104055438 A CN2011104055438 A CN 2011104055438A CN 201110405543 A CN201110405543 A CN 201110405543A CN 102446781 A CN102446781 A CN 102446781A
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CN102446781B (zh
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缪向水
李震
陈伟
瞿力文
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Huazhong University of Science and Technology
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Abstract

本发明公开了相变存储器芯片的封装方法，具体为：首先将需要封装的芯片固定在封装管壳内，然后采用超声键合技术将芯片的电极与管壳的引脚一一相连，最后使用屏蔽盖将其与外界隔离。本发明由于超声键合不需要一个临界键合温度，可在常温下进行，因此对相变存储器芯片本身特性不会有影响；键合时不加电流，不发生熔化，对材料的物理、化学性能没有任何影响，不会形成任何化合物而影响器件的性能，能保持其清洁度，不需经繁琐的清洗处理而直接进行封装，从而达到稳定性好、精度高、重复性好的测试需求。

Description

相变存储器芯片的封装方法
技术领域
本发明属于集成电路封装领域，具体涉及到一种相变存储器芯片的封装方法。
背景技术
现在用于做电极的材料很多，比如Cu、Al、Au、TiW、W、GeWN等。由于相变存储器的特殊性质，即对发热体电阻、热扩散和发热效率要求比较高，Cu、Al、Au等材料属于软质材料且容易扩散，所以不适合做相变存储器的电极；相反，TiW、W、GeWN等电极为硬质材料，它们有合适的电阻，良好的热稳定性，不与相变材料发生反应，与相变材料有良好的结合力，所以目前用于做相变存储器电极的主要材料为TiW、W、GeWN等。目前，对软质材料电极的芯片封装技术已经非常成熟，但是对用TiW、W、GeWN等硬质材料做电极的芯片封装技术还不够成熟。随着相变存储材料越来越广泛的应用，硬质材料电极也会越来越多，随着科技发展，相变存储器芯片的尺寸必然也会越来越小，电极也就会越来越小，为了能方便测试其电学特性，就必须对其进行合适的封装，由于相变存储材料对温度非常敏感及其电极材料的特殊性，常规的封装技术必然会对相变存储芯片的电学性能有很大的影响，为了克服以上困难，就需要发明一种专门用于相变存储器芯片的封装技术，这正是本发明的出发点。
发明内容
本发明的目的是提供一种相变存储器芯片的封装方法，该方法能在不影响相变存储芯片的电学性能条件下，有效的将相变存储器芯片中较小的硬质电极引出与管壳引脚相连接，从而达到稳定性好、精度高、重复性好的测试需求。
相变存储器芯片的封装方法，具体为：首先将需要封装的芯片固定在封装管壳内，然后采用超声键合技术将芯片的电极与管壳的引脚一一相连，最后使用屏蔽盖将其与外界隔离。
所述采用超声键合技术将芯片的电极与管壳的引脚一一相连的具体实现方式为：采用劈刀将金属丝引到电极表面，通过超声振动驱使劈刀对电极施加压力，带动金属丝在电极表面摩擦，金属丝和电极表面产生塑性形变，同时电极金属层界面的氧化薄膜被破坏，使得金属丝和电极表面紧密接触实现焊接。超声键合功率为1W～2W，超声键合时间为20ms～50ms，超声键合压力为10g～50g。
所述劈刀的孔直径为35微米，倒角为45度，所述金属丝为直径35微米铝丝，所述芯片电极为硬质材料电极。
本发明的技术效果体现在：
本发明能有效地封装相变存储器芯片，由于超声键合不需要一个临界键合温度，可在常温下进行，因此对相变存储器芯片本身特性不会有影响。键合时不加电流，不发生熔化，对材料的物理、化学性能没有任何影响，不会形成任何化合物而影响器件的性能，能保持其清洁度，不需经繁琐的清洗处理而直接进行封装。找出合适的键合参数后，正常操作能有效地提高焊接速度和成品率。
附图说明
图1是相变存储器芯片的结构示意图。
图2是固定在铜箔管壳中间的相变存储器芯片俯视示意图。
图3是铝丝穿过劈刀内部示意图。
图4是超声和键合芯片电极示意图。
图5是键合完芯片电极后上拉示意图。
图6是超声和键合管壳引脚示意图。
图7是键合完管壳电极后上拉示意图。
图8是超声键合完芯片后俯视示意图。
图中，1为相变存储器芯片的内部电路，2为相变存储器芯片的电极，3为相变存储器芯片，4为132脚铜箔管壳，5为35微直径45度劈刀，6为35微直径的铝丝，7为管壳引脚电极。
具体实施方式
下面结合附图和实施例对本发明作进一步说明。
本发明相变存储器芯片的封装方法，具体为：首先将需要封装的芯片固定在封装管壳内，然后采用超声键合技术将芯片的电极与管壳的引脚一一相连，最后使用屏蔽盖将其与外界隔离。
所述采用超声键合技术将芯片的电极与管壳的引脚一一相连的具体实现方式为：采用劈刀将金属丝引到芯片电极表面，通过超声振动驱使劈刀对电极施加压力，带动金属丝在电极表面摩擦，金属丝和电极表面产生塑性形变，同时电极金属层界面的氧化薄膜被破坏，使得金属丝和电极表面紧密接触实现焊接。其中，超声键合功率为1W～2W，超声键合时间为20ms～50ms，超声键合压力为10g～50g，所述金属丝可选用金丝、铝丝等，所述芯片电极为硬质材料电极例如TiW、W和GeWN等。
下面以1Mb相变存储器芯片封装为例，图1为1Mb相变存储器芯片结构示意图，其中1为相变存储器芯片的内部电路，2为相变存储器芯片电极，1Mb存储器芯片共59个引脚。封装前，需将1Mb芯片3固定于专用的132脚铜箔管壳4的中间位置，如图2所示，然后才能将其置于超声键合机进行超声键合。本实例中，金属丝选用直径为35微米的铝丝6，劈刀5的参数为：孔直径为35微米，倒角为45度(参见图3)，芯片电极2采用TiW，管壳电极7选用Cu(也可采用Al，Au等软质材料)。
超声键合前，需摸索出各种电极的最适合的超声键合参数，这样才能对芯片电极进行快速合理的引线，表1是经实验得到的几种电极的键合参数：
表1几种电极的键合参数
Figure BDA0000117336940000041
图3到图7是超声键合阶段，也是此封装技术最重要的一步。超声键合是磁致伸缩换能器在超高频63.5KHz/115KHz正弦波磁场的感应下，迅速伸缩而产生弹性振动，经变幅杆传给劈刀，劈刀在对金属样品施加一定压力的情况下，带动铝丝在被焊接的电极表面上迅速摩擦，使铝丝和电极表面产生塑性形变和破坏电极层界面的氧化薄膜(高熔点，不导电)，使得两个纯净的面紧密接触，形成牢固的冶金焊接(如图8所示)。
超声键合的步骤如下：
1.接触和预变形
焊丝由劈刀引到压焊表面。根据设备参数的设定，此时焊机仅仅使引线同压焊表面接触而使引线压扁或产生一定程度的预变形。
2.超声阶段和焊接
将超声频率引到传感器，同传感器连接的劈刀连着引线振动。超声键合的振动频率的是63.5KHz/115KHz。开始时劈刀和引线在稳定的引线和压焊表面压力下一起运动。经过一段时间后引线开始变形，温度上升，焊接出现。压焊表面温度和引线变形的分析表明这个过程可分成三个阶段：
a.清洗过程：超声功率主要是用来产生热量和清洗表面——摩擦清除表面氧化层和污染层，只有很少一部分用来产生变形。在这个过程中，压焊劈刀压着引线在键合表面。
b.混合过程：超声功率用来挤压焊丝和接触表面并引起压焊表面温度明显上升。发生局部焊接和引线焊接到焊盘上。劈刀摩擦基本上固定了引线，焊丝的温度进一步上升。
c.扩散过程：没有明显的变形和温度上升。压焊劈刀摩擦在引线表面产生的热量使得压焊表面温度上升，进一步松弛了焊接的区域。这个回火的过程通过校正扩散接触面，稳定键合点，使它不会太脆。
为了避免外环境的影响，需将其用专门的屏蔽盖将其与外界环境屏蔽，便于测试和长期保持，这样就完成了芯片的最后封装，
以上是通过具体实施例的阐述，以进一步说明本发明实质性特点和显著的进步，但本发明绝非仅局限于硬质电极材料的芯片封装，同样适用于软质电极材料芯片的封装。

Claims (8)

1.相变存储器芯片的封装方法，具体为：首先将需要封装的芯片固定
在封装管壳内，然后采用超声键合技术将芯片的电极与管壳的引脚一一相连，最后使用屏蔽盖将其与外界隔离。
2.根据权利要求1所述的相变存储器芯片的封装方法，其特征在于，所述采用超声键合技术将芯片的电极与管壳的引脚一一相连的具体实现方式为：采用劈刀将金属丝引到电极表面，通过超声振动驱使劈刀对电极施加压力，带动金属丝在电极表面摩擦，金属丝和电极表面产生塑性形变，同时电极金属层界面的氧化薄膜被破坏，使得金属丝和电极表面紧密接触实现焊接。
3.根据权利要求2所述的相变存储器芯片的封装方法，其特征在于，超声键合功率为1W～2W，超声键合时间为20ms～50ms，超声键合压力为10g～50g。
4.根据权利要求2所述的相变存储器芯片的封装方法，其特征在于，所述劈刀的孔直径为35微米，倒角为45度。
5.根据权利要求2所述的相变存储器芯片的封装方法，其特征在于，所述金属丝为铝丝。
6.根据权利要求5所述的相变存储器芯片的封装方法，其特征在于，所述铝丝直径为35微米。
7.根据权利要求2至6任一所述的相变存储器芯片的封装技术，其特征在于，所述电极为硬质材料电极。
8.根据权利要求7所述的相变存储器芯片的封装技术，其特征在于，所述硬质材料电极选用TiW、W或GeWN。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103824786A (zh) * 2013-12-10 2014-05-28 中国电子科技集团公司第四十一研究所 一种粗金丝键合方法
CN104112684A (zh) * 2014-07-03 2014-10-22 上海交通大学 一种基于镍微针锥的固态超声键合方法
CN104112681A (zh) * 2014-07-03 2014-10-22 上海交通大学 一种基于铜微针锥的固态超声键合方法
CN106312289A (zh) * 2016-10-14 2017-01-11 大连理工大学 一种预冲压变形处理的超声波金属焊接方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050269694A1 (en) * 2003-05-02 2005-12-08 Luechinger Christoph B Ribbon bonding in an electronic package
CN101375382A (zh) * 2003-08-14 2009-02-25 宇芯（毛里求斯）控股有限公司 半导体器件封装及其制造方法
CN101383293A (zh) * 2008-09-26 2009-03-11 凤凰半导体通信(苏州)有限公司 一种微型引线框架半导体封装方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050269694A1 (en) * 2003-05-02 2005-12-08 Luechinger Christoph B Ribbon bonding in an electronic package
CN101375382A (zh) * 2003-08-14 2009-02-25 宇芯（毛里求斯）控股有限公司 半导体器件封装及其制造方法
CN101383293A (zh) * 2008-09-26 2009-03-11 凤凰半导体通信(苏州)有限公司 一种微型引线框架半导体封装方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
《中国优秀硕士论文全文数据库》 20060515 杨文建 超细间距引线键合工艺的试验研究 2-8 , *
L.W.QU等: "SET/RESET properties dependence of phase-change memory cell on thickness of phase-change layer", 《SOLID-STATE ELECTRONICS》, vol. 56, no. 1, 11 January 2011 (2011-01-11), pages 191 - 195 *
杨文建: "超细间距引线键合工艺的试验研究", 《中国优秀硕士论文全文数据库》, 15 May 2006 (2006-05-15) *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103824786A (zh) * 2013-12-10 2014-05-28 中国电子科技集团公司第四十一研究所 一种粗金丝键合方法
CN103824786B (zh) * 2013-12-10 2016-08-17 中国电子科技集团公司第四十一研究所 一种粗金丝键合方法
CN104112684A (zh) * 2014-07-03 2014-10-22 上海交通大学 一种基于镍微针锥的固态超声键合方法
CN104112681A (zh) * 2014-07-03 2014-10-22 上海交通大学 一种基于铜微针锥的固态超声键合方法
CN106312289A (zh) * 2016-10-14 2017-01-11 大连理工大学 一种预冲压变形处理的超声波金属焊接方法

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