CN102646645B - 封装结构及其制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims description 22
- 239000011810 insulating material Substances 0.000 claims description 16
- 239000004593 Epoxy Substances 0.000 claims description 6
- 238000000465 moulding Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000005553 drilling Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000012774 insulation material Substances 0.000 abstract 2
- 230000017525 heat dissipation Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 9
- 238000004100 electronic packaging Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000011161 development Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 5
- 239000006185 dispersion Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/732—Location after the connecting process
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- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2224/8119—Arrangement of the bump connectors prior to mounting
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- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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Abstract
本发明提供了一种具有高导热性的导热载板的封装结构及其制造方法,所述封装结构包括:导热载板、芯片、凸点、塑封材料、导电材料、以及绝缘材料。所述制造方法包括:准备芯片;在所述芯片上形成凸点;用塑封材料将形成有凸点的芯片塑封;使所述凸点暴露;在塑封材料上形成电路图案;在所述电路图案中填充导电材料以与凸点电连接;用绝缘材料覆盖所述凸点和导电材料,并暴露导电材料的一端,以实现芯片与外部的电气连接。本发明具有材料成本较低,可靠性和散热性好,且其制造工艺无需新的设备的优点。
Description
技术领域
本发明涉及一种半导体封装结构及其制造方法,更具体地讲,本发明涉及一种不采用带电路的基板(例如印刷电路板(PCB))而是采用具有高导热性的导热载板的封装结构及其制造方法。
背景技术
随着半导体产业的飞速发展及其向各行业的迅速渗透,电子封装已经逐步成为实现半导体芯片功能的一个瓶颈,电子封装因此在近二三十年内获得了巨大的发展,并已经取得了长足的进步。今日的电子封装不但要提供芯片保护,还要在控制成本的同时满足不断增加的功能、可靠性、散热性等性能。电子封装的设计和制造对系统应用正变得越来越重要,电子封装的设计和制造从一开始就需要从系统入手以获得最佳的性能价格比。电子封装发展的驱动力主要来源于半导体芯片的发展和市场需要,可以概括为如下几点:速度及处理能力的增加需要更多的引脚数、更快的时钟频率和更好的电源分配。市场需要电子产品有更多功能,更长的电池寿命和更小的几何尺寸。电子器件和电子产品的需要量不断增加,新的器件不断涌现。市场竞争日益加剧,芯片制造业的发展和电子产品的市场需要将最终决定电子封装的发展趋向于更小、更薄、更轻、功能更强、能耗更小、可靠性更好、更符合环保要求、更便宜等
随着电子技术的飞速发展,封装的小型化和组装的高密度化以及各种新型封装技术的不断涌现,对电子组装质量的要求也越来越高。
在众多的封装形式中,倒装芯片FC(Flip chip)封装由于具有组件尺寸小、性能高和成本低等诸多优点而备受关注。倒装芯片技术由IBM公司在60年代引入,开始使用的是铜凸点,后发展为在芯片上制备高铅焊料凸点再将芯片正面朝下直接贴在陶瓷衬底上,使用回流焊接实现多个焊点的一次性组装。既大大提高了生产效率(当时的金丝球焊机焊接速度较慢),同时由于引线电阻小,寄生电容小,因而获得了优异的性能特别是高频性能。目前倒装芯片技术在计算机、通信等领域已经获得了相当程度的应用,并且正呈高速增长趋势。
目前比较成熟的倒装芯片封装形式通常是包含基板(substrate)13的,如图1所示,其中,基板13一般为印刷电路板,芯片11由塑封材料12塑封,基板包括形成有电路图案的电路板15,芯片11通过电路板和焊球14实现与外部的电气连接。然而,由于使用印刷电路板会提高封装成本,因此,不采用带电路的基板的倒装芯片封装已经成为一种发展趋势。
现有的不采用带电路的基板的封装技术主要分为两种:第一种如图2所示(美国专利US 7,160,755 B2),先在基板23上嵌入一个可导电的载体,然后将芯片21贴到载体上以形成一个导电通路,用塑封材料22塑封后去除基板23,在载体的另一端形成焊球结合24后完成封装;第二种如图3所示(美国专利US 7,772,033 B2),直接在基板33上制作导电线路,然后是贴芯片31和使用塑封材料32塑封,最后是去掉基板33和贴球34。
现有的不采用带电路的基板的封装的主要问题在于材料成本较高,可靠性和散热性能不够理想,且其制造工艺需要新的设备。
发明内容
本发明的目的在于提供一种封装结构及其制造方法,所述封装结构包括不采用带电路的基板而是采用具有高导热性的导热载板,具有良好的可靠性和散热性能。
根据本发明的一方面,提供了一种封装结构,所述封装结构包括:导热载板;芯片,设置在所述导热载板上;凸点,形成在所述芯片上并与芯片电连接;塑封材料,包封所述芯片,塑封材料上形成有电路图案;导电材料,填充在所述电路图案中并与凸点电连接;绝缘材料,覆盖所述凸点和导电材料,并暴露导电材料的一端,以实现芯片与外部的电气连接。
根据本发明的一方面,所述凸点可以通过电镀形成。
根据本发明的一方面,所述凸点可以由焊料形成。
根据本发明的一方面,所述塑封材料可以为环氧模塑料。
根据本发明的一方面,所述封装结构还可以包括焊球,焊球可以设置在导电材料的暴露绝缘材料的一端,用于实现芯片与外部的电气连接。
根据本发明的一方面,导热载板可以为金属。
根据本发明的一方面,提供了一种封装结构的制造方法,所述方法可以包括如下步骤:准备芯片;在所述芯片上形成凸点,凸点与芯片电连接;将形成有凸点的芯片附着到导热载板上;用塑封材料将形成有凸点的芯片塑封;使所述凸点暴露;在塑封材料上形成电路图案;在所述电路图案中填充导电材料以与凸点电连接;用绝缘材料覆盖所述凸点和导电材料,并暴露导电材料的一端,以实现芯片与外部的电气连接。
根据本发明的一方面,所述凸点可以通过电镀形成。
根据本发明的一方面,所述凸点可以由焊料形成。
根据本发明的一方面,所述塑封材料可以为环氧模塑料。
根据本发明的一方面,可以通过研磨或激光打孔的方式使所述凸点暴露。
根据本发明的一方面,可以通过在导电材料的暴露绝缘材料的一端设置焊球来实现芯片与外部的电气连接。
与现有技术相比,本发明材料成本较低,可靠性和散热性能较好,且其制造工艺无需新的设备。
附图说明
图1是通常的倒装芯片封装结构的示意图。
图2是去除基板的倒装芯片封装结构的一个示例的示意图。
图3是去除基板的倒装芯片封装结构的另一个示例的示意图。
图4是根据本发明示例性实施例的具有高导热性的导热载板的封装结构的示意图。
图5至图13C是示出根据本发明示例性实施例的制造具有高导热性的导热载板的封装结构的方法的示意图。
具体实施方式
在下文中参照附图更充分地描述了本发明,在附图中示出了本发明的实施例。然而,本发明可以以许多不同的形式来实施,且不应该解释为局限于在这里所提出的实施例。相反,提供这些实施例使得本公开将是彻底和完全的,并将本发明的范围充分地传达给本领域技术人员。在附图中,为了清晰起见,会夸大层和区域的尺寸和相对尺寸。
图4是示出根据本发明示例性实施例的具有高导热的导热载板的封装结构的示意图。
参照图4,根据本发明的一方面,提供了一种封装结构,所述封装结构包括:导热载板43,由具有高导热性的材料形成,例如,导热载板43可以由金属形成,导热载板43上不具有电路;芯片41,设置在所述导热载板43上;凸点45,形成在所述芯片41上,所述凸点45可以由导电的材料形成,例如,通过电镀形成;塑封材料42,包封所述芯片41,塑封材料42上形成有电路图案48(参照图10A至图10C),所述塑封材料42可以为环氧模塑料(EMC);导电材料47,填充在所述电路图案48中;绝缘材料46,覆盖所述凸点45和导电材料47,绝缘材料46暴露导电材料47的一端,以实现芯片与外部的电气连接。
根据本发明的一方面,所述封装结构还可以包括焊球44,焊球44可以设置在导电材料47的暴露绝缘材料46的一端,从而可以通过在导电材料47的暴露绝缘材料46的一端设置的焊球44来实现与外部的电气连接。然而,本发明不限于此,可以通过其它方式实现导电材料与外部的电气连接。
图5至图13C是示出根据本发明示例性实施例的制造具有高导热的导热载板的封装结构的方法的示意图。
参照图5至图8,根据本发明示例性实施例的封装结构的制造方法包括如下步骤:准备芯片1;在所述芯片1上形成凸点5(例如,可以通过使用电镀的方法在芯片1上形成的铝焊盘表面上形成凸点),所述凸点5可以由导电的材料形成;将形成有凸点5的芯片1附着到具有高导热性的导热载板3上(例如,可以通过导热胶将芯片1粘贴到导热载板3上);用塑封材料2将形成有凸点5的芯片1塑封,所述塑封材料2可以为环氧模塑料。
之后,使所述凸点5暴露。
图9A、10A、11A、12A和13A是示出根据本发明示例性实施例的封装结构的制造方法的通过将塑封材料2研磨使所述凸点暴露以及后续工艺的示意图。
图9B、10B、11B、12B和13B是示出根据本发明示例性实施例的封装结构的制造方法的通过激光打孔使所述凸点暴露以及后续工艺的示意图。
图10C、11C、12C和13C是示出根据本发明示例性实施例的封装结构的制造方法的俯视示意图。
根据本发明示例性实施例的封装结构的制造方法还包括如下步骤:在塑封材料2上形成电路图案8(例如可以通过使用激光形成电路图案或者在塑封材料2表面腐蚀的方法在具有电路图案的模具的引导下在塑封材料2表面上形成电路图案)(参照图10A至图10C);在所述电路图案8中填充导电材料7(例如可以通过在具有电路图案的模具表面涂覆导电材料实现填充)(参照图11A至图11C);用绝缘材料6覆盖所述凸点5和导电材料7(例如可以通过使用具有电路图案的模具将绝缘材料覆盖所述凸点5和导电材料7),使其与外界隔离,绝缘材料6暴露导电材料7的一端,以实现芯片与外部的电气连接,例如,所述一端为导电材料的与凸点相对的一端(参照图12A至图12C)。
根据本发明的一方面,参照图13A至图13C,可以通过在导电材料7的暴露绝缘材料6的一端设置焊球4来实现与外部的电气连接。然而,本发明不限于此,可以通过其它方式实现导电材料与外部的电气连接。
根据本发明示例性实施例的封装结构中没有传统的具有电路的基板,而是包括高导热的导热载板,电路图案设置在塑封材料上,从而提供了具有良好的可靠性和散热性能且降低了成本的封装结构。
尽管已经结合本发明的示例性实施例示出并描述了本发明,然而,本领域普通技术人员应该理解,在不脱离由权利要求限定的本发明的精神和范围的情况下,可以对本发明作出形式和细节上的各种改变。
Claims (8)
1.一种封装结构,所述封装结构包括:
导热载板;
芯片,设置在所述导热载板上;
凸点,形成在所述芯片上并与所述芯片电连接;
塑封材料,包封所述芯片,塑封材料的表面中形成有电路图案;
导电材料,填充在所述电路图案中并与凸点电连接;
绝缘材料,仅覆盖所述凸点和导电材料,并暴露导电材料的远离凸点的一端;
焊球,设置在导电材料的远离凸点的所述一端,用于实现与外部的电气连接,并且使焊球与塑封材料以及绝缘材料的一端接触。
2.如权利要求1所述的封装结构,其中,所述凸点由焊料通过电镀形成。
3.如权利要求1所述的封装结构,其中,所述塑封材料为环氧模塑料。
4.如权利要求1所述的封装结构,其中,导热载板为金属。
5.一种封装结构的制造方法,所述方法包括如下步骤:
准备芯片;
在所述芯片上形成凸点,凸点与芯片电连接;
将形成有凸点的芯片附着到导热载板上;
用塑封材料将形成有凸点的芯片塑封;
使所述凸点暴露;
在塑封材料的表面中形成电路图案;
在所述电路图案中填充导电材料以与凸点电连接;
用绝缘材料仅覆盖所述凸点和导电材料,并暴露导电材料的远离凸点的一端;
在导电材料的远离凸点的所述一端设置焊球,用于实现与外部的电气连接,并且使焊球与塑封材料以及绝缘材料的一端接触。
6.如权利要求5所述的制造方法,其中,所述凸点由焊料通过电镀形成。
7.如权利要求5所述的制造方法,其中,所述塑封材料为环氧模塑料。
8.如权利要求5所述的制造方法,其中,通过研磨或激光打孔的方式使所述凸点暴露。
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