CN1462070A - 一种芯片封装结构 - Google Patents
一种芯片封装结构 Download PDFInfo
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- CN1462070A CN1462070A CN02111890A CN02111890A CN1462070A CN 1462070 A CN1462070 A CN 1462070A CN 02111890 A CN02111890 A CN 02111890A CN 02111890 A CN02111890 A CN 02111890A CN 1462070 A CN1462070 A CN 1462070A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
本发明提供一种经改进的芯片封装结构。传统的BGA(球栅格阵列)封装结构由于使用基板为中间体,而基板的成本占了封装结构成本的约50%以上,因此,传统的封装结构有需改进之必要。本发明的经改进的芯片封装结构包括芯片和焊接于焊盘上的焊球,所述焊球位于所述芯片具有引线焊盘的一侧,所述焊盘与所述芯片的引线焊盘之间通过金属连接线连接,在所述焊球与所述芯片之间的金属连接线中,填充有填充物。本发明的芯片封装结构省却了占较大成本的基板,从而有效地降低了芯片封装成本。
Description
技术领域
本发明涉及一种芯片的封装结构,尤其涉及一种无基板部分进行直接封装的芯片封装结构。
背景技术
在现有的半导体封装技术中,有一种已为大家所熟知的球栅阵列(BGA)的封装方法,例如美国专利US 5216278揭示了这种技术,其为一种高引脚的器件提供了一种有效的解决方案。
下面参照图4和图5简述这种已知的封装方法。图4是传统球栅阵列封装结构的外形示意图;图5是传统球栅阵列封装结构的剖面示意图。如图4和5所示,这种封装结构包括基板101和半导体芯片102,在制造中,半导体芯片102一般采用粘接剂103固定到基板101的表面上。芯片102通过芯片信号引线104连接到基板101上表面上的引线焊盘105。该引线焊盘105通过具有金属镀层106的过孔107与基板101下表面的焊盘110相连通。在基板101下表面的焊盘110上贴装有焊球108。在基板101贴有芯片102的一侧,用一种热固性树脂,采用注塑的方法形成一层塑封体109,从而完成芯片102的封装。
上述这种传统的芯片封装方法由于以基板为基础,而在实践中,基板占整个封装成本约50%以上。因此,这种传统的封装结构存在着成本高的缺陷。
发明内容
因此,本发明的目的在于提供一种经改进的芯片封装结构,它省却了传统结构中的基板,从而有效地降低芯片封装结构的成本。
根据本发明的上述目的,本发明提供的一种经改进的芯片封装结构包括:芯片和焊接于焊盘上的焊球,所述焊球位于所述芯片具有引线焊盘的一侧,所述焊盘与所述芯片的引线焊盘之间通过金属连接线连接,在所述焊球与所述芯片之间的金属连接线中,填充有填充物。
根据上述的芯片封装结构,还包括保护层,所述保护层包覆所述芯片和所述填充物。
根据上述的芯片封装结构,所述填充物为环氧树脂。
根据上述的芯片封装结构,所述填充物为热固性树脂。
如上所述,由于本发明的封装结构中除去了利用基板作为中间体,芯片与焊盘焊球之间直接通过金属连接线来连接,中间填充以填充物,从而在保证封装性能的前提下,有效地降低了封装成本。
附图说明
下面结合附图详细描述本发明的具体实施例,附图中,
图1是本发明的芯片封装结构的剖面图;
图2是本发明的芯片封装结构的带有保护层的实施例的剖面图;
图3是本发明的芯片封装结构的外形图;
图4是已有技术的芯片封装结构的外形图;以及
图5是已有技术的芯片封装结构的剖图示意图。
具体实施方式
如图1所示,图1示出了本发明经改进的芯片封装结构的内部结构示意图。请参照图1,图中,1为需封装的芯片,在芯片1上表面,具有引线焊盘2,引线焊盘2通过金属连接线3与位于芯片同侧的焊盘4电连接,在芯片1的引线焊盘2与焊盘2之间的金属连接线3中,填充填充物5,该填充物5一般采用绝缘材料,例如环氧树脂、热固性树脂等聚合物。在焊盘4上,利用传统工艺,焊接上焊球6,从而完成芯片的封装工艺。
将本发明的芯片封装结构与图4和5所示的传统的芯片封装结构相比,省却了基板,简化了芯片的引线方式,因此,有效地降低了芯片封装成本,提高封装效率。而且,还增加了一个焊盘4,以增大金属连接线3与焊球6之间的焊接面积,增强了焊接的强度。
图2示出了本发明的另一种具有保护层的封装结构的实施例。图2的实施例与前一实施例的区别在于,增加了一个保护层,即,在芯片1和填充物5外设置一个保护层7,使保护层7包覆芯片1和填充物5。该保护层7可以根据需要使用金属或非金属,其作用为散热或者放大构装体尺寸。
图3示出了本发明的芯片封装结构的外形图,本发明芯片封装结构不仅能有效地降低成本,而且从外形上看,其厚度也较传统的封装结构更薄。
上面已根据通过本发明的具体实施例,对本发明作了详细的描述。但应当理解,这里的描述不应被视为对本发明的限制。熟悉本技术领域者,理解了本发明的思想和精神后,可以在此基础上作出某些变化或修饰,而不需要创造性劳动。因此,本发明的保护范围应由所附的权利要求书来限定。
Claims (4)
1、一种经改进的芯片封装结构包括:芯片和焊接于焊盘上的焊球,所述焊球位于所述芯片具有引线焊盘的一侧,所述焊盘与所述芯片的引线焊盘之间通过金属连接线连接,在所述焊球与所述芯片之间的金属连接线中,填充有填充物。
2、如权利要求1所述的芯片封装结构,其特征在于,还包括保护层,所述保护层包覆所述芯片和所述填充物。
3、如权利要求1或2所述的芯片封装结构,其特征在于,所述填充物为环氧树脂。
4、如权利要求1或2所述芯片封装结构,其特征在于,所述填充物为热固性树脂。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102468277A (zh) * | 2010-11-11 | 2012-05-23 | 三星半导体(中国)研究开发有限公司 | 多芯片层叠封装结构及其制造方法 |
CN102646645A (zh) * | 2011-02-16 | 2012-08-22 | 三星半导体(中国)研究开发有限公司 | 封装结构及其制造方法 |
WO2015109596A1 (zh) * | 2014-01-26 | 2015-07-30 | 清华大学 | 一种封装结构、封装方法及在封装方法中使用的模板 |
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2002
- 2002-05-31 CN CN02111890A patent/CN1462070A/zh active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102468277A (zh) * | 2010-11-11 | 2012-05-23 | 三星半导体(中国)研究开发有限公司 | 多芯片层叠封装结构及其制造方法 |
CN102646645A (zh) * | 2011-02-16 | 2012-08-22 | 三星半导体(中国)研究开发有限公司 | 封装结构及其制造方法 |
CN102646645B (zh) * | 2011-02-16 | 2015-03-18 | 三星半导体(中国)研究开发有限公司 | 封装结构及其制造方法 |
WO2015109596A1 (zh) * | 2014-01-26 | 2015-07-30 | 清华大学 | 一种封装结构、封装方法及在封装方法中使用的模板 |
US9960093B2 (en) | 2014-01-26 | 2018-05-01 | Tsinghua University | Packaging structure, packaging method and template used in packaging method |
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