CN1274019C - 将管芯附着到衬底上的方法 - Google Patents

将管芯附着到衬底上的方法 Download PDF

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CN1274019C
CN1274019C CNB031051677A CN03105167A CN1274019C CN 1274019 C CN1274019 C CN 1274019C CN B031051677 A CNB031051677 A CN B031051677A CN 03105167 A CN03105167 A CN 03105167A CN 1274019 C CN1274019 C CN 1274019C
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semiconductor device
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CN1442898A (zh
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郑文汉
周伟煌
何伟强
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NXP USA Inc
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Abstract

一种半导体器件30包括一个底座32，一个粘合材料层36和一个集成电路管芯34。底座32具有一个顶面和一个底面，顶面具有一个用于接收管芯34的中央区和一个包围中央区的周边区。粘合材料层36按一种“X”形图形分配在底座的顶面上。“X”形图形包括两个平分线。两个平分线充分延伸到底座顶面的中央区外面和周边区中。管芯34在中央区处用粘合材料层36附着到底座32上。即使在附着管芯34之后，粘合材料36也充分延伸到管芯34和中央区外面和周边区中。

Description

将管芯附着到衬底上的方法
发明领域
本发明涉及集成电路以及一种封装集成电路的方法，更具体地说，涉及一种将管芯附着到衬底上的方法。
背景技术
集成电路(IC)管芯是一种在半导体晶片，如：硅晶片上形成的小器件。这种管芯通常是从晶片上切割下来并附着到衬底或基底座上用于互连重新分配。管芯上的焊盘然后通过引线焊接与基底座的引线电连接。用保护性材料将管芯和引线焊接的部分封起来，以便形成封装。在封装中被封起来的引线在基底座内导体网络中再分配，且最终成为封装外部的一个接线终点阵列。视封装类型而定，这些接线终点可以照原样使用，如在薄型小外壳封装(TSOP)中，或者进行进一步处理，如通过附着球形焊球用于焊球网格阵列(BGA)封装。接线终点使管芯可以与其它电路电连接，：如在印刷电路板上。IC管芯也可以附着到其它的管芯上，以便形成一种叠层式多片器件。
现在参见图1，图1示出常规的TSOP 10的放大侧视图。TSOP 10包括一个用粘合材料层16附着到叶片(paddle)14上的集成电路或管芯12。集成电路12利用引线焊接20与引线框架的管脚18电连接。将集成电路12，叶片14，和引线焊接20，如：用一种模制塑料22，进行封装，。
常规的管芯附着法用一定量的粘合材料16覆盖叶片14，粘合材料16的量仅仅精确地匹配管芯尺寸。这样，如图2中所示，当集成电路12压到粘合材料16上时，粘合材料16只延伸到管芯尺寸外面一个距离，该距离约等于管芯或集成电路12的高度。
图3是用粘合材料16附着到叶片14上的集成电路12顶部平面图。正如可以看到的，有一大部分叶片未被集成电路12或粘合材料16盖住。
某些器件采用一种外露的焊盘设计(EP)进行封装，以便增加散热作用和改善某些电特性。在一种外露的管芯附着焊盘设计中，管芯附着焊盘直接焊接到印刷电路板(PCB)上。也就是说，管芯直接附着到一个金属叶片上，金属叶片直接焊接到PCB上。然而，在处理和焊接这些EP封装时，必需特别小心。这些EP封装在焊接之前必需在干燥环境中处理，并且在组装之前必需使暴露于潮湿气氛下最少以保证可靠的性能。在管芯附着过程中覆盖粘合材料16对现场操作可靠性来说是很关键的。粘合材料16厚度中的空隙和变动是不希望有的。另外，管芯附着材料16覆盖不足使器件由于，例如：分离而对可靠性失效很敏感。在管芯附着粘合剂中形成的湿气也可能造成分离。上述管芯附着法在240℃回流条件下在一定程度上只达到湿敏级三级(MSL-3)。
人们希望能用一种粘合剂将管芯附着到叶片、衬底或载体上，以使器件对湿度不太敏感并且更可靠。
附图简述
当结合附图阅读本说明书时，将能更好地理解上述概述及下面对本发明优选实施例的详细说明。为了说明本发明，在附图中示出了一些目前优选的实施例。然而，应该理解，本发明不限于所示的精确安排和手段。在附图中：
图1是一种常规的薄型小外壳封装的放大剖视图；
图2是用常规方法附着到载体上的IC管芯放大侧视图；
图3是图2的管芯和载体的放大顶部平面图；
图4是根据本发明第一实施例所述的附着到载体上的管芯放大顶部平面图；
图5是图4的管芯和载体的放大侧视图；
图6是根据本发明一个实施例所述管芯附着材料第一图形的放大顶部平面图；及
图7是根据本发明一个实施例所述管芯附着材料第二图形的放大顶部平面图。
优选实施例的详细说明
这里，把下面结合附图所做的详细说明作为本发明目前优选实施例的详细说明，但并不是要代表本发明可以实施的唯一形式。应该理解，利用打算包括在本发明的精神和范围内的不同实施例，可以完成相同或等效的功能。为简化起见，用来说明本发明的一些例子涉及到TSOPs。然而，本发明可以应用于其它的封装并且对EP型封装特别有用，在上述EP型封装中，至少金属管芯焊盘的一侧露出。
为了容易举例说明，对附图中的某些部分进行了放大，并且各附图及其元件不一定按合适的比例示出。然而，本领域的技术人员很容易理解这些细节。在各图中，相同的标号始终表示相同的元件。
为了提供一种可靠的集成电路，本发明是一种半导体器件，包括一个底座，一个粘合材料层，和一个集成电路管芯。底座具有一个顶面和一个底面，顶面具有一个中央区和一个周边区。中央区用于接收集成电路管芯。粘合材料层设置在底座的顶面上。粘合材料层基本上覆盖底座顶面的全部中央区和周边区。集成电路管芯在中央区处用粘合材料层附着到底座上。
本发明还提供一种新型管芯附着扩散图形，该管芯附着扩散图形在240℃回流时的MSL-1和260℃回流时的MSL-2的联合电子器件工程委员会(JEDEC)条件下增强叶片界面处的抗分层性很有效。按照这个实施例，本发明提供一种半导体器件，包括一个底座，一个粘合材料层，和一个集成电路管芯。底座具有一个顶面和一个底面，顶面具有一个用于接收管芯的中央区域一个周边区。粘合材料层设置在上述底座的顶面上。粘合材料层以一种“X”形图形设置在底座的顶测上，该“X”形图形具有两个平分线，这两个平分线延伸到中央区之外并延伸到底座顶面的周边区中。管芯用中央区处的X形粘合材料层附着到底座上。
本发明还包括这样把管芯附着材料分配到叶片的顶面上，以便管芯附着材料基本上覆盖叶片的整个顶面，而与待附着到叶片上的管芯尺寸无关。因此，按照这个实施例，本发明提供一种把集成电路管芯附着到底座上的方法，该方法包括以下步骤：
将一种粘合材料分配到底座顶面的中央区上，其中设定中央区的尺寸以便接收集成电路管芯，并且中央区被周边区包围；和
用粘合材料将集成电路管芯的底面附着到底座顶面的中央区上，其中分配到底座顶面上的粘合材料充分延伸到底座顶面的周边区中。
现在参见图4，图4示出根据本发明的一种半导体器件30的其中一部分顶部平面图。器件30包括一个底座32，该底座32具有一个顶面(部分可见)和一个底面。顶面具有一个用于接收集成电路管芯34的中央区和一个周边区。如图所示，周边区包围中央区和管芯34。底座32是本领域技术人员所公知的一种类形。底座32可以是一种引线框架叶片，印刷电路板，衬底等。
粘合材料层36设置在底座32的顶面上。粘合材料层覆盖上述底座32顶面的大部分中央区和周边区。也就是说，按照本发明，器件30扩大了粘合材料覆盖范围。扩大了的粘合材料覆盖范围意思是指，粘合材料延伸到管芯34的边缘外部，并且这种延伸大于或等于管芯厚度的两倍。图5是放大的侧视图，示出了粘合材料层36如何充分延伸到中央区(亦即管芯34的周长)的外部和延伸到周边区中。
粘合材料36是本领域技术人员众所周知的一种类型的优选的管芯附着粘合剂，它能提供低吸湿并能散热的特点。如果使用导电粘合材料，优选的是提供均匀的金属间组成。某些粘合剂的例子是焊料，环氧树脂，改性环氧树脂，和氰酸盐酯共混物(Cyanate Esterblends)。粘合材料可以充以颗粒物，以便增加散热性能。
集成电路管芯34在底座32的中央区处用粘合材料层36附着到底座32上。在管芯附着以后，通常是在125-175℃之间的温度范围下使粘合材料固化。集成电路管芯34可以是本领域技术人员所公知的一种类型，如在硅片上形成并从硅片切下的一个电路。底座32顶面的中央区被定好尺寸和形状，以便接收管芯34。典型的管芯尺寸可以是从4mm×4mm到12mm×12mm的范围内。管芯34的厚度可以在约6密耳到约21密耳的范围内。例如，如果管芯34是8mm×8mm×6密耳，则中央区是8mm×8mm，并且从中央区边缘到周边区的外部边缘之间的距离(亦即周边区的宽度)大于12密耳，并且通常是在约13密耳到15密耳的范围内。
如上所述，粘合材料层36充分延伸到中央区外部并基本上覆盖底座32的全部顶面。在另一个例子中，如果管芯34是8mm×8mm×6密耳且底座32是12mm×12mm，则粘合材料层36优选的是约10.4mm×10.4mm。
在本发明的一个实施例中，底座32可以是一种引线框架的叶片。在这个实施例中，管芯34上的焊盘可以用一种公知的方式引线焊接到引线框架的指形件上，因此管芯34导电地连接到引线框架指形件上。底座或叶片32，管芯34和至少一部分指形件可以用一种塑料或环氧树脂的树脂材料封起来，形成一种保护性密封。本发明为EP型封装提供最大的好处，因为EP封装通常需要使露出的焊盘达到最大，而不管用于最大热性能的尺寸，这造成更多的小管芯在大管芯焊盘上的情况。成完全密封形式的封装，如图1所示，及采用一种有机衬底的封装，象BGAs，较少能从本发明预定的粘合材料覆盖物得到好处。
现在参见图6，在本发明的一个优选实施例中，底座32包括一个用于接收集成电路管芯的中央区38和一个周边区。管芯附着材料40呈“X”形图形分布在底座32的一个表面上，“X”的支腿完全延伸到中央区38的外部并延伸到底座32的角中。“X”形图形包括两个平分线，这两个平分线延伸到底座顶面的中央区38外面和周边区中。然后可以用粘合材料层将集成电路管芯附着到底座32的中央区38上。可以用市售设备按控制的量将管芯附着或粘合材料分配到底座32上。
现在参见图7，在本发明的另一个优选实施例中，底座32包括一个用于接收集成电路管芯的中央区38和一个周边区。管芯附着材料42以一种星形图形分布在底座32的一个表面上。正如可以看到的那样，星形图形的各尖头都完全延伸到底座32的中央区38外部并延伸到底座32的各角落中。更具体地说，星形图形包括两个平分线，这两个平分线延伸到底座顶面的中央区38外部和周边区的各角落中。星形图形可以包括一个或两个附加的线段。例如，上述图形可以包括一个第一线段，该第一线段这样从底座32第一侧面周边区的中部延伸到底座32第二，相对侧面周边区的中部，以便粘合材料层42形成一种六个尖头的星。
星形图形还可以包括一个第二线段，该第二线段这样从底座32第三侧面周边区的中部延伸到底座32第四，相对侧面周边区的中部，以便粘合材料层42形成一种八个尖头的星。然后，可以用星形粘合材料层将集成电路管芯附着到底座32的中央区38上。
根据本发明，将集成电路管芯附着到底座上的方法包括以下步骤：将一种粘合材料分配到底座顶面的中央区上，然后用粘合材料将集成电路管芯的底面附着到底座顶面上的中央区上。如上所述，中央区被定好尺寸，以便接收集成电路管芯，并且中央区被周边区包围。粘合材料被这样分配到底座的顶面上，以便它完全延伸到底座顶面的周边区中。粘合材料以受控的方式，并以一种预定的图形，如：“X”形或星形分配。
本发明提供一种简单而廉价的方法来改善EP封装湿度水平性能，并且不要求任何主要的材料改变。本发明还可以将具有大管芯焊盘的单根引线框架部分供大尺寸器件和小尺寸器件二者用，这样减少了引线框架用品的库存品种。
上面已经给出了本发明优选实施例，用于说明的目的。但这些说明不是详尽无遗的或是将本发明限于所公开的形式。本领域的技术人员将会理解，在不脱离本发明广泛的发明思想情况下，对上述实施例可以作各种改变。此外，管芯和叶片尺寸也可以改变，以便适应所要求的封装设计。因此，应该理解，本发明不限于所公开的一些特定的实施例，它包括如所附权利要求所述的本发明精神和范围内的变更。

Claims (18)

1.一种半导体器件，包括：
一个底座，该底座具有一个顶面和一个底面，顶面具有一个用于接收集成电路的中央区和一个周边区；
一层延伸的粘合材料层，被设置在底座的顶面上，该粘合材料层覆盖底座顶面的中央区和大部分周边区，其中该粘合材料延伸超过管芯边缘一个大于管芯厚度两倍的距离；及
一个集成电路管芯，该管芯在中央区处用粘合材料层附着到底座上。
2.根据权利要求1的半导体器件，其中底座包括一个叶片。
3.根据权利要求2的半导体器件，还包括一个与集成电路管芯电连接的引线框架。
4.根据权利要求3的半导体器件，还包括一种密封包装材料，该密封包装材料包围底座、集成电路管芯和至少一部分引线框架。
5.根据权利要求3的半导体器件，其中所述器件是一种露出焊盘式封装器件。
6.一种半导体器件，包括：
一个底座，该底座具有一个顶面和一个底面，顶面具有一个用于接收集成电路管芯的中央区和一个周边区；
一层延伸的粘合材料层，该粘合材料层设置在底座的顶面上，其中粘合材料层以一种“X”形图形分布在底座的顶面上，“X”形图形包括两条平分线，其中两条平分线延伸到底座顶面中央区的外部并延伸到底座顶面的周边区中；及
一个集成电路管芯，该管芯在中央区处用粘合材料层附着到底座上。
7.根据权利要求6的半导体器件，其中粘合材料的“X”形图形，还包括一个第一线段，该第一线段从底座的一个第一侧边周边区的中部延伸到底座的一个第二、相对侧边周边区的中部，以使粘合材料层形成一种六个尖端的星。
8.根据权利要求7的半导体器件，其中粘合材料层的“X”形图形还包括一个第二线段，该第二线段从底座第三侧边周边区的中部延伸到底座的第四、相对侧周边区的中部，以使粘合材料层形成一种八个尖端的星。
9.根据权利要求6的半导体器件，其中底座包括一个叶片。
10.根据权利要求9的半导体器件，还包括一个与集成电路管芯电连接的引线框架。
11.根据权利要求10的半导体器件，还包括一种密封包装材料，该密封包装材料包围底座、集成电路管芯和至少一部分引线框架。
12.根据权利要求10的半导体器件，其中半导体器件包括一种露出焊盘式封装的器件。
13.一种将集成电路管芯附着到底座的方法，包括以下步骤：
将一种粘合材料分配到底座顶面的中央区上，其中中央区被定好尺寸以便接收集成电路管芯，并且中央区被周边区包围；及
用粘合材料将集成电路管芯的底面附着到底座顶面的中央区上，其中分配到底座顶面上的粘合材料充分延伸到底座顶面的周边区中，其中该粘合材料延伸超过管芯边缘一个大于管芯厚度两倍的距离。
14.根据权利要求13的将集成电路管芯附着到底座上的方法，其中所分配的粘合材料基本上覆盖底座的整个顶面。
15.根据权利要求13的将集成电路管芯附着到底座上的方法，其中粘合材料按照预定的图形分配到底座顶面上。
16.根据权利要求15的将集成电路管芯附着到底座上的方法，其中预定的图形包括一种“X”图形。
17.根据权利要求15的将集成电路管芯附着到底座上的方法，其中预定图形包括一种六个尖端的星形图形。
18.根据权利要求15的将集成电路管芯附着到底座上的方法，其中预定图形包括一种八个尖端的星形图形。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869831B2 (en) * 2001-09-14 2005-03-22 Texas Instruments Incorporated Adhesion by plasma conditioning of semiconductor chip surfaces
US7238550B2 (en) * 2002-02-26 2007-07-03 Tandon Group Ltd. Methods and apparatus for fabricating Chip-on-Board modules
JP2009099709A (ja) * 2007-10-16 2009-05-07 Nec Electronics Corp 半導体装置
US8348370B2 (en) * 2008-01-18 2013-01-08 Hewlett-Packard Development Company, L.P. Assay system and method
US20100051577A1 (en) * 2008-09-03 2010-03-04 Micron Technology, Inc. Copper layer processing
US7897481B2 (en) * 2008-12-05 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. High throughput die-to-wafer bonding using pre-alignment
US9230928B2 (en) * 2011-09-12 2016-01-05 Conexant Systems, Inc. Spot plated leadframe and IC bond pad via array design for copper wire
DE102015000063A1 (de) * 2015-01-12 2016-07-14 Micronas Gmbh IC-Gehäuse
EP3489991A4 (en) * 2016-08-22 2020-10-21 Senju Metal Industry Co., Ltd METAL Sintered Bonding Body and Chip Bonding Method
US9837333B1 (en) 2016-09-21 2017-12-05 International Business Machines Corporation Electronic package cover having underside rib

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2309388A (en) * 1987-08-26 1989-03-31 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and method of producing the same
US5336639A (en) * 1993-06-28 1994-08-09 Motorola, Inc. Method for securing a semiconductor chip to a leadframe
US5691567A (en) * 1995-09-19 1997-11-25 National Semiconductor Corporation Structure for attaching a lead frame to a heat spreader/heat slug structure
US5822848A (en) * 1996-06-04 1998-10-20 Industrial Technology Research Institute Lead frame having a detachable and interchangeable die-attach paddle
US6238223B1 (en) 1997-08-20 2001-05-29 Micro Technology, Inc. Method of depositing a thermoplastic polymer in semiconductor fabrication
US6265530B1 (en) 1998-07-02 2001-07-24 National Starch And Chemical Investment Holding Corporation Die attach adhesives for use in microelectronic devices
US6258626B1 (en) * 2000-07-06 2001-07-10 Advanced Semiconductor Engineering, Inc. Method of making stacked chip package
US20020182774A1 (en) * 2001-05-29 2002-12-05 Heckman James Kent Die-attach method and assemblies using film and epoxy bonds

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