CN1170234A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN1170234A
CN1170234A CN97113834A CN97113834A CN1170234A CN 1170234 A CN1170234 A CN 1170234A CN 97113834 A CN97113834 A CN 97113834A CN 97113834 A CN97113834 A CN 97113834A CN 1170234 A CN1170234 A CN 1170234A
Authority
CN
China
Prior art keywords
copper foil
foil plate
protective layer
semiconductor device
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN97113834A
Other languages
English (en)
Other versions
CN1087102C (zh
Inventor
池水守彦
奥友贵之
福冈大
竹内正文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1170234A publication Critical patent/CN1170234A/zh
Application granted granted Critical
Publication of CN1087102C publication Critical patent/CN1087102C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明半导体装置针对下述课题:对TAB带与加强体进行热压接时,未加足够压力的位置粘接不够紧密,随后经加热工序,粘接不够紧密的位置上TAB带就会弯曲,致使焊球平整性变差。本发明在TAB带上未设置焊盘11、引线12的粘接剂14上设有伪铜箔图版13,通过使其上面覆盖的焊料保护层的上表面均匀,以便热压接时可均匀加压。

Description

半导体装置
本发明涉及一种多插脚半导体装置，尤其涉及用于带型BGA的TAB带。
图3示出现有三层结构的TAB带的俯视图。图4是图3所示的TAB带的剖面图。图3和图4所示的TAB带由例如聚酰亚胺制成的树脂带35，涂覆在该树脂带上的粘接剂34，和该粘接剂上形成的铜箔图版31、32所构成。铜箔图版由带焊球的焊盘31和使该焊盘31与半导体芯片连接的引线32所组成。此外，还在TAB带的铜箔一侧整面涂覆焊剂保护层33，以保护铜箔图版31、32。若铜箔图版的膜厚设定为例如18μm的话，涂覆铜箔图版31、32上的焊剂保护层33的上表面与直接涂覆在粘接剂34上的焊剂保护层33的上表面的高低落差有18μm。
然后，在加强体上粘接TAB带聚酰亚胺这一面。图5是BGA带所用的加强体。该加强体由金属板52和在该金属板52上涂覆的粘接剂51所组成。
图6示出对图4所示的TAB带与图5所示的加强体进行热压接的工艺。下面对与图4、图5相同的组成部分加相同标号，并省略其说明。如图6所示，用夹具61、62，从上下方向夹住TAB带与加强体。接着，边加热，边由夹具61、62向TAB带和加强体加压，用粘接剂5 1把两者粘接起来。
然后，如图7所示，将半导体芯片72与TAB带74接合，用浇注封装树脂71封住半导体芯片72，在TAB带74的焊盘上加焊球75。图7示出这样形成的BGA带的剖面图。
但在图6所示TAB带与加强体热压接工序中，焊料保护层33的凹凸较大，上下夹具61、62的压力未加到焊料保护层中较大的凹部63，因此，压力未传递到凹部的63底部的粘接剂51上，如图8所示，发生粘接不够紧密的现象。
随后，在粘接体熟化工序或回流工序中加热的话，在那种粘接得不好的位置上就有气泡发生。图9为此阶段BGA带的剖面图。由于这种气泡91，导致BGA带弯曲，焊球部的平整性变差。
本发明鉴于上述问题，其目的在于使得加强体和TAB带整个面完全粘接，提高焊球平整性。
本发明包括：树脂带；设置在树脂带上的焊盘；由引线组成的铜箔图版；设置在铜箔图版相互间的伪(dummy)铜箔图版；以及全面覆盖铜箔图版、伪铜箔图版以及这些铜箔图版相互间的焊料保护层，以解决上文所述问题。
图1是本发明实施例剖面图。
图2是图1所示本发明的俯视图。
图3是现有TAB带的俯视图。
图4是图3所示TAB带的剖面图。
图5图示的是BGA带所用的加强体。
图6表示TAB带与加强体热压接的工艺。
图7是BGA带的剖面图。
图8是热压接后现有BGA带的剖面图。
图9是加热后现有BGA带的剖面图。
以下参照附图说明本发明的实施例。
图1示出本发明实施例的剖面图。图2示出图1实施例的俯视图。图1是图2中的1-1线的剖面图。该BGA带由聚酰亚胺15，涂覆在聚酰亚胺15上的粘接剂14，形成在粘接剂14上的焊盘11、引线12组成的金属(例如铜箔)的图版，伪铜箔图版10，覆盖这些铜箔图版10、11、12的焊料保护层13，以及通过粘接剂16与聚酰亚胺15的底面压接的金属板17所构成。
如图1、图2所示，本实施例在位于焊盘11和引线12相互之间较宽的空档中设有伪图版10。这种伪图版10一般与焊盘11、引线12同时形成，有时象伪图版10a那样单独配置，有时象伪图版10b那样与焊盘11连接配置，或与地线连接配置。
在本实施例中设置伪图版10，并使粘接剂14直接露出的部分为最小，再涂覆焊料保护层13，因而可以减小铜箔图版11、12上涂覆的焊料保护层13的上表面与直接涂覆在粘接剂14上的焊料保护层13的上表面之间的高低落差。例如，使铜箔图版10、11、12的膜厚为18μm的话，就可以将高低落差抑制在大于3μm但小于18μm的范围内，更为精细时可抑制在7μm以内。
因此，向TAB带粘贴加强体时，就可以向粘接剂全面均匀加压，从而在整体上提高密接性，使气泡不发生。
而且，如果将伪图版同其他引线、焊盘连接，则可增加粘接剂14与这些铜箔图版的粘接面积，因而铜箔与TAB带15的密接强度增加。
此外，将焊盘间配置的伪图版与地线连接便可以减小相邻焊盘间的感抗。
上述实施例是就TAB带为三层结构的情况加以说明的，但不限于此，即便是由树脂带与铜箔图版组成的两层结构也行。另外，上述实施例中，图版和伪图版都是铜箔的，但并不限于铜箔。
按照本发明，通过设置伪金属图版，粘贴TAB带与加强体时，在粘接剂的整个面上加压力，因而粘接剂与TAB带没有粘接不够紧密的地方。
而且，通过使伪金属图版与焊盘连接，该图版与粘接剂的粘接面积便可增加，因而可以使焊盘与粘接剂的密接强度增加。
此外，通过使伪图版与地线连接可减小相邻插脚间的感抗。

Claims (7)

1.一种半导体装置，为由树脂带；设置在所述树脂带上的焊盘和引线构成的铜箔图版；和全面覆盖所述铜箔图版和所述铜箔图版相互间的焊料保护层所组成的带状BGA封装用TAB带，其特征在于，还包括：配置在所述铜箔图版相互间，并为所述焊料保护层所覆盖，减小所述焊料保护层的高低落差的伪铜箔图版。
2.如权利要求1所述的半导体装置，其特征在于，所述铜箔图版厚度与所述铜箔图版上涂覆的焊料保护层的厚度之和，比所述铜箔图版相互之间涂覆的焊料保护层厚度要厚3μm以上但不到18μm。
3.如权利要求1所述的半导体装置，其特征在于，所述伪铜箔图版与作为所述焊盘或引线的铜箔图版连接。
4.如权利要求1所述的半导体装置，其特征在于，所述伪铜箔图版接地。
5.一种半导体装置，其特征在于包括：
由树脂带；设置在所述树脂带上的焊盘和引线构成的第一铜箔图版；以及全面覆盖所述铜箔图版和所述铜箔图版相互间的焊料保护层所组成的带状BGA封装用TAB带，
粘接于所述树脂带底部的加强体，
配置在所述铜箔图版相互间，并为所述焊料保护层所覆盖，压接所述TAB带和所述加强体时在所述加强体上均匀加压力的第二铜箔图版。
6.如权利要求1所述的半导体装置，其特征在于，所述树脂带与所述铜箔图版之间涂覆有粘接剂。
7.如权利要求5所述的半导体装置，其特征在于，所述树脂带与所述铜箔图版之间涂覆有粘接剂。
CN97113834A 1996-06-20 1997-06-20 半导体器件 Expired - Fee Related CN1087102C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP159686/96 1996-06-20
JP15968696A JP3346985B2 (ja) 1996-06-20 1996-06-20 半導体装置

Publications (2)

Publication Number Publication Date
CN1170234A true CN1170234A (zh) 1998-01-14
CN1087102C CN1087102C (zh) 2002-07-03

Family

ID=15699111

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97113834A Expired - Fee Related CN1087102C (zh) 1996-06-20 1997-06-20 半导体器件

Country Status (7)

Country Link
US (1) US5892277A (zh)
EP (1) EP0814510B1 (zh)
JP (1) JP3346985B2 (zh)
KR (1) KR100253872B1 (zh)
CN (1) CN1087102C (zh)
DE (1) DE69736157T2 (zh)
TW (1) TW460996B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3638778B2 (ja) * 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
US6194313B1 (en) * 1997-04-30 2001-02-27 Texas Instruments Incorporated Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process
JP4307664B2 (ja) * 1999-12-03 2009-08-05 株式会社ルネサステクノロジ 半導体装置
TW469552B (en) * 1999-12-10 2001-12-21 Toshiba Corp TAB type semiconductor device
US6501170B1 (en) 2000-06-09 2002-12-31 Micron Technology, Inc. Substrates and assemblies including pre-applied adhesion promoter
US6555910B1 (en) * 2000-08-29 2003-04-29 Agere Systems Inc. Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof
KR100378185B1 (ko) * 2000-10-16 2003-03-29 삼성전자주식회사 테스트용 탭을 구비하는 마이크로 비지에이 패키지 테이프
JP4626919B2 (ja) * 2001-03-27 2011-02-09 ルネサスエレクトロニクス株式会社 半導体装置
US6528417B1 (en) * 2001-09-17 2003-03-04 Taiwan Semiconductor Manufacturing Company Metal patterned structure for SiN surface adhesion enhancement
JP3914732B2 (ja) * 2001-10-02 2007-05-16 鹿児島日本電気株式会社 回路基板の接続構造及び該接続構造を備えた液晶表示装置並びに液晶表示装置の実装方法
JP2009527121A (ja) * 2006-02-15 2009-07-23 エヌエックスピー ビー ヴィ 半導体パッケージの製造方法、パッケージ基板、および集積回路（ｉｃ）デバイス
TWI474458B (zh) * 2012-03-23 2015-02-21 Chipmos Technologies Inc 半導體封裝基板
US9508637B2 (en) 2014-01-06 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9418928B2 (en) 2014-01-06 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9275967B2 (en) * 2014-01-06 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9305890B2 (en) 2014-01-15 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
KR102214512B1 (ko) * 2014-07-04 2021-02-09 삼성전자 주식회사 인쇄회로기판 및 이를 이용한 반도체 패키지

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162896A (en) * 1987-06-02 1992-11-10 Kabushiki Kaisha Toshiba IC package for high-speed semiconductor integrated circuit device
US4916514A (en) * 1988-05-31 1990-04-10 Unisys Corporation Integrated circuit employing dummy conductors for planarity
JP2864705B2 (ja) * 1990-09-21 1999-03-08 セイコーエプソン株式会社 Ｔａｂ用フイルムキャリアテープ及びそのリードへのはんだ被覆方法
JPH081917B2 (ja) * 1991-01-22 1996-01-10 株式会社東芝 フィルムキャリアテ−プ
JP3197291B2 (ja) * 1991-04-30 2001-08-13 株式会社リコー Ｔａｂ実装体
US5289032A (en) * 1991-08-16 1994-02-22 Motorola, Inc. Tape automated bonding(tab)semiconductor device and method for making the same
US5441915A (en) * 1992-09-01 1995-08-15 Taiwan Semiconductor Manufacturing Company Ltd. Process of fabrication planarized metallurgy structure for a semiconductor device
JPH088295A (ja) * 1994-06-20 1996-01-12 Toshiba Corp 半導体実装装置およびその製造方法

Also Published As

Publication number Publication date
DE69736157T2 (de) 2007-05-03
KR100253872B1 (ko) 2000-04-15
EP0814510B1 (en) 2006-06-21
US5892277A (en) 1999-04-06
JPH1012676A (ja) 1998-01-16
EP0814510A2 (en) 1997-12-29
TW460996B (en) 2001-10-21
JP3346985B2 (ja) 2002-11-18
KR980005944A (ko) 1998-03-30
EP0814510A3 (en) 1999-04-21
CN1087102C (zh) 2002-07-03
DE69736157D1 (de) 2006-08-03

Similar Documents

Publication Publication Date Title
CN1087102C (zh) 半导体器件
CN1086059C (zh) 叠层型半导体芯片封装
KR950012658B1 (ko) 반도체 칩 실장방법 및 기판 구조체
KR100470897B1 (ko) 듀얼 다이 패키지 제조 방법
TWI479637B (zh) 半導體裝置及其製造方法
JPH0394459A (ja) 半導体装置およびその製造方法
DE102010000407B4 (de) Halbleiter-Package mit einem aus Metallschichten bestehenden Band und Verfahren zum Herstellen eines derartigen Halbleiter-Package
CN1153997A (zh) 改进的减小尺寸的集成芯片封装
KR20050119414A (ko) 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법
JP2003078105A (ja) スタックチップモジュール
US8169089B2 (en) Semiconductor device including semiconductor chip and sealing material
CN101853835B (zh) 倒装芯片封装的制造方法
CN100514612C (zh) 半导体封装用印刷电路板的窗口加工方法
CN111081564A (zh) 一种叠层芯片封装结构及其制造方法
US6107118A (en) Chip-contacting method requiring no contact bumps, and electronic circuit produced in this way
KR100617071B1 (ko) 적층형 반도체 패키지 및 그 제조방법
US6137166A (en) Semiconductor device
CN203325892U (zh) 一种晶圆颗粒
CN102556938B (zh) 芯片叠层封装结构及其制造方法
JPH03123067A (ja) リードフレーム及び半導体装置
CN101651106B (zh) 堆叠芯片封装结构的制造方法
JP4288026B2 (ja) 装着ツール及びｉｃチップの装着方法
JPH07326710A (ja) 半導体実装構造
JPH06338539A (ja) 半導体素子の接続方法
JP2000174442A (ja) 電子部品の実装方法、及び半導体装置

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1037755

Country of ref document: HK

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20020703

Termination date: 20110620