TWI479637B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI479637B TWI479637B TW097126595A TW97126595A TWI479637B TW I479637 B TWI479637 B TW I479637B TW 097126595 A TW097126595 A TW 097126595A TW 97126595 A TW97126595 A TW 97126595A TW I479637 B TWI479637 B TW I479637B
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- Prior art keywords
- semiconductor
- electrode
- tapered surface
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- semiconductor elements
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- 239000004065 semiconductor Substances 0.000 title claims description 237
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 54
- 239000002184 metal Substances 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 35
- 238000005520 cutting process Methods 0.000 claims description 21
- 239000002245 particle Substances 0.000 claims description 16
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 66
- 239000010931 gold Substances 0.000 description 13
- 229910052737 gold Inorganic materials 0.000 description 13
- 238000000034 method Methods 0.000 description 12
- 238000001179 sorption measurement Methods 0.000 description 11
- 239000011888 foil Substances 0.000 description 10
- 239000012790 adhesive layer Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000007790 scraping Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Description
本揭露係有關於一種半導體裝置及其製造方法。更特別地,本揭露係有關於一種半導體裝置,其中在一電路基板之一表面上堆疊複數個四邊形之半導體元件,及亦形成一用以電性連接於該等半導體元件之各個電極與一在該電路基板上所形成之焊墊間之側面佈線,以及係有關於該半導體裝置之一種製造方法。
隨著最近半導體裝置之容量及密度之成長,已藉由如圖11所示之一半導體裝置所述以三度空間配置半導體元件100,100以達成密度成長。在如圖11所示之半導體裝置,藉由黏著層104,104在一佈線基板102之一表面上堆疊該等半導體元件100,100。以金線106,106,…實施該佈線基板102之焊墊與在該等半導體元件100,100各周緣的附近所配置之電極端間的線結合,因而使該等焊墊電性連接至該等電極端。
然而,如圖11所示,藉由線結合使該佈線基板102之焊墊電性連接至在該等半導體元件100,100各周緣的附近中所配置之電極端。因此,造成必需以樹脂密封該等金線106,106,…以便保護該等金線106,106,…因而最後所獲得之半導體裝置變得較大。
結果,為了最小化以三度空間配置多個半導體元件之半導體裝置,已在以下專利參考資料1中提出圖12所示之
一半導體裝置200。
在圖12所示之半導體裝置200中,在一佈線基板202之一表面上所堆疊之複數個半導體元件204,204,…的側面上形成側面佈線206,206。該等側面佈線206,206係電性連接該佈線基板202之焊墊至每一半導體元件204,204,…之電極端。
[專利參考資料1]日本專利申請案公告第2002-76167號。
相較於圖11所示之半導體裝置,依據圖12所示之半導體裝置200可達成小型化。
然而,當該等半導體元件204,204,…構成圖12所示之半導體裝置200時,必需使用在側面上形成該電極端的半導體元件且無法使用在一表面上形成電極端的標準半導體元件。
再者,使用一剝離法及一氣相沉積法在該電路基板202之一表面上堆疊該等半導體元件204,204,…後,在該等半導體元件204,204,…之側面上形成圖12所示之半導體裝置200的側面佈線206,206,…。因此,使該半導體裝置200之製造步驟產生麻煩。
另外,當使用在該一表面上形成電極端之半導體元件做為該等半導體元件204,204,…時,必需使一重新佈線延伸至該半導體元件之側面,其中該重新佈線之一端連接至該電極端。因此,使該半導體裝置200之製造步驟更為麻煩。
並且,顯示出甚至當一金線(該金線之一端連接至一半導體元件之一電極端)企圖沿著該側面延伸以取代該重新佈線時,會在該半導體元件之邊緣處切斷該金線。這可能是因為應力傾向於集中該金線之對應於該半導體元件之邊緣的部分。
因此,在堆疊複數個半導體元件之相關技藝半導體裝置中,無法使用在一表面上形成一電極端之標準半導體元件,且該半導體裝置之製造步驟係複雜化。
本發明之示範性具體例提供一種半導體裝置,其能防止該半導體裝置之製造步驟的複雜化及使用一在其一表面上形成一電極端之標準半導體元件,以及提供該半導體裝置之一種製造方法。
本發明人等發現可輕易地形成一使用一標準化半導體元件之半導體裝置及可藉由以下結構而小型化該所獲得之半導體裝置。亦即,使用一在其一表面上形成一電極端之標準四邊形之半導體元件以做為一半導體元件。藉由在沿著該半導體元件之每一側所形成之邊緣中切除一形成有該電極端之表面(稱為一電極端形成表面)的一邊緣以形成一錐面。一金屬線在它的一端連接至該電極端及沿著該半導體元件之錐面延伸。在一電路基板之一表面上堆疊這樣複數個半導體元件。藉由塗抹一含金屬粒子之導電膠以形成一用以電性連接於該等半導體元件之每一電極端與一在該電路基板上所形成之焊墊間之側面佈線,以便與
各金屬線的至少一部分接觸。
亦即,本發明之一示範性具體例係一種半導體裝置,其包括:一電路基板;複數個四邊形之半導體元件堆疊在該電路基板上,各半導體元件具有一電極端,各半導體元件具有一藉由在沿著該半導體元件之每一側所形成之邊緣中切除一上面形成有該電極端之電極端形成表面的至少一邊緣所形成之錐面;一側面佈線,電性連接於該等半導體元件之各電極端與一在該電路基板上所形成之焊墊間;以及金屬線,其各由其之一端連接至該等半導體元件之各電極端及沿著每一半導體元件之錐面延伸,其中沿著該錐面從該等半導體元件之各電極端所延伸之該金屬線的至少一部分與該側面佈線接觸及電性連接至該側面佈線。
並且,本發明之一示範性具體例係一種半導體裝置之製造方法,其包括:準備複數個四邊形之半導體元件,各半導體元件具有一電極端,各半導體元件具有一藉由在沿著該半導體元件之每一側所形成之邊緣中切除一上面形成有該電極端之電極端形成表面的至少一邊緣所形成之錐面;連接每一金屬線之一端至該等半導體元件之各電極端及沿著各半導體元件的錐面延伸每一金屬線;堆疊該等半導體元件於一電路基板上;以及
形成一側面佈線,該側面佈線與沿著該錐面從該等半導體元件之各電極端所延伸之該金屬線的至少一部分接觸,以便電性連接於該等半導體元件之各電極端與一在該電路基板上所形成之焊墊間。
在本發明之這樣的示範性具體例中,可藉由使該金屬線在該半導體元件之一側面延伸越過該半導體元件之錐面以改善該金屬線與該側面佈線間之接合。
並且,該半導體元件可以具有藉由切除該電極端形成表面之該邊緣所形成之該錐面及具有一藉由切除一相對於該電極端形成表面之表面的一邊緣所形成之錐面。在複數個堆疊半導體元件之側面上所塗佈之該導電膠進入該等相鄰半導體元件間之間隙及係提供於該錐面上。因此,可改善一金線與側面佈線間之接觸。特別地,可藉由延伸該金屬線至該兩個錐面以進一步改善該金屬線與該側面佈線間之接合。
在依據本發明之半導體裝置中,該金屬線之至少一部分與藉由塗佈該含金屬粒子之導電膠所形成之側面佈線接觸,其中該金屬線之一端連接至該電極端及該金屬線沿著藉由切割上面形成有該半導體元件之電極端的電極端形成表面之一邊緣所形成之錐面延伸。
因此,在依據本發明之半導體裝置中,該金屬線沿著該半導體元件之錐面延伸,其中該金屬線之一端連接至該半導體元件之電極端,以便可使用一標準半導體元件,其中該電極端係形成於該半導體元件之該表面上。
又,在依據本發明之半導體裝置,藉由塗抹該含導電粒子之導電膠以形成該側面佈線,以便相較於一使用一氣相沉積法及一剝離法形成該側面佈線之相關技藝半導體裝置,可輕易地形成它的側面佈線。
因此,在使該金屬線與該導電膠間接觸之情況中,該金屬線與該導電膠間之可濕性係良好的,以致於該導電膠傾向於集中在該對應金屬線之周圍表面上及可防止該導電膠與該相鄰側面佈線接觸。因而,可改善該最後獲得半導體裝置之可靠性。
此外,在該複數個堆疊半導體元件之側面上所塗抹之導電膠的一部分會輕易地進入該等相鄰半導體元件間之間隙及係形成於該錐面上,以及因此,與一沿著該錐面延伸之金屬線接觸。結果,可確實使該金屬線與該側面佈線接觸,其中該金屬線之一端連接至該半導體元件之電極端,因而可進一步改善該半導體裝置之可靠性。
圖1A及1B顯示依據本發明之一半導體裝置的一實施例。圖1A係一半導體裝置10之示意剖面圖,以及圖1B係該半導體裝置10之示意平面圖。在圖1所示之半導體裝置10中,經由黏著層14,14在一電路基板12之一表面上堆疊半導體元件16,16。
各該半導體元件16,16係一四邊形之半導體元件,其中在該半導體元件之一表面(稱為電極端形成表面)上形成電極端18,18,…。藉由在沿著此半導體元件16之每一側
所形成之邊緣中切除上面形成有該等電極端18,18,…之電極端形成表面的一邊緣以形成一錐面20。在此具體例中,藉由在該電極端形成表面之邊緣中切除較靠近該等電極端18,18,…之邊緣以形成該錐面20。
再者,做為一金屬線之金線22在其一端連接至該電極端18及沿著該半導體元件16之錐面20延伸。
沿著該錐面20延伸之金線22與一側面佈線24接觸。藉由塗抹一含導電粒子(例如,銀粒子、銅粒子或碳粒子)之導電膠至在該電路基板12之該表面上所堆疊之半導體元件16,16的側面以形成該側面佈線24。該側面佈線24亦與在該電路基板12之該表面上所形成之一焊墊26接觸。
在如圖1A所示之複數個堆疊半導體元件16,16的側面上所形成之側面佈線24的一部分進入該等相鄰半導體元件16,16間之間隙及係形成於該錐面20上,以便它與沿著該錐面20所延伸之金線22接觸。結果,可確實使該金線22與該側面佈線24接觸,其中該金線22之一端連接至該等半導體元件16,16之各個電極端18。
如下製造在圖1所示之半導體裝置10中所使用之具有錐面20的半導體元件16。亦即,在切割一製造有多個半導體元件之晶圓30的情況中,使用一如圖2A所示之用於斜割之刀片32在該晶圓30中進行斜割,因而在如圖2B所示之晶圓30的一表面中形成一V-形槽33。該晶圓30之形成有該V-形槽33的表面係該電極端形成表面,其中
在該電極端形成表面上形成該等半導體元件16之電極端18,18,…。
然後,以一切割刀片切割在一垂直於該晶圓30之該表面且通過圖2B所示之V-形槽33的最深部之直線(虛線34所示)上的部分。因此,可獲得該半導體元件16,其中在該表面之邊緣上形成該錐面20。
在該表面上形成有該等電極端18,18,…之四邊形的半導體元件16中,使該金線22沿著圖3A至3D所示之錐面20延伸,其中該金線22之一端連接至該電極端18。
使用一焊線機進行金線22至該半導體元件16之電極端18的連接及該金線22之延伸。
首先,如圖3A所示,在以一噴燈熔化從該焊線機之一焊針40的頂部所拉出之金線22的頂部及形成一焊球22a後,使該焊球22a捲曲在該電極端18上。
再者,在朝相反於該錐面20之方向移動該焊針40及從該焊針40拉出一預定長度後,如圖3B所示該焊針40開始朝該錐面20之方向移動。
隨後,當如圖3C所示沿著該錐面20從該錐面之一邊緣側朝另一邊緣側之方向移動該焊針40及使該金線22之另一端(該金線22之一端連接至該電極端18)延伸至該錐面20的另一邊緣時,如圖3D所示以該焊針40扯斷該金線22。
然後,如圖4所示,以該等黏著層14,14在該電路基板12之該表面上(上面形成有該焊墊26之表面)堆疊該等半
導體元件16,16,其中該等金線22(該等金線22之一端連接至在該電極端形成表面上所形成之電極端18)沿著該等錐面20延伸。在此情況中,在該電路基板12上所直接安裝之該半導體元件16的電極端形成表面變成一要黏著另一半導體元件16之黏著表面。在該半導體元件16上所堆疊之另一半導體元件16的電極端形成表面變成一暴露表面。
如圖4所示,在此方式中將一含導電粒子(例如,銀粒子、銅粒子或碳粒子)之導電膠25塗抹至在該電路基板12之該表面上所堆疊之半導體元件16,16的側面。藉由以來自一構成一塗抹器42之填充有該導電膠之填充路徑42b的氣體壓力(例如,氮氣壓力)從一噴嘴42a排放至該等堆疊半導體元件16,16之側面的方式來塗抹此導電膠25。在此情況中,可藉由從該等堆疊半導體元件16,16之下部移動該塗抹器42至上部(如圖4所示之箭頭的方向)以條狀在該等半導體元件16,16之側面上形成該導電膠25。此條狀導電膠25之一端與該電路基板12之焊墊26接觸。
再者,該導電膠25可輕易地進入該等相鄰半導體元件16,16間之間隙,以及因此,在該錐面20上提供該導電膠25之一部分。因此,該導電膠25與沿著該錐面20延伸之金線22接觸。
然後,將該電路基板及該等半導體元件16,16插入一加熱爐及將其熱處理。因此,可在該等半導體元件16,16之
側面上形成該側面佈線24及可使該金線22藉由該側面佈線24電性連接至該電路基板12之焊墊26,其中該金線22之一端連接至該等半導體元件16,16之各個電極端18。
在此,該金線22與該導電膠25間之可濕性係良好的。因此,該導電膠25傾向於集中在該對應金線22之周圍表面上及可防止該導電膠25與被塗抹至相鄰金線22之導電膠接觸。因而,可改善對該導電膠25之半導體元件16,16的電性連接之可靠性。
在圖1A至4所示之半導體裝置10中,使該金線22之另一端沿著該錐面20延伸,其中該金線22之一端連接至該半導體元件16之電極端18。然而,如圖5所示,可以使該金線22之另一端沿著該側面延伸越過該金線22之錐面20。
在此情況中,如圖3D所示,使用該焊線機之焊針40延伸該金線22,其中該金線22之一端連接至該半導體元件16之電極端18。在此情況中,可以在該半導體元件16之側面的中間扯斷該金線22,然而如圖5所示,可以使用該半導體元件16之下表面(相對於該電極端之表面)的邊緣扯斷該金線22。
在此,可藉由事先以夾鉗(clamp)等刮掉該金線22之預定位置以輕易地在一預定位置扯斷該金線22。
在圖1A至5所示之半導體裝置10中,使用一在該電極端形成表面之邊緣上形成有該錐面20之半導體元件做為該半導體元件16。然而,如圖6所示,可使用一半導體
件16,其中切除該電極端形成表面之邊緣及相對於該電極端形成表面之表面的邊緣之每一邊緣,以形成錐面20,20。
在使用圖6所示之這樣的半導體元件16之情況中,延伸該金線22(該金線22之一端連接至該電極端18),以便越過該等錐面20,20。因此,在該電路基板12之該表面上所堆疊之半導體元件16,16的側面上所形成之側面佈線24的一部分進入該等相鄰半導體元件16,16間之間隙及係形成於該等錐面20,20上,因而,可進一步改善該側面佈線24與該金線22間之接觸。
如下面製造圖6所示之半導體元件16,其中在該電極端形成表面之邊緣及相對於該電極端形成表面之表面的邊緣之每一邊緣上形成該等錐面20,20。亦即,如圖7A所示,在切割一製造有多個半導體元件之晶圓30的情況中,使用一用於斜割之刀片32進行斜割,因而在該晶圓30之該表面中形成一V-形槽33。
再者,如圖7B所示,藉由使用該用於斜割之刀片32,在該晶圓30之另一表面的對應於該表面中所形成之V-形槽33的位置中形成一V-形槽33。
然後,藉由以一切割刀片切割在該晶圓30之兩個表面側中所形成之V-形槽33,可形成該半導體元件16,其中在該電極端形成表面之邊緣及相對於該電極端形成表面之表面的邊緣之每一邊緣形成該等錐面20,20。
在延伸該金線22(該金線22之一端連接至該電極端18)以便越過在該半導體元件16中所形成之錐面20,20的情
況中,圖8及9A至9C所示之方法係容易的。
首先,如圖8所示,在一吸附板50上放置金屬箔(例如,鋁箔)及亦在該金屬箔52中所形成之一通孔54上放置該半導體元件16。放置在該金屬箔52上所放置之半導體元件16,以便上面形成有該半導體元件之電極端18的電極端形成表面係面向上。
藉由該吸附板50之逐漸產生的吸附力分別將這樣的金屬箔52及半導體元件16吸附及固定在該吸附板50之預定位置中。在此情況中,將該半導體元件16經由該金屬箔52之通孔54吸附及固定在該吸附板50之預定位置中。
在此方式中,在藉由一焊線機使該金線22之一端連接至以該吸附板50之吸附力所固定之金屬箔52的半導體元件16之近處後,從焊針40拉出該金線22以及將該金線22之另一端連接至該半導體元件16之電極端18及扯斷。
接下來,如圖9A所示,釋放該吸附板50之吸附及從該吸附板50取出該半導體元件16及該金屬箔52。當釋放該吸附板50之吸附時,可移動該半導體元件16。
結果,如圖9B所示,朝該金線22之方向(圖9B之箭頭的方向)移動該半導體元件16及使該半導體元件16之側面鄰近該金線22,以便該金線22越過該半導體元件16之錐面20,20。
之後,如圖9C所示,折疊該金屬箔52之一部分及暴露沿著相對於該半導體元件16之電極端形成表面的表面延伸之金線22。以一切割機等切割延伸越過在相對於該電
極端形成表面之表面中所形成之錐面20的金線22之部分(圖9C之箭頭所示之部分)。因此,可獲得該半導體元件16,其中使該金線22(其一端連接至該電極端18)延伸,以越過該等錐面20。
如圖4所示,以該等黏著層14,14在該電路基板12之該表面上堆疊在此方式中所形成之複數個半導體元件,其中該等金線22(其一端連接至該等電極端18)延伸,以越過在該電極端形成表面及它的相對表面之邊緣的每一邊緣中所形成之錐面20,20。然後,使用該塗抹器42將含導電粒子(例如,銀粒子、銅粒子或碳粒子)之導電膠25塗抹至該等半導體元件之側面。之後,可形成圖6所示之側面佈線24。
在圖6至9C所示之半導體元件16中,使該金線22(其一端連接至該電極端18)延伸以越過兩個錐面20,20及沿著相對於該電極端形成表面之表面延伸。然而,可以使該金線22沿著該側面之中間或下端延伸越過該電極端形成表面之錐面20(在此情況中,該金線22沒有沿著相對於該電極端形成表面之表面的錐面20延伸)。
並且,該半導體裝置可以是一具有一半導體元件16之半導體裝置,其中如圖10所示,只在該電極形成表面中形成一錐面20及使一金線22(其一端連接至該半導體元件16之一電極端18)沿著相對於該電極形成表面之表面延伸,以便越過該錐面20。
在圖10所示之半導體裝置中,該側面佈線24之一部分
進入該等相鄰半導體元件16,16之間隙及係形成於該錐面20上及越過該錐面20之金線22與該側面佈線24接觸,因而可確實達成該金線22與該側面佈線24間之連接。
如在構成圖6及10所示之半導體裝置的半導體元件16中所述,當使該金屬線22(其一端連接至該半導體元件16之電極端18)沿著相對於上面形成有該電極端18之電極端形成表面的表面延伸時,可以如圖3A所示使用該打線機之焊針40延伸該金屬線22。在此情況中,可藉由以一夾鉗等事先刮掉該金線22(該金線22之一端連接至該半導體元件16之電極端18)之一預定切割位置以在該切割位置輕易地扯斷該金線22。
又,在圖1A及10所示之半導體裝置中,堆疊該等半導體元件,以便該等半導體元件16,16之電極端形成表面係朝相同方向,然而,可以堆疊該等半導體元件16,16,以便該等電極端形成表面彼此相對。
10‧‧‧半導體裝置
12‧‧‧電路基板
14‧‧‧黏著層
16‧‧‧半導體元件
18‧‧‧電極端
20‧‧‧錐面
22‧‧‧金屬線;金線
22a‧‧‧焊球
24‧‧‧側面佈線
25‧‧‧導電膠
26‧‧‧焊墊
30‧‧‧晶圓
32‧‧‧刀片
33‧‧‧V-形槽
34‧‧‧虛線
40‧‧‧焊針
42‧‧‧塗抹器
42a‧‧‧噴嘴
42b‧‧‧填充路徑
50‧‧‧吸附板
52‧‧‧金屬箔
54‧‧‧通孔
100‧‧‧半導體元件
102‧‧‧佈線基板
104‧‧‧黏著層
106‧‧‧金線
200‧‧‧半導體裝置
202‧‧‧佈線基板
204‧‧‧半導體元件
206‧‧‧側面佈線
圖1A係說明依據本發明之一半導體裝置的一實施例之示意剖面圖。
圖1B係說明依據本發明之一半導體裝置的一實施例之示意平面圖。
圖2A至2C係說明一用以形成一構成圖1A所示之半導體裝置的半導體元件之一錐面的方法之程序圖。
圖3A至3D係說明一用以延伸一金屬線至一錐面之方法的程序圖,其中該金屬線之一端連接至該構成圖1A所示
之半導體裝置的半導體元件之一電極端。
圖4係說明一用以在一電路基板之一表面側上所堆疊之複數個半導體元件的側面上形成側面佈線之形成方法的說明圖。
圖5係說明依據本發明在一半導體裝置中所使用之一半導體元件的另一實施例之剖面圖。
圖6係說明依據本發明之一半導體裝置的另一實施例之示意剖面圖。
圖7A及7B係說明一用以形成一構成圖6所示之半導體裝置的半導體元件之一錐面的方法之程序圖。
圖8係說明一用以延伸一金屬線至兩個錐面之方法的第一步驟之程序圖的一部分,其中該金屬線之一端連接至該構成圖6所示之半導體裝置的半導體元件之一電極端。
圖9A至9C係說明用以延伸一金屬線至該兩個錐面之方法的其它步驟之程序圖,其中該金屬線之一端連接至該構成圖6所示之半導體裝置的半導體元件之電極端。
圖10係說明依據本發明之一半導體裝置的另一實施例之示意剖面圖。
圖11係說明一相關技藝半導體裝置之示意圖。
圖12係說明一改良半導體裝置之立體圖。
10‧‧‧半導體裝置
12‧‧‧電路基板
14‧‧‧黏著層
16‧‧‧半導體元件
18‧‧‧電極端
20‧‧‧錐面
22‧‧‧金屬線;金線
24‧‧‧側面佈線
26‧‧‧焊墊
Claims (7)
- 一種半導體裝置,包括:一電路基板;複數個四邊形之半導體元件,其分別具有形成有電極端之電極端形成面、側面及上述電極端形成面與上述側面之間的錐面,並且堆疊在該電路基板上,上述錐面係藉由將上述電極端形成表面之邊緣切除而形成,上述錐面與相對於上述側面之上述電路基板之傾斜相異;一側面佈線,其設於各上述錐面及各上述側面,並且電性連接於該等半導體元件之各個電極端與一在該電路基板上所形成之焊墊間;以及金屬線,其各由其之一端連接至該等半導體元件之各個電極端及沿著每一半導體元件之錐面延伸,而藉由線結合而形成,其中,沿著該錐面從該等半導體元件之各個電極端所延伸之該金屬線的至少一部分係與該側面佈線接觸及電性連接至該側面佈線,該側面佈線係由一含導電粒子之導電膠所形成,上述導電膠係進入於由該半導體元件之錐面與鄰接之半導體元件所形成的間隙而與上述金屬線接觸,該金屬線係沿著該半導體元件之一側面延伸越過該半導體元件之錐面。
- 如申請專利範圍第1項之半導體裝置,其中,該半導體元件具有藉由切除該電極端形成表面之該邊緣所形成 之該錐面,及具有一藉由切除相對於該電極端形成表面之表面的一邊緣所形成之錐面。
- 如申請專利範圍第2項之半導體裝置,其中,該金屬線係沿著該兩個錐面延伸。
- 一種半導體裝置之製造方法,包括以下步驟:準備複數個四邊形之半導體元件,其分別具有形成有電極端之電極端形成面、側面及上述電極端形成面與上述側面之間的錐面,上述錐面係藉由將上述電極端形成表面之邊緣切除而形成;連接藉由線結合而形成之各金屬線之一端至該等半導體元件之各個電極端及沿著各個半導體元件的錐面延伸每一金屬線;堆疊該等半導體元件於一電路基板上;以及形成一側面佈線,該側面佈線與沿著該錐面從該等半導體元件之各個電極端所延伸之該金屬線的至少一部分接觸,以便電性連接於該等半導體元件之各個電極端與一在該電路基板上所形成之焊墊間,該側面佈線係設於各個該錐面及各個該側面;該側面佈線係由塗佈含導電粒子之導電膠於上述堆疊之半導體元件之側面而形成,上述導電膠係進入於由該半導體元件之錐面與鄰接之半導體元件所形成的間隙而與上述金屬線接觸,該金屬線係沿著該半導體元件之一側面延伸越過該半導體元件之錐面。
- 如申請專利範圍第4項之半導體裝置之製造方法,其中,使用之半導體元件之每一者係具有藉由切除該電極端形成表面之該邊緣所形成之該錐面,及具有一藉由切除相對於該電極端形成表面之表面的一邊緣所形成之錐面,以做為該等半導體元件。
- 如申請專利範圍第5項之半導體裝置之製造方法,其中,該金屬線係沿著該兩個錐面延伸。
- 一種半導體裝置,包括:一電路基板;複數個四邊形之半導體元件,其分別具有形成有電極端之電極端形成面、側面及上述電極端形成面與上述側面之間的錐面,並且堆疊在該電路基板上,上述錐面係藉由將上述電極端形成表面之邊緣切除而形成,上述錐面與相對於上述側面之上述電路基板之傾斜相異;一側面佈線,其設於各上述錐面及各上述側面,並且電性連接於該等半導體元件之各個電極端與一在該電路基板上所形成之焊墊間;以及金屬線,其各由其之一端連接至該等半導體元件之各個電極端及沿著每一半導體元件之錐面延伸,而藉由線結合而形成,其中,沿著該錐面從該等半導體元件之各個電極端所延伸之該金屬線的至少一部分係與該側面佈線接觸及電性連接至該側面佈線,該側面佈線係由塗佈含導電粒子之導電膠於上述堆疊 之半導體元件之側面而形成,上述導電膠係進入於由該半導體元件之錐面與鄰接之半導體元件所形成的間隙而與上述金屬線接觸。
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