CN101375382A - 半导体器件封装及其制造方法 - Google Patents
半导体器件封装及其制造方法 Download PDFInfo
- Publication number
- CN101375382A CN101375382A CNA2004800232766A CN200480023276A CN101375382A CN 101375382 A CN101375382 A CN 101375382A CN A2004800232766 A CNA2004800232766 A CN A2004800232766A CN 200480023276 A CN200480023276 A CN 200480023276A CN 101375382 A CN101375382 A CN 101375382A
- Authority
- CN
- China
- Prior art keywords
- bonding
- pad
- lead
- wire
- insertion portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims description 65
- 238000004519 manufacturing process Methods 0.000 title description 11
- 238000003780 insertion Methods 0.000 claims description 66
- 230000037431 insertion Effects 0.000 claims description 66
- 239000000206 moulding compound Substances 0.000 claims description 45
- LFOIDLOIBZFWDO-UHFFFAOYSA-N 2-methoxy-6-[6-methoxy-4-[(3-phenylmethoxyphenyl)methoxy]-1-benzofuran-2-yl]imidazo[2,1-b][1,3,4]thiadiazole Chemical compound N1=C2SC(OC)=NN2C=C1C(OC1=CC(OC)=C2)=CC1=C2OCC(C=1)=CC=CC=1OCC1=CC=CC=C1 LFOIDLOIBZFWDO-UHFFFAOYSA-N 0.000 claims description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 19
- 239000004411 aluminium Substances 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 15
- 239000002243 precursor Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims 1
- 238000000576 coating method Methods 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 description 56
- 238000005516 engineering process Methods 0.000 description 19
- 238000009413 insulation Methods 0.000 description 7
- 239000011247 coating layer Substances 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 238000003466 welding Methods 0.000 description 6
- 238000003486 chemical etching Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 238000000608 laser ablation Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 206010027439 Metal poisoning Diseases 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 229910000906 Bronze Inorganic materials 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000001746 injection moulding Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000007731 hot pressing Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- -1 billon Chemical compound 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000004441 surface measurement Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48455—Details of wedge bonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
- H01L2224/78302—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78313—Wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78313—Wedge
- H01L2224/78314—Shape
- H01L2224/78317—Shape of other portions
- H01L2224/78318—Shape of other portions inside the capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85053—Bonding environment
- H01L2224/85095—Temperature settings
- H01L2224/85099—Ambient temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85203—Thermocompression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
本发明描述了半导体器件(管芯)封装(50,102,110)的引脚框(52,100,112)。引脚框(52,100,112)中的每条引脚(60)包括插入部分(64),其一端(66)设置为靠近封装(50,102,110)的外面(58),另一端(68)设置为靠近管芯(14)。板连接支柱(70)和支撑支柱(74)从插入部分(64)的相对端延伸出。每条引脚(60)经由引线键合、载带键合被电连接到管芯(14)上的关联输入/输出(I/O)焊盘(80),或者倒装芯片附接到键合点(78)。在使用引线键合时,将I/O焊盘(80)电连接到键合点(78)的引线可以被楔形键合到I/O焊盘(80)和键合点(78)。支撑支柱(74)在键合和涂覆工艺期间提供对插入部分(64)的末端(68)的支撑(图3)。
Description
相关申请交叉引用
本申请要求2003年8月14日提交的美国临时申请No.60/494,982(律师案卷号102479-100)的优选权,该申请通过引用整体结合于此。
技术领域
本发明涉及半导体器件封装。更具体地说,本发明涉及基于引脚框的半导体器件封装,以及用于制造基于引脚框的半导体器件封装的方法。
背景技术
在基于引脚框的半导体器件封装中,电信号通过导电引脚框在至少一个半导体器件(管芯)和诸如印刷电路板之类的外部电路之间传输。引脚框包括多条引线,每条都具有内引线末端和相对的外引线末端。内引线末端被电连接到管芯上的输入/输出(I/O)焊盘,并且外引线末端提供封装主体外的端子。在外引线末端在封装主体的面上终止时,该封装被称作“无引脚”封装,而如果外引线延伸过封装主体的周界,则该封装被称作“有引线”封装。公知的无引脚封装的示例包括方形扁平无引脚(QFN)封装,这种封装沿正方形封装主体的底部的周界设置有四组引线;以及双列扁平无引脚(DFN)封装,这种封装沿封装主体的底部相对侧设置有两组引线。在共同拥有的已公开美国专利申请公开号US 2003/0203539 A1中公开了用于制造QFN封装的方法,该专利申请于2002年4月29日提交,并且通过引用整体结合于此。
管芯到内引线的末端的连接一般使用引线接合法、载带自动键合(TAB)法或者倒装芯片法连接。在引线接合或TAB法中,内引线末端距离管芯一定距离终止,并且通过细直径线或导电带被电连接到管芯顶上的I/O焊盘。管芯可由支撑焊盘支撑,支撑焊盘由引线围绕。在倒装芯片法中,引脚框的内引线末端在管芯下延伸,并且管芯被倒装,以使管芯上的I/O焊盘通过直接电连接(例如,焊接连接)接触内引线末端。
在应用引线键合的无引脚封装中,引线一般以两种通用配置之一形成。在第一配置中,如图1所示,每条引线10基本上由靠近封装侧面设置的支柱组成。支撑焊盘12一般设置在引线10之间,用于支撑管芯14。引线10和支撑焊盘12可以包括锁定结构,例如从引线10和支撑焊盘12伸出的突出(tab)16,其与模塑料(molding compound)协作来将引线10和支撑焊盘12保持在封装内。这种配置的一个缺点在于其需要相对较长的键合引线18来将管芯14上的I/O焊盘连接到引线10。使用较长的键合引线18增加了管芯14和引线10之间的电阻,从而对封装的性能造成负面影响。并且,键合引线18相对昂贵,并且易碎,因此,不期望使用大量键合引线18。由于对于小尺寸封装工业上趋向使用越来越小的芯片尺寸,这对于给定的封装尺寸增加了键合引线18的长度,所以加剧了该问题。
在引线键合无引脚封装的第二种一般配置中,如图2所示,引线10包括插入部分20,其从连接支柱的板朝支撑焊盘12延伸。插入部分20减少了所需键合引线18的长度,从而克服图1的配置的某些问题。然而,图2的配置自身也有问题,因为在将管芯键合到引线时难以维持插入部分20上的键合点的共面性。
应用倒装芯片键合法的无引脚封装一般使用类似于在图2中所示的配置,但是没有支撑焊盘12。插入部分20在管芯14下延伸,并且芯片被倒装以使管芯14上的I/O焊盘可以被焊接到插入部分20上的键合点。使用这种倒装芯片键合方法的配置也存在在将管芯14键合到引线10时维持插入部分20上的键合点的共面性的问题。
在使用引线键合的情形中,键合引线18一般使用三种引线键合技术之一被附接:超声波键合,热压键合和热声键合。
在热声键合中,压力和超声波振动突发的组合被施加来形成冶金冷焊点。超声波键合形成所谓的“楔形键合”。在楔形键合中,键合沿引线18的侧面发生,同时引线18一般平行于引线10的表面延伸,如图2中的19处所示。
在热压键合中,施加压力和上升的温度的组合以形成焊点。另一方面,热声键合使用压力和上升的温度的组合,并且超声波振动突发被施加来形成焊点。热压和热声键合技术一般在I/O焊盘处形成所谓的“球键合”,在引线10处形成楔形键合。在球键合中,键合发生在引线18的端点处,同时引线18一般在连接点处垂直于I/O焊盘的表面延伸,如图2中的21处所示。实际上所有热压和热声键合都使用金或金合金引线执行。
在现代封装技术中,互连的引脚框矩阵被用来允许同时制造多个封装。这些技术一般包括使用焊料、环氧树脂、双面胶带等将管芯14紧固到矩阵中的每个引脚框的中央支撑焊盘12。然后,每个引脚框的引线10被引线键合到关联的管芯14的I/O焊盘上。在引线键合后,管芯14、键合引线18、和引线10的至少一部分被使用例如转移造型或注入成型工艺封装到塑料中。然后这些封装被使用刀片、喷水装置等锯成单个,每个封装的引线10的剩余部分暴露来电连接到外部电路。
由于多种原因,在这种现代封装技术中使用超声波键合是有问题的。例如,在现代引脚框上形成的引线10非常薄,所以铝楔形键合工艺非常容易使其断裂。由于这种限制,使用铝楔形键合现在专用于单个的密封封装,这种封装提供了焊接键合支柱,并且在铝楔形键合工艺中,封装可以精确地旋转和定位。
发明内容
利用下述半导体器件封装,现有技术的上述和其他缺点和不足得到克服或减轻,所述半导体器件封装包括:模塑料形成第一封装面的至少一部分,半导体器件至少部分由模塑料覆盖,并且导电材料的引脚框至少部分由模塑料覆盖。引脚框包括多条引脚。每条所述引脚包括插入部分,该插入部分具有从该插入部分延伸出的板连接支柱和支撑支柱。板连接支柱和支撑柱都终止于第一封装面,并且该插入部分与第一封装面间隔开。在每条引脚中,键合点形成在插入部分的与支撑支柱相对的表面上。I/O焊盘中的至少一个在键合点处被电连接到插入部分。I/O焊盘可以被引线键合或载带键合到键合点,或者I/O焊盘可以被直接电连接到键合点,以形成倒装芯片型连接。
在一个实施例中,模塑料形成与第一封装面相邻的第二封装面的至少一部分,并且与板连接支柱的末端表面相邻的该板连接支柱的侧表面在第二封装面处可见。板连接支柱的侧表面与板连接支柱的末端表面之间的拐角可以被移除以形成缺口,该缺口从板连接支柱的末端表面测量具有在约1密耳到约2密耳之间的高度。
在本发明的另一个方面,一种用于封装半导体器件的方法包括:(a)用导电材料形成引脚框,引脚框包括多条引脚,每条引脚包括:插入部分,其具有相对的第一和第二末端;板连接支柱,其从靠近插入部分的第一末端延伸出,该板连接支柱具有远离插入部分的末端表面;支撑支柱,其与板连接支柱间隔开,并且从靠近插入部分的第二末端延伸出,该支撑支柱具有远离插入部分自由端;以及键合点,其形成在插入部分的与支撑支柱相对的表面上;(b)支撑支撑支柱和板连接支柱的自由端;(c)在支撑支撑支柱和板连接支柱的自由端的同时将半导体器件上的I/O焊盘电连接到键合点;(d)在支撑支撑支柱和板连接支柱的自由端的同时利用模塑料覆盖半导体器件的至少一部分以及引脚框的至少一部分。
将I/O焊盘电连接到键合点可以包括将I/O焊盘引线键合到键合点,或者将I/O焊盘直接电连接到键合点,以形成倒装芯片型连接。支撑支撑支柱和板连接支柱的自由端可以包括将支撑支柱和键合连接支柱的自由端粘到表面。在一个实施例中,形成引脚框包括:(a)用导电材料形成引脚框前体(precursor),引脚框前体包括多个引脚前体,每个引脚前体是导电材料条带;以及(b)设置跨过每个引脚前体的沟道来形成多条引脚。该方法还包括用树脂填充沟道。
在本发明的另一个方面中,半导体器件封装包括:模塑料,其形成第一封装面的至少一部分;半导体器件,其至少部分由模塑料覆盖;以及导电材料的引脚框,其至少部分由模塑料覆盖。引脚框包括多条引脚,每条引脚具有形成在其上的键合点。每个键合点由引线电连接到半导体器件上的对应的I/O焊盘,引线被楔形键合到I/O焊盘和键合点二者。引线可由铝或铝基合金制成,并且可以具有该引线在I/O焊盘和键合点之间延伸的部分的直径的约1.2到约1.5倍之间的楔形宽度。在一个实施例中,在模塑料被施加到引脚框后,引脚框被蚀刻以分离引脚。
在本发明的另一个方面中,一种用于封装半导体器件的方法包括:用导电材料形成引脚框,引脚框包括多条引脚;将半导体器件上的I/O焊盘电连接到引脚上的键合点;用模塑料覆盖半导体器件的至少一部分以及引脚框的至少一部分。将I/O盘电连接到键合点包括:将引线楔形键合到I/O焊盘,并且将引线楔形键合到键合点。引线可由铝或铝基合金制成,并且可以具有该引线在I/O焊盘和键合点之间延伸的部分的直径的约1.2到约1.5倍之间的楔形宽度。在一个实施例中,在模塑料被施加到引脚框后,引脚框被蚀刻以分离引脚。
在下面的附图和描述中,阐述了本发明的一个或多个实施例的细节。从描述和附图中,以及从权利要求书中将清楚本发明的其他特征、目的和优点。
附图说明
结合附图从下面的详细描述将更全面地理解本发明,其中相同的元素用相同的标号标注,在附图中:
图1是现有技术的引线键合的无引脚封装的一部分的截面图;
图2是现有技术的另一个引线键合的无引脚封装的一部分的截面图;
图3是根据本发明一个实施例的方形无引脚引线键合的半导体器件封装的截面图;
图4是图3的半导体器件的引脚框的立体底视图;
图5是引线键合到管芯的图4的引脚框的立体顶视图;
图6是图3的半导体器件封装的部分切除后的立体顶视图;
图7是图3的半导体器件封装的立体底视图;
图8是根据本发明另一个实施例的双列无引脚引线键合的半导体器件封装的引线键合到管芯的引脚框的立体顶视图;
图9是应用图8的引脚框的半导体器件封装的部分切除后的立体顶视图;
图10是图9的半导体器件封装的立体底视图;
图11是根据本发明另一个实施例的方形无引脚倒装芯片半导体器件封装的截面图;
图12是图11的半导体器件封装的引脚框的立体顶视图;
图13是根据本发明另一个实施例的键合到双列无引脚倒装芯片半导体器件封装的管芯的引脚框的立体顶视图;
图14a和图14b是替换引线配置的截面图;
图15a和图15b是另一替换引线配置的截面图;
图16是应用图14a的替换引线配置的引线键合的半导体器件封装的截面图;
图17是图16的半导体器件封装的引脚框的立体顶视图;
图18是图16的半导体器件封装的部分切除后的立体顶视图;
图19是图16的半导体器件封装的立体底视图;
图20是应用图14b的替换引线配置的倒装芯片半导体器件封装的截面图;
图21是图20的半导体器件封装的引脚框的立体顶视图;
图22是图20的半导体器件封装的部分切除后的立体顶视图;
图23是图20的半导体器件封装的立体底视图;
图24是示出了覆盖支撑支柱的自由端的电绝缘涂层的方形无引脚半导体器件封装的立体底视图;
图25是示出了覆盖支撑支柱的自由端的电绝缘涂层的双列无引脚半导体器件封装的立体底视图;
图26a~图26h示出了用于在封装的集成电路芯片封装中引线键合的楔形键合顺序;
图27是芯片的I/O焊盘上的楔形键合的立体立体图;
图28是引线的键合点上的楔形键合的立体立体图;
图29a~图29i示出了在组装的各个阶段的替换半导体器件封装
具体实施方式
参考图3,该图示出了方形无引脚引线键合的半导体器件封装50的截面图。半导体器件封装50包括半导体器件(管芯)14和由模塑料54覆盖的引脚框52,其形成封装50的部分外面56和58。引脚框52包括多个引脚60和设置在引脚60之间的管芯焊盘62。每条引脚60包括插入部分64,插入部分64一端66设置为靠近封装50的外面58,另一端68设置为靠近管芯14。板连接支柱70从每个插入部分64的靠近末端66延伸出,其具有终止在封装面56处的自由端72。支撑支柱74从每个插入部分64的靠近相反的末端68延伸出,其与板连接支柱70间隔开,并且具有终止在封装面56处的自由端76。每条引脚60包括形成在与支撑支柱74相反的插入部分64的表面上的键合点78。每条引脚60经由键合引线18被电连接到管芯14上的关联的输入/输出(I/O)焊盘80上,其中键合引线18连接在I/O焊盘80和键合点78之间。板连接支柱70的自由端72可以被电连接到外部电路,例如印刷电路板或另一个半导体器件封装。电信号经由I/O焊盘80、键合引线18、插入部分64和板连接支柱70在管芯14和外部电路之间传输。在下文中将更详细描述,支撑支柱74在键合和涂覆工艺期间对插入部分64的末端68提供支撑。另外,由插入部分64、支撑支柱74和板连接支柱70限定的沟道82容纳模塑料54,以帮助将每条引脚60锁定在封装50内。板连接支柱70也可以从插入部分64的末端66偏移,以使末端66充当突出,用于将引脚60锚定在模塑料54内。
参考图4,该图示出了引脚框52的立体底视图。在所示实施例中,在管芯支撑焊盘62的四侧每侧设置有七条引脚60。但是,应当意识到,对于具体应用,引脚60的数目和位置可以按需修改。引脚60彼此分离,并且与管芯支撑焊盘62分离开,以使引脚60彼此电绝缘并且与管芯支撑焊盘62电绝缘。每个插入部分64被成型为调整相邻引脚60之间的斜度。例如,每侧最中央的插入部分64基本上是直的,而每侧上最外的插入部分64是成一定角度成型的。
拉杆(tie bar)90从管芯焊盘62的每个拐角延伸出,其用来将管芯焊盘锚定到模塑料54内(图3)。
引脚框52可由任何适当的导电材料片形成,优选是铜或者铜基合金(copper base alloy)。所谓铜基合金是指包含在重量上超过50%的铜。形成引脚框52的导电材料片优选具有约0.10mm到约0.25mm之间的厚度,更优选地在约0.15mm到约0.20mm。引线焊盘的每个特征的前体,包括管芯支撑焊盘62、引脚60和拉杆90可以使用任何已知方法形成,例如冲压、化学蚀刻、激光切除等。在执行特征的每个中形成的各种凹进可以然后使用受控减少工艺形成,例如化学蚀刻或激光切除。例如,要形成支撑支柱74和板连接支柱70的自由端76、72的每个表面可以涂覆化学抗蚀剂,并且未涂覆的表面暴露给适当的蚀刻剂持续一定时间,有效地形成沟道82。同样的方法也可以用来使拉杆90从管芯支撑焊盘62的底面92凹进。沟道82优选被蚀刻跨过引线前体,到引脚框52的厚度(即,用来形成引线框的材料的厚度)的约40%到约75%之间的深度,更优选在该厚度的约50%到约60%之间。在该优选范围内的沟道深度提供了这样的插入部分64,该插入部分64具有足够的电导性,同时允许沟道82中的足够的余隙容纳模塑料54(图3)。
在各种凹进(例如,沟道82)已形成后,支撑支柱74和板连接支柱70的自由端76、72以及芯片支撑焊盘62的底面92被粘结到表面94。在所示实施例中,表面94形成在胶带上,其使得在支撑支柱74和板连接支柱70的自由端76、72上形成的基本共面的表面和支撑焊盘62的底面92接触并紧固。尽管4示出了单个引脚框52,但是应当意识到可以提供多个互连的引脚框52,提供多个互连的引脚框52,在一般作为制造工艺的最后步骤中,通过用刀片、喷水装置等将互连的引脚框52锯成单个。
参考图5,该图示出了引脚框52的立体顶视图,其中引脚框52被引线键合到管芯14。管芯14使用任何方便的方法被紧固到支撑焊盘62,例如,焊接、环氧树脂、双面胶带等。在管芯14被紧固到支撑焊盘62后,引线18被单独连接在管芯14上的I/O焊盘80和各个引脚60上的键合点78之间。支撑支柱74维持每条引脚60中的键合点78的共面性,这允许将引线18精确地键合到键合点78,从而减少封装的制造缺陷。另外,支撑支柱74将与引线18的键合关联的力从键合点78传递到表面94。由于支撑支柱74和键合点78得到支撑,所以与利用现有技术的引脚框设计相比,本发明的引脚60允许使用广泛的键合方法和引线材料。将在下文描述,引线键合可以使用超声波键合来实现,其中压力和超声波振动突发的组合被施加来形成冶金冷焊点;也可以使用热压键合,其中压力和升高的温度的组合被施加来形成焊点;或者使用热声键合,其中压力、升高的温度和超声波振动突发的组合被施加来形成焊点。
在下文中将详细描述,通过对封装特征的部分蚀刻形成的健壮的中间结构可以使得能够使用超声波键合来在焊盘和引脚二者处形成楔形键合。在键合中使用的这种类型的引线优选由金、金合金、铝或者铝合金制成。
也可以使用载带自动键合(TAB)来作为引线键合的替换。
在I/O焊盘80被引线键合到它们的关联键合点78后,用模塑料54覆盖管芯14、引脚框52、和键合引线18,如图6所示。模塑料54可以使用任何方便的技术而被应用,例如,转移造型或注入成型工艺。模塑料54是一种电绝缘材料,优选是聚合成型树脂,例如环氧树脂,其具有在约250℃到约300℃之间的范围内的流动温度。模塑料54也可以是低温热玻璃复合材料。
在施加模塑料54期间,粘到表面94的支撑支柱74和板连接支柱70防止插入部分64移动,从而维持引脚60之间的间隔,并且帮助确保在键合点78处的引线键合不被弄乱或断裂。另外,在插入部分64下面形成的沟道82(图3)容纳模塑料54,其将插入部分64、支撑支柱74和板连接支柱70锚定在封装50内。
在键合点78、管芯14和引脚框52被涂覆后,粘结的表面94被移除,并且如果必要的话利用刀片、喷水装置等将附接的封装50锯成单个。参考图3和图7,在移除了粘结的表面94并且单个化后,每个封装50的引脚框52的多个部分被暴露出。具体而言,支撑支柱74的自由端76、板连接支柱70的自由端72、插入部分64的末端66、拉杆90的末端、管芯支撑焊盘62的底面92可以被暴露出。在典型的布置中,仅板连接支柱70的自由端72将用于连接到外部电路。然而,如果需要的话,支撑支柱74的自由端76和插入部分64的末端66也可以连接到外部电路。
参考图8,该图示出了引线键合到管芯14的替换引脚框100的立体顶视图。图8示出的引脚框100用于生产双列无引脚引线键合的半导体器件封装102,该封装102在图9和图10中示出。图9示出了半导体封装102的部分切出后的立体顶视图,而图10示出了半导体封装的立体底视图。图8到图10的封装102与参考图3~7描述的封装50基本类似,除了引脚框100是针对两类半导体封装设计。引脚框100包括两组每组八条引脚60,每组引脚60设置为靠近管芯支撑焊盘62的相对两侧。尽管示出了两组每组八条引脚,但是应当意识到每组可以包括任意数目的引脚60。管芯支撑焊盘62包括两个拉杆90,每个从管芯的相对端延伸出。制造半导体封装102的方法与参考图3~7描述的相同。
参考图11,该图示出了方形无引脚倒装芯片半导体器件封装110的截面图。图11的封装110与图3所示的封装50基本类似,除了图11中的管芯14使用倒装芯片法被连接到引脚框112从而不使用管芯支撑焊盘。
图12是有管芯14焊接到的方形无引脚倒装芯片封装110的引脚框112的立体顶视图。所示引脚框112包括在四侧的每侧设置的七条引脚60。但是,应当意识到可以在每侧使用任意数目的引脚60。
制造封装110的方法与参考图3~7描述的基本类似,除了管芯14直接被电连接到键合点78(如图11和图12所示)而不是附接到支撑焊盘并且引线键合或带键合到键合点78。“直接”电连接意思是指用倒装芯片法互连而不使用居间的引线键合或载带自动键合。适当的附接包括利用从由金、锡和铅组成的组中选出的主要组分的焊接。支撑支柱74维持每条引脚60中的键合点78的共面性,这允许将管芯14精确键合到键合点78,并且从而减少制造封装110中的缺陷。支撑支柱74还将与将管芯14键合到键合点78关联的任何力传递到表面94。另外,粘到表面94的支撑支柱74和板连接支柱70防止在施加模塑料54期间插入部分64移动,从而维持引脚60直接的间隔,并且帮助确保管芯14和引脚框112之间的键合不被弄乱或断裂。另外,在插入部分64下面形成的沟道82容纳模塑料54,其将插入部分64、支撑支柱74和板连接支柱70锚定在封装110内。
参考图13,该图示出了双列无引脚倒装芯片半导体器件封装的替换引脚框120的立体顶视图。在图13中,示出了在单个化之前的多个相邻引脚框120的一部分,其中外框部分122连接每个引线框120。线124指示在单个化期间被毁坏的引脚框120部分。应当意识到,这里所述的任何实施例都可以包括这种用于在单个化之前互连引脚框外引脚框部分122。图13中示出的引脚框120可以结合这里所述的方法用来生产双列无引脚倒装芯片半导体器件封装。设想仅通过从参考图8~10描述的引脚框100移除管芯支撑焊盘62对用于倒装芯片封装的引脚框120进行修改,相同的引脚框设计可用于倒装芯片和引线键合封装二者。
在图3~13的每个实施例中,支撑支柱74从插入部分64的末端66偏移,以使末端66充当突出,用于将引脚60锚定在模塑料54内。图14和图15示出了引脚60的替换配置,其中板连接支柱70的与自由端72相邻的侧124在封装的面58处可见。这种布置是有益的,因为侧124在封装的侧面58上可见确保在封装被表面安装到印刷电路板时板连接支柱70与安装在该印刷电路板上的引脚适当对准和连接。插入部分64可以使用受控的减少工艺被成型为包括凹进126,例如化学蚀刻或激光切除。如图15a和图15b所示,自由端72和侧124之间的板连接支柱70的拐角可以被移除,从而形成缺口(relief)128。优选地,当垂直于自由端72测量时缺口128高度在约1密耳到约2密耳之间。缺口128被提供来在单个化处理时容许或抹去模糊形成(burrformation),同时使侧124能够提供可见的圆角(fillet)以便封装的表面安装。
应该意识到图14和图15中提供的替换引脚60布置可以被用于在这里所述的任意实施例中。例如,图16是应用图14a所示替换引脚60配置的方形无引脚引线键合的半导体器件封装50的截面图。图17是应用了图14a的替换引脚60配置的封装50的引脚框52的立体顶视图。图18是应用了图14a的替换引脚60配置的封装50的部分切出后的立体顶视图,并且图19是应用了图14a的替换引脚60配置的封装50立体底视图。在另一示例中,图16是应用了图14b中示出的替换引脚60配置的方形无引脚倒装芯片半导体器件封装110的截面图。图17是应用了图14b中示出的替换引脚60配置的封装110的引脚框112的立体顶视图。图18是应用了图14b中示出的替换引脚60配置的封装110的部分切出后的立体顶视图,并且图19是应用了图14b中示出的替换引脚60配置的封装110的立体底视图。
在这里所述的任意实施例中,可能最好在封装底表面56处将支撑支柱74的自由端76电间隔。这可以通过向自由端76涂覆电绝缘涂层来实现。图24示出了具有覆盖在支撑支柱74的自由端76上的电绝缘涂层130的方形无引脚半导体器件封装的立体底视图。图25示出了具有覆盖在支撑支柱74的自由端76上的电绝缘涂层130的双列无引脚半导体器件封装的立体底视图。电绝缘涂层130可以通过丝网印刷、喷墨或者贴带等被涂覆。
图26a~h示出了楔形键合方法的各个阶段,用于在将I/O焊盘80引线键合到上述器件封装50或102中的各个引脚60上的键合点78中使用的楔形键合方法的各个阶段。该方法在I/O焊盘80和键合点78二者处形成所谓的“楔形键合”200。楔形键合200是这样的键合,其中引线18的侧面附接到I/O焊盘80或键合点78,同时引线18一般平行于I/O焊盘80或键合点78的表面延伸,如图26h所示。
如图26a所示,该方法应用键合楔(触针)202,键合楔202基本上是多面体结构,其具有形成在自由端上的平面键合面204。在邻近键合面204设置有V形槽口,该V形槽口限定键合楔202的引线引导部分206。引线引导部分206包括通过其设置的孔径,用于容纳在过程中使用的引线18。键合楔202还包括引线夹具208,引线通过该引线夹具。键合楔202可由计算机控制的系统制造,其相对于矩阵移动键合楔202,以沿I/O焊盘80及其关联键合点78之间的轴对准键合楔202。应当意识到可以同时操作多于一个键合楔202来对框架矩阵中的每个框架执行引线键合。
在楔形键合方法中使用的引线18可以是铝线或铝基合金。铝基合金是指在重量上包含超过50%的铝的材料。例如,铝线可以搀杂有硅(例如,1%的硅),来使引线的硬度与I/O焊盘80或键合点78材料更加匹配。也可以使用其他引线材料(例如,金或金基合金)。
在楔形键合工艺中,键合线18被导向I/O焊盘80或键合点78的表面,然后利用键合楔202压到表面上,如图26b和图26e所示。尽管引线18被稳固地夹持在键合楔202和I/O焊盘80或键合点78之间,但是超声波振动突发被施加到键合楔202。如果在室温执行超声波振动(即,没有外部温度源被施加到键合楔202、键合引线18、I/O焊盘80或键合点78),则该工艺被称作超声波键合。利用超声波键合,压力和振动的组合在引线18和I/O焊盘80或键合点78之间实现冶金冷焊点。在热量被施加到键合楔202、键合引线18、I/O焊盘80或键合点78的同时超声波振动突发被施加到键合楔202,则该工艺被称作热声键合。但是,不同于传统的热声键合,楔形键合200被形成在I/O焊盘80和键合点78二者处。
在图27b~26g中,描述了楔形键合方法,其中引线18在被键合到引脚60上的键合点78之前被键合到I/O焊盘80。可替换地,引线18也可以在被键合到I/O焊盘80之前被键合到键合点78。
参考图26b,引线18使用超声波或热声键合被楔形键合到I/O焊盘80。在I/O焊盘80处形成了楔形键合200之后,夹具208释放引线18,并且键合楔202离开I/O焊盘80并从I/O焊盘80朝引脚60上的关联键合点78移动,如图26c和图26d所示。然后,键合楔202下降到键合点78上,并且引线18使用超声波或热声键合被楔形键合到键合点78。在引线18和键合点78之间的楔形键合200形成后,键合楔202摆动以割断或切断引线18(图26f),然后键合楔202从引脚60移开,同时夹具208闭合以分开引线18(图26g)。结果楔形键合200形成在引线18和I/O焊盘80之间以及引线18与引脚60之间,如图26h所示。
图27是形成在I/O焊盘80上的楔形键合200的立体图,图28是形成在引脚60的键合点78上的楔形键合200的立体图。如图27和图28可见,在楔形键合200处,引线18的侧面被附接到I/O焊盘80或键合点78,同时引线18一般平行于I/O焊盘80或键合点78的表面延伸。引线18沿楔形键合200被压扁,该压扁部分的长度被限定为楔形长度(220所示)。在与I/O焊盘80或键合点78的表面平行的平面方向上横着引线18测量的引线18的压扁部分的最大宽度被限定为楔形宽度(222所示),并且引线18的延伸超过压扁部分的自由端的长度被称作尾长(224所示)。楔形宽度222一般是在I/O焊盘80和键合点78之间延伸的未压扁部分的直径的约1.2到约1.5倍。
已经发现在I/O焊盘80和引脚60上形成楔形键合200的顺序确定I/O焊盘80和引脚60哪个具有较长的尾长224。更具体地说,已经发现引线终止发生的点(I/O焊盘80或引脚60)具有较短的尾长224。因此,如上所述,楔形键合200首先形成在I/O焊盘80上,然后形成在引脚60上,则在引脚60处的尾长224比在I/O焊盘80处的尾长224短。有益地是,在引脚60处具有较短的尾长224有助于确保引线18的尾部将不会突出超过引脚60的末端,结果可以使封装宽度最小化。
上述器件封装50和102尤其适合楔形键合方法,这是由于器件封装50和102中的支撑支柱74提供了对键合点78的支撑,这防止在形成楔形键合200期间损坏引脚60。也可以设想可用在其他类型封装中的方法。例如,图29a~29i示出了也非常适于使用该方法的替换半导体器件封装300的组装的各个阶段。
在图29a~29j中,在引线键合之前每个引脚框302仅被部分蚀刻。引脚框302在其上表面被蚀刻,以使支撑焊盘62和引脚60仍由金属衬底304连接。金属衬底304在楔形键合工艺期间向引脚60提供坚固的结构和支撑,从而防止损坏引脚60。在另一个实施例中,引脚框可以被部分蚀刻,以使尽管引脚60不连接到支撑焊盘62,但是它们具有比将在最终封装中使用的大的厚度。该额外的厚度提供在楔形键合工艺期间防止损坏引脚60所需的坚固结构和支撑。
图29a是引脚框302(图29g)的前体级的平面图,图29b是引脚框302的前体级的截面正视图。多个引脚框302优选连接在一起,以允许同时组装。或者,设想引脚框302也可以单独被组装。引脚框302可由任何合适的导体片形成,并且优选是铜或铜基合金。
在每个引脚框302中形成的各个特征优选使用受控的减少工艺形成,例如,化学蚀刻或激光切除。例如,要形成引脚60和支撑焊盘62的上表面的每个表面可由用化学抗蚀剂涂覆,并且剩余的表面暴露给适当的蚀刻剂持续一定时间,有效地减少剩余表面下的厚度,以实现引脚60和支撑焊盘62的期望高度。该工艺最终形成引脚60和支撑焊盘62,它们都从金属衬底304延伸出。
参考图29c,引脚60上的键合点78可以镀有材料来辅助引线键合。例如,键合点78可以镀有与在引线18中使用的材料相对应的材料(例如,在使用铝或铝基合金引线18的情况下键合点78可以镀有铝或铝基合金)。
参考图29d,然后使用任何方便的方法将管芯14紧固到支撑焊盘62,例如,焊接、环氧树脂、双面胶带等。在管芯14被紧固到支撑焊盘62之后,引线18单独被连接在管芯14上的I/O焊盘80和各个引脚60上的键合点78之间,如图29e所示。
参考图29f,在引线键合完成后,管芯14、引脚框302的上部、以及键合引线18被用模塑料54覆盖。可以使用任何方便的技术施加模塑料54,例如,转移造型或注入成型工艺。模塑料54是电绝缘材料,优选是聚合成型树脂,例如环氧树脂,其具有在约250℃到约300℃之间的范围内的流动温度。模塑料54也可以是低温热玻璃复合材料。
在模塑料54被施加后,金属衬底304材料使用受控减法工艺被移除,例如,化学蚀刻或激光切除。该步骤的结果如图29g所示。移除金属衬底304材料将引脚60从支撑焊盘62电分离。暴露的表面可以被电镀以辅助电连接到外部电路。另外,焊球306可以被附接到暴露的表面,以辅助与外部电路的电连接,如图29h所示。
然后通过利用刀片、喷水装置等将附接的封装锯成单个,以形成如图29i所示的封装300。
使用楔形键合方法来将I/O焊盘80键合到各个引脚60的键合点78与现有技术相比提供了许多优点。例如,最终楔形宽度222(图27)约为所使用的引线18的直径的1.2~1.5倍,该宽度远小于球形键合的宽度,球形键合的宽度一般是引线18的直径的2~3倍。与球形键合相比,较小的宽度允许减小引线节距(即,相邻引脚之间的间隔)。结果,相对于利用球形键合,使用楔形键合方法可以准许极大增加在封装中使用的引脚60的数目。
另外,与利用球形键合特征相比,楔形键合方法允许较小的引线环高(loop height)。如图26h可见,引线环高是引线18延伸高过触点(例如,I/O焊盘80)的高度“h”。由于引线一般平行于触点延伸,所以与球形键合所要求的环高(其中引线从触点垂直延伸,如图2的21所示)相比,环高“h”可以相对较小。这非常有益于保持较薄的塑料封装,以及堆叠的多管芯封装。
此外,楔形键合方法可以在室温使用超声波键合执行,因此与球形键合方法相比增强了封装工艺的可靠性。更具体地说,球形键合要求将引脚框和管芯都暴露在150~360℃左右的温度中。由于当今在矩阵和阵列矩阵格式中使用大量引线键合,所以执行引线键合的时间,从而即组件承受高温的时间可能长到足以在管芯14中导致缺陷。由于不需要使用高温,所以楔形键合方法消除了这种缺陷的涞来源。
最后,楔形键合方法可以减少制造封装的成本,这是因为该方法允许使用铝或铝基合金引线,它们的成本远远低于一般用于球形键合技术的金引线。
已经描述了本发明的多个实施例。然而,应当理解,在不脱离本发明的精神和范围的情况下,可以作出各种修改。因此,其他实施例也在所附权利要求书的范围内。
应当理解,这里所述的关于特定实施例的任何特征、特性、替换、修改、或者优点也可以应用于、用于或者结合到这里所述的任何其他实施例。
Claims (33)
1.一种半导体器件封装(50,102,110),包括:
模塑料(54),其形成至少第一封装面(56)的一部分;
半导体器件(14),其至少部分由所述模塑料(54)覆盖,所述半导体器件(14)包括多个I/O焊盘(80);以及
导电材料的引脚框(52,100,112),其至少部分由模塑料(54)覆盖,所述引脚框(52,100,112)包括多条引脚(60),每条所述引脚(60)包括:
插入部分(64),其具有相对的第一和第二末端(66,68),所述插入部分(64)与所述第一封装面(56)间隔开,
板连接支柱(70),其从靠近所述插入部分(64)的第一末端(66)延伸出并且终止于所述第一封装面(56),
支撑支柱(74),其与所述板连接支柱(70)间隔开,所述支撑支柱(74)从靠近所述插入部分(64)的第二末端(68)延伸出并且终止于所述第一封装面(56),以及
键合点(78),其形成在所述插入部分(64)的与所述支撑支柱(74)相对的表面上,所述I/O焊盘(80)中的至少一个在所述键合点(78)处被电连接到所述插入部分(64)。
2.如权利要求1所述的半导体器件封装(50,102),其中,所述I/O焊盘(80)中的至少一个被引线键合或载带键合到所述键合点(78)。
3.如权利要求2所述的半导体器件封装(50,102),其中,所述I/O焊盘(80)中的至少一个通过在所述I/O焊盘(80)处引线形成楔形键合并且在所述键合点(78)处引线形成楔形键合,从而在所述键合点(78)处被电连接到插入部分(64)。
4.如权利要求3所述的半导体器件封装(50,102),其中,所述引线由铝或铝基制成。
5.如权利要求1所述的半导体器件封装(110),其中,所述I/O焊盘(80)中的至少一个被直接焊接到所述键合点(78)以形成倒装芯片型连接。
6.如权利要求2所述的半导体器件封装(50,102,110),其中,所述模塑料(54)形成与所述第一封装面(56)相邻的第二封装面(58)的至少一部分,并且与所述板连接支柱(70)的末端表面(72)相邻的所述板连接支柱(70)的侧表面(124)在所述第二封装面(58)处可见。
7.如权利要求6所述的半导体器件封装(50,102,110),其中,所述板连接支柱(70)的所述侧表面(124)与所述板连接支柱(70)的所述末端表面(72)之间的拐角被移除以形成缺口(128),所述缺口(128)从所述板连接支柱(70)的所述末端表面(72)测量具有在约1密耳到约2密耳之间的高度。
8.如权利要求1所述的半导体器件封装(50,102,110),其中,每条所述引脚(60)由材料条带形成,所述材料条带具有设置跨过所述条带的沟道(82)。
9.如权利要求8所述的半导体器件封装(50,102,110),其中,所述沟道(82)填充有所述模塑料(54)。
10.一种用于封装半导体器件(14)的方法,所述方法包括:
用导电材料形成引脚框(52,100,112),所述引脚框(52,100,112)包括多条引脚(60),每条所述引脚(60)包括:
插入部分(64),其具有相对的第一和第二末端(66,68),
板连接支柱(70),其从靠近所述插入部分(64)的第一末端(66)延伸出,所述板连接支柱(70)具有远离所述插入部分(64)的末端表面(72),
支撑支柱(74),其与所述板连接支柱(70)间隔开,并且从靠近所述插入部分(64)的所述第二末端(68)延伸出,所述支撑支柱(74)具有远离所述插入部分(64)的末端表面(76),以及
键合点(78),其形成在所述插入部分(64)的与所述支撑支柱(74)相对的表面上;
支撑所述支撑支柱(74)的所述末端表面(72,76)和所述板连接支柱(70);以及
在支撑所述支撑支柱(74)的所述末端表面(72,76)和所述板连接支柱(70)的同时将所述半导体器件(14)上的I/O焊盘(80)电连接到所述键合点(78);以及
在支撑所述支撑支柱(74)的所述末端表面和所述板连接支柱(70)的同时利用模塑料(54)覆盖所述半导体器件(14)的至少一部分以及所述引脚框(52,100,112)的至少一部分。
11.如权利要求10所述的方法,其中,将所述I/O焊盘(80)电连接到所述键合点(78)包括:
将每个I/O焊盘(80)引线键合或载带键合到关联的键合点(78)。
12.如权利要求11所述的方法,其中,将每个I/O焊盘(80)引线键合到关联的键合点(78)包括:
将引线(18)楔形键合到所述I/O焊盘(80),并且
将引线(18)楔形键合到所述键合点(78)。
13.如权利要求12所述的方法,其中,所述引线(18)由铝或铝基合金制成。
14.如权利要求10所述的方法,其中,将所述I/O焊盘(80)电连接到所述键合点(78)包括:
将所述I/O焊盘(80)直接电连接到所述键合点(78)来形成倒装芯片型连接。
15.如权利要求10所述的方法,其中,支撑所述支撑支柱(74)的末端表面(72,76)和所述板连接支柱70包括:
将所述支撑支柱(74)的所述末端表面(72,76)和所述板连接支柱(70)粘到一个表面(94)。
16.如权利要求10所述的方法,其中,所述模塑料(54)形成至少第一封装面(56)的一部分,并且所述支撑支柱(74)的所述末端表面(72,76)和所述板连接支柱(70)与所述第一封装面(56)共面。
17.如权利要求16所述的方法,其中,所述模塑料(54)形成至少与所述第一封装面(56)相邻的第二封装面(58)的一部分,并且与所述板连接支柱(70)的所述末端表面(72)相邻的所述板连接支柱(70)的侧表面(124)在所述第二封装面(58)处可见。
18.如权利要求17所述的方法,其中,所述板连接支柱(70)的所述侧表面(124)与所述板连接支柱(70)的所述末端表面(72)之间的拐角被移除以形成缺口(128),所述缺口(128)从所述板连接支柱(70)的所述末端表面(72)测量具有在约1密耳到约2密耳之间的高度。
19.如权利要求10所述的方法,其中,形成所述引脚框(52,100,112)包括:
用导电材料形成引脚框前体,所述引脚框前体包括多个引脚前体,每个所述引脚前体是导电材料条带;以及
设置跨过每个所述引脚前体的沟道(82)来形成所述多条引脚(60)。
20.如权利要求19所述的方法,还包括:
用所述模塑料(54)填充每条引脚中的所述沟道(82)。
21.一种半导体器件封装(50,102,300),包括:
模塑料(54),其形成至少第一封装面(56)的一部分;
半导体器件(14),其至少部分由所述模塑料(54)覆盖,所述半导体器件(14)包括多个I/O焊盘(80);以及
导电材料的引脚框(52,100,112),其至少部分由所述模塑料(54)覆盖,所述引脚框(52,100,112)包括多条引脚(60),每条所述引脚(60)包括形成在其上的键合点(78),每个键合点(78)由引线(18)电连接到关联的I/O焊盘(80),所述引线(18)在所述I/O焊盘(80)处形成楔形键合并且在所述键合点(78)处形成楔形键合。
22.如权利要求21所述的半导体器件封装(50,102,300),其中,所述引线(18)由铝或铝基制成。
23.如权利要求21所述的半导体器件封装(50,102),其中,每个所述引脚60还包括:
插入部分(64),其具有相对的第一和第二末端(66,68),所述插入部分(64)与所述第一封装面(56)间隔开,
板连接支柱(70),其从靠近所述插入部分(64)的第一末端(66)延伸出并且终止于所述第一封装面(56),
支撑支柱(74),其与所述板连接支柱(70)间隔开,所述支撑支柱(74)从靠近所述插入部分(64)的第二末端(68)延伸出并且终止于所述第一封装面(56),所述键合点(78)形成在所述插入部分(64)的与所述支撑支柱(74)相对的表面上。
24.如权利要求21所述的半导体器件封装(300),其中,在所述模塑料(54)被施加到所述引脚框(302)后,所述引脚框(302)被蚀刻来分离所述引脚(60)。
25.如权利要求21所述的半导体器件封装(50,102,300),其中,所述引线(18)具有所述引线(18)在所述I/O焊盘(80)和所述键合点(78)之间延伸的部分的直径的约1.2到约1.5倍之间的楔形宽度。
26.一种用于封装半导体器件(14)的方法,所述方法包括:
用导电材料形成引脚框(52,100,302),所述引脚框(52,100,302)包括多条引脚(60),每条所述引脚(60)包括形成在其上的键合点(78);
将所述半导体器件(14)上的I/O焊盘(80)电连接到所述键合点(78),所述电连接包括:
将引线(18)楔形键合到所述I/O焊盘(80),并且
将引线(18)楔形键合到所述键合点(78);以及
用模塑料54覆盖所述半导体器件(14)的至少一部分以及所述引脚框(52,100,302)的至少一部分。
27.如权利要求26所述的方法,其中,所述引线(18)由铝或铝基制成。
28.如权利要求26所述的方法,其中,每条引脚包括:
插入部分(64),其具有相对的第一和第二末端(66,68),
板连接支柱(70),其从靠近所述插入部分(64)的第一末端(66)延伸出,所述板连接支柱(70)具有远离所述插入部分(64)的末端表面(72),
支撑支柱(74),其与所述板连接支柱(70)间隔开,并且从靠近所述插入部分(64)的所述第二末端(68)延伸出,所述支撑支柱(74)具有远离所述插入部分(64)的末端表面(76),所述键合点(78)形成在所述插入部分(64)的与所述支撑支柱(74)相对的表面上,所述支撑支柱(74)在将所述引线(18)引线键合到所述键合点(78)期间支撑所述键合点(78)。
29.如权利要求26所述的方法,其中,所述楔形键合包括超声波键合。
30.如权利要求26所述的方法,其中,所述楔形键合包括热声键合。
31.如权利要求26所述的方法,其中,在所述引线(18)被楔形键合到所述键合点(78)之前,所述引线(18)被楔形键合到所述I/O焊盘(80)。
32.如权利要求26所述的方法,还包括:
在将所述半导体器件14上的I/O焊盘(80)电连接到所述键合点(78)后,蚀刻所述引线框(302)以分离所述引脚(60)。
33.如权利要求26所述的方法,其中,所述引线(18)具有所述引线(18)在所述I/O焊盘(80)和所述键合点(78)之间延伸的部分的直径的约1.2到约1.5倍之间的楔形宽度。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US49498203P | 2003-08-14 | 2003-08-14 | |
US60/494,982 | 2003-08-14 | ||
PCT/US2004/026152 WO2005017968A2 (en) | 2003-08-14 | 2004-08-11 | Semiconductor device package and method for manufacturing same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101375382A true CN101375382A (zh) | 2009-02-25 |
CN101375382B CN101375382B (zh) | 2011-04-20 |
Family
ID=34193261
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2004800232766A Expired - Fee Related CN101375382B (zh) | 2003-08-14 | 2004-08-11 | 半导体器件封装及其制造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7563648B2 (zh) |
EP (1) | EP1654753A4 (zh) |
JP (1) | JP2007509485A (zh) |
KR (1) | KR20060058111A (zh) |
CN (1) | CN101375382B (zh) |
TW (1) | TWI350573B (zh) |
WO (1) | WO2005017968A2 (zh) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101958300A (zh) * | 2010-09-04 | 2011-01-26 | 江苏长电科技股份有限公司 | 双面图形芯片倒装模组封装结构及其封装方法 |
CN102254893A (zh) * | 2011-07-29 | 2011-11-23 | 天水华天科技股份有限公司 | 一种带双凸点的四边扁平无引脚封装件及其生产方法 |
CN102263080A (zh) * | 2011-07-29 | 2011-11-30 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚三ic芯片封装件及其生产方法 |
CN102263081A (zh) * | 2011-07-29 | 2011-11-30 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法 |
CN102270620A (zh) * | 2011-04-08 | 2011-12-07 | 日月光半导体制造股份有限公司 | 在边缘引脚具有凹槽的半导体封装结构 |
CN102376671A (zh) * | 2011-11-29 | 2012-03-14 | 杭州矽力杰半导体技术有限公司 | 引线框架以及应用其的倒装芯片式半导体封装结构 |
CN102446781A (zh) * | 2011-12-08 | 2012-05-09 | 华中科技大学 | 相变存储器芯片的封装方法 |
CN105789167A (zh) * | 2016-03-15 | 2016-07-20 | 昂宝电子(上海)有限公司 | 集成电路芯片封装装置、和引线框架 |
CN105990167A (zh) * | 2014-09-16 | 2016-10-05 | 株式会社东芝 | 导线键合装置及半导体装置 |
CN107195612A (zh) * | 2017-06-20 | 2017-09-22 | 南京矽邦半导体有限公司 | 一种基于加长半蚀刻拱形内引脚qfn框架及其封装芯片 |
CN107611041A (zh) * | 2016-07-11 | 2018-01-19 | 艾马克科技公司 | 具有夹具对准凹口的半导体封装和相关方法 |
CN108370104A (zh) * | 2015-12-03 | 2018-08-03 | 大陆-特韦斯股份有限公司 | 导电轨,方法及用途 |
CN113192920A (zh) * | 2021-05-21 | 2021-07-30 | 南京矽邦半导体有限公司 | 一种qfn封装的引脚结构 |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006068643A1 (en) * | 2004-12-20 | 2006-06-29 | Semiconductor Components Industries, L.L.C. | Semiconductor package structure having enhanced thermal dissipation characteristics |
US7439100B2 (en) * | 2005-08-18 | 2008-10-21 | Semiconductor Components Industries, L.L.C. | Encapsulated chip scale package having flip-chip on lead frame structure and method |
US20070063333A1 (en) * | 2005-09-20 | 2007-03-22 | Texas Instruments Incorporated | Semiconductor package with internal shunt resistor |
US8022512B2 (en) | 2006-02-28 | 2011-09-20 | Unisem (Mauritus) Holdings Limited | No lead package with heat spreader |
US7816186B2 (en) | 2006-03-14 | 2010-10-19 | Unisem (Mauritius) Holdings Limited | Method for making QFN package with power and ground rings |
TWI286375B (en) * | 2006-03-24 | 2007-09-01 | Chipmos Technologies Inc | Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for fabricating the same |
SG139573A1 (en) | 2006-07-17 | 2008-02-29 | Micron Technology Inc | Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods |
JP4533875B2 (ja) | 2006-09-12 | 2010-09-01 | 株式会社三井ハイテック | 半導体装置およびこの半導体装置に使用するリードフレーム製品並びにこの半導体装置の製造方法 |
KR100813621B1 (ko) * | 2006-10-03 | 2008-03-17 | 삼성전자주식회사 | 적층형 반도체 소자 패키지 |
US7741704B2 (en) | 2006-10-18 | 2010-06-22 | Texas Instruments Incorporated | Leadframe and mold compound interlock in packaged semiconductor device |
SG149726A1 (en) | 2007-07-24 | 2009-02-27 | Micron Technology Inc | Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods |
MY154596A (en) * | 2007-07-25 | 2015-06-30 | Carsem M Sdn Bhd | Thin plastic leadless package with exposed metal die paddle |
SG150396A1 (en) | 2007-08-16 | 2009-03-30 | Micron Technology Inc | Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods |
US8492883B2 (en) | 2008-03-14 | 2013-07-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having a cavity structure |
US8017451B2 (en) | 2008-04-04 | 2011-09-13 | The Charles Stark Draper Laboratory, Inc. | Electronic modules and methods for forming the same |
US8273603B2 (en) * | 2008-04-04 | 2012-09-25 | The Charles Stark Draper Laboratory, Inc. | Interposers, electronic modules, and methods for forming the same |
US8269324B2 (en) * | 2008-07-11 | 2012-09-18 | Stats Chippac Ltd. | Integrated circuit package system with chip on lead |
US20100044850A1 (en) * | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
TWI414048B (zh) * | 2008-11-07 | 2013-11-01 | Advanpack Solutions Pte Ltd | 半導體封裝件與其製造方法 |
TWI372454B (en) * | 2008-12-09 | 2012-09-11 | Advanced Semiconductor Eng | Quad flat non-leaded package and manufacturing method thereof |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
JP5706254B2 (ja) * | 2011-07-05 | 2015-04-22 | 株式会社東芝 | 半導体装置 |
US9147629B2 (en) * | 2012-09-20 | 2015-09-29 | Silego Technology, Inc. | Extremely thin package |
US9142491B2 (en) * | 2012-09-28 | 2015-09-22 | Conexant Systems, Inc. | Semiconductor package with corner pins |
ITMI20130473A1 (it) * | 2013-03-28 | 2014-09-29 | St Microelectronics Srl | Metodo per fabbricare dispositivi elettronici |
US9437458B2 (en) * | 2013-11-12 | 2016-09-06 | Infineon Technologies Ag | Method of electrically isolating leads of a lead frame strip |
US9324642B2 (en) | 2013-11-12 | 2016-04-26 | Infineon Technologies Ag | Method of electrically isolating shared leads of a lead frame strip |
US9287238B2 (en) | 2013-12-02 | 2016-03-15 | Infineon Technologies Ag | Leadless semiconductor package with optical inspection feature |
US9570381B2 (en) | 2015-04-02 | 2017-02-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages and related manufacturing methods |
US9847281B2 (en) | 2015-06-30 | 2017-12-19 | Stmicroelectronics, Inc. | Leadframe package with stable extended leads |
US11538768B2 (en) * | 2019-10-04 | 2022-12-27 | Texas Instruments Incorporated | Leadframe with ground pad cantilever |
US20230063278A1 (en) * | 2021-08-27 | 2023-03-02 | Texas Instruments Incorporated | Laser-cut lead-frame for integrated circuit (ic) packages |
CN117133746B (zh) * | 2023-10-26 | 2024-01-30 | 成都电科星拓科技有限公司 | 用于双面焊接的方形扁平无引脚封装芯片结构及封装方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0348018B1 (en) | 1982-03-10 | 1999-05-19 | Hitachi, Ltd. | Method of manufacture of a resin encapsulated semiconductor device |
JP2852134B2 (ja) * | 1991-02-20 | 1999-01-27 | 日本電気株式会社 | バンプ形成方法 |
US5890644A (en) * | 1996-01-26 | 1999-04-06 | Micron Technology, Inc. | Apparatus and method of clamping semiconductor devices using sliding finger supports |
US6281568B1 (en) * | 1998-10-21 | 2001-08-28 | Amkor Technology, Inc. | Plastic integrated circuit device package and leadframe having partially undercut leads and die pad |
JP3062192B1 (ja) * | 1999-09-01 | 2000-07-10 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法 |
JP3450238B2 (ja) * | 1999-11-04 | 2003-09-22 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6238952B1 (en) * | 2000-02-29 | 2001-05-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6452255B1 (en) * | 2000-03-20 | 2002-09-17 | National Semiconductor, Corp. | Low inductance leadless package |
KR100559664B1 (ko) * | 2000-03-25 | 2006-03-10 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
US7042068B2 (en) * | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
JP3883784B2 (ja) * | 2000-05-24 | 2007-02-21 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
US6838319B1 (en) | 2000-08-31 | 2005-01-04 | Micron Technology, Inc. | Transfer molding and underfilling method and apparatus including orienting the active surface of a semiconductor substrate substantially vertically |
JP2002118222A (ja) * | 2000-10-10 | 2002-04-19 | Rohm Co Ltd | 半導体装置 |
US6437429B1 (en) * | 2001-05-11 | 2002-08-20 | Walsin Advanced Electronics Ltd | Semiconductor package with metal pads |
FR2825515B1 (fr) * | 2001-05-31 | 2003-12-12 | St Microelectronics Sa | Boitier semi-conducteur a grille evidee et grille evidee |
JP2003017646A (ja) * | 2001-06-29 | 2003-01-17 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置およびその製造方法 |
US6812552B2 (en) | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US6940154B2 (en) * | 2002-06-24 | 2005-09-06 | Asat Limited | Integrated circuit package and method of manufacturing the integrated circuit package |
US7033517B1 (en) * | 2003-09-15 | 2006-04-25 | Asat Ltd. | Method of fabricating a leadless plastic chip carrier |
US7154186B2 (en) * | 2004-03-18 | 2006-12-26 | Fairchild Semiconductor Corporation | Multi-flip chip on lead frame on over molded IC package and method of assembly |
-
2004
- 2004-08-11 US US10/563,712 patent/US7563648B2/en active Active
- 2004-08-11 CN CN2004800232766A patent/CN101375382B/zh not_active Expired - Fee Related
- 2004-08-11 JP JP2006523369A patent/JP2007509485A/ja not_active Abandoned
- 2004-08-11 EP EP04780916A patent/EP1654753A4/en not_active Withdrawn
- 2004-08-11 KR KR1020067003063A patent/KR20060058111A/ko not_active Application Discontinuation
- 2004-08-11 WO PCT/US2004/026152 patent/WO2005017968A2/en active Application Filing
- 2004-08-13 TW TW093124401A patent/TWI350573B/zh not_active IP Right Cessation
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101958300A (zh) * | 2010-09-04 | 2011-01-26 | 江苏长电科技股份有限公司 | 双面图形芯片倒装模组封装结构及其封装方法 |
CN102270620A (zh) * | 2011-04-08 | 2011-12-07 | 日月光半导体制造股份有限公司 | 在边缘引脚具有凹槽的半导体封装结构 |
CN102254893A (zh) * | 2011-07-29 | 2011-11-23 | 天水华天科技股份有限公司 | 一种带双凸点的四边扁平无引脚封装件及其生产方法 |
CN102263080A (zh) * | 2011-07-29 | 2011-11-30 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚三ic芯片封装件及其生产方法 |
CN102263081A (zh) * | 2011-07-29 | 2011-11-30 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法 |
CN102376671A (zh) * | 2011-11-29 | 2012-03-14 | 杭州矽力杰半导体技术有限公司 | 引线框架以及应用其的倒装芯片式半导体封装结构 |
CN102446781A (zh) * | 2011-12-08 | 2012-05-09 | 华中科技大学 | 相变存储器芯片的封装方法 |
CN105990167A (zh) * | 2014-09-16 | 2016-10-05 | 株式会社东芝 | 导线键合装置及半导体装置 |
CN105990167B (zh) * | 2014-09-16 | 2019-08-02 | 东芝存储器株式会社 | 导线键合装置及半导体装置 |
CN108370104A (zh) * | 2015-12-03 | 2018-08-03 | 大陆-特韦斯股份有限公司 | 导电轨,方法及用途 |
CN105789167A (zh) * | 2016-03-15 | 2016-07-20 | 昂宝电子(上海)有限公司 | 集成电路芯片封装装置、和引线框架 |
CN107611041A (zh) * | 2016-07-11 | 2018-01-19 | 艾马克科技公司 | 具有夹具对准凹口的半导体封装和相关方法 |
CN107611041B (zh) * | 2016-07-11 | 2023-03-28 | 艾马克科技公司 | 具有夹具对准凹口的半导体封装和相关方法 |
CN107195612A (zh) * | 2017-06-20 | 2017-09-22 | 南京矽邦半导体有限公司 | 一种基于加长半蚀刻拱形内引脚qfn框架及其封装芯片 |
CN113192920A (zh) * | 2021-05-21 | 2021-07-30 | 南京矽邦半导体有限公司 | 一种qfn封装的引脚结构 |
Also Published As
Publication number | Publication date |
---|---|
US7563648B2 (en) | 2009-07-21 |
EP1654753A4 (en) | 2009-01-21 |
US20070161157A1 (en) | 2007-07-12 |
WO2005017968A3 (en) | 2006-10-19 |
TWI350573B (en) | 2011-10-11 |
EP1654753A2 (en) | 2006-05-10 |
WO2005017968A2 (en) | 2005-02-24 |
KR20060058111A (ko) | 2006-05-29 |
JP2007509485A (ja) | 2007-04-12 |
CN101375382B (zh) | 2011-04-20 |
TW200520120A (en) | 2005-06-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101375382B (zh) | 半导体器件封装及其制造方法 | |
CN101611484B (zh) | 无引脚半导体封装及其制造方法 | |
CN101587869B (zh) | 可颠倒无引线封装及其堆叠和制造方法 | |
US6927479B2 (en) | Method of manufacturing a semiconductor package for a die larger than a die pad | |
KR970010678B1 (ko) | 리드 프레임 및 이를 이용한 반도체 패키지 | |
US6387732B1 (en) | Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby | |
US7981796B2 (en) | Methods for forming packaged products | |
CN100380614C (zh) | 部分构图的引线框架及其制造方法以及在半导体封装中的使用 | |
US5869905A (en) | Molded packaging for semiconductor device and method of manufacturing the same | |
CN103946976A (zh) | 具有翻转式球接合表面的双层级引线框架及装置封装 | |
US8133759B2 (en) | Leadframe | |
JP2005191240A (ja) | 半導体装置及びその製造方法 | |
KR20040037575A (ko) | 사선형 에칭부를 갖는 엠.엘.피(mlp)형 반도체 패키지 | |
CN102412225A (zh) | Bga半导体封装及其制造方法 | |
CN101866889B (zh) | 无基板芯片封装及其制造方法 | |
CN102339762B (zh) | 无载具的半导体封装件及其制造方法 | |
CN103594425B (zh) | 软性基材的封装工艺及其结构 | |
KR100520443B1 (ko) | 칩스케일패키지및그제조방법 | |
JPH0992767A (ja) | 複合リードフレームおよび半導体装置 | |
KR20050046348A (ko) | 반도체 패키지 | |
JPH07106495A (ja) | 半導体装置 | |
KR20010004617A (ko) | 볼 그리드 어레이 패키지 | |
KR19990000394A (ko) | 칩 스케일 패키지 및 그 제조방법 | |
JP2003100955A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110420 Termination date: 20120811 |