CN102376671A - 引线框架以及应用其的倒装芯片式半导体封装结构 - Google Patents
引线框架以及应用其的倒装芯片式半导体封装结构 Download PDFInfo
- Publication number
- CN102376671A CN102376671A CN2011103847425A CN201110384742A CN102376671A CN 102376671 A CN102376671 A CN 102376671A CN 2011103847425 A CN2011103847425 A CN 2011103847425A CN 201110384742 A CN201110384742 A CN 201110384742A CN 102376671 A CN102376671 A CN 102376671A
- Authority
- CN
- China
- Prior art keywords
- lead frame
- finger
- pin
- chip
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (9)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011103847425A CN102376671A (zh) | 2011-11-29 | 2011-11-29 | 引线框架以及应用其的倒装芯片式半导体封装结构 |
TW101131179A TW201322397A (zh) | 2011-11-29 | 2012-08-28 | 引線框架及應用此引線框架的倒裝晶片式半導體封裝結構 |
US13/674,201 US8866273B2 (en) | 2011-11-29 | 2012-11-12 | Lead frame and semiconductor package structure thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011103847425A CN102376671A (zh) | 2011-11-29 | 2011-11-29 | 引线框架以及应用其的倒装芯片式半导体封装结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN102376671A true CN102376671A (zh) | 2012-03-14 |
Family
ID=45795047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2011103847425A Pending CN102376671A (zh) | 2011-11-29 | 2011-11-29 | 引线框架以及应用其的倒装芯片式半导体封装结构 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8866273B2 (zh) |
CN (1) | CN102376671A (zh) |
TW (1) | TW201322397A (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9123629B2 (en) | 2013-10-31 | 2015-09-01 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Chip package and method for forming the same |
CN109087907A (zh) * | 2017-06-14 | 2018-12-25 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
CN110189993A (zh) * | 2018-02-23 | 2019-08-30 | 东莞新科技术研究开发有限公司 | 半导体表面消除内应力的方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103035604B (zh) | 2012-12-17 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | 一种倒装芯片封装结构及其制作工艺 |
CN103400819B (zh) | 2013-08-14 | 2017-07-07 | 矽力杰半导体技术(杭州)有限公司 | 一种引线框架及其制备方法和应用其的封装结构 |
US9905515B2 (en) * | 2014-08-08 | 2018-02-27 | Mediatek Inc. | Integrated circuit stress releasing structure |
WO2017181399A1 (en) * | 2016-04-22 | 2017-10-26 | Texas Instruments Incorporated | Improved lead frame system |
CN107393836B (zh) | 2017-06-19 | 2020-04-10 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装方法及封装结构 |
CN107808868B (zh) | 2017-10-13 | 2020-03-10 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装结构及其制造方法 |
CN110323141B (zh) | 2019-04-15 | 2021-10-12 | 矽力杰半导体技术(杭州)有限公司 | 引线框架结构,芯片封装结构及其制造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
JP2007027645A (ja) * | 2005-07-21 | 2007-02-01 | Renesas Technology Corp | 半導体装置 |
CN101375382A (zh) * | 2003-08-14 | 2009-02-25 | 宇芯(毛里求斯)控股有限公司 | 半导体器件封装及其制造方法 |
CN101640178A (zh) * | 2008-07-30 | 2010-02-03 | 三洋电机株式会社 | 半导体装置、半导体装置的制造方法及引线框 |
CN101694837A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双排引脚的四面扁平无引脚封装件及其生产方法 |
CN101719487A (zh) * | 2009-08-10 | 2010-06-02 | 杭州矽力杰半导体技术有限公司 | 单片集成开关型调节器的倒装封装装置及其封装方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4918511A (en) * | 1985-02-01 | 1990-04-17 | Advanced Micro Devices, Inc. | Thermal expansion compensated metal lead frame for integrated circuit package |
US5477086A (en) * | 1993-04-30 | 1995-12-19 | Lsi Logic Corporation | Shaped, self-aligning micro-bump structures |
SG88741A1 (en) * | 1998-09-16 | 2002-05-21 | Texas Instr Singapore Pte Ltd | Multichip assembly semiconductor |
JP3420153B2 (ja) * | 2000-01-24 | 2003-06-23 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6400004B1 (en) * | 2000-08-17 | 2002-06-04 | Advanced Semiconductor Engineering, Inc. | Leadless semiconductor package |
US6867481B2 (en) * | 2003-04-11 | 2005-03-15 | Fairchild Semiconductor Corporation | Lead frame structure with aperture or groove for flip chip in a leaded molded package |
US8723324B2 (en) * | 2010-12-06 | 2014-05-13 | Stats Chippac Ltd. | Integrated circuit packaging system with pad connection and method of manufacture thereof |
-
2011
- 2011-11-29 CN CN2011103847425A patent/CN102376671A/zh active Pending
-
2012
- 2012-08-28 TW TW101131179A patent/TW201322397A/zh unknown
- 2012-11-12 US US13/674,201 patent/US8866273B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
CN101375382A (zh) * | 2003-08-14 | 2009-02-25 | 宇芯(毛里求斯)控股有限公司 | 半导体器件封装及其制造方法 |
JP2007027645A (ja) * | 2005-07-21 | 2007-02-01 | Renesas Technology Corp | 半導体装置 |
CN101640178A (zh) * | 2008-07-30 | 2010-02-03 | 三洋电机株式会社 | 半导体装置、半导体装置的制造方法及引线框 |
CN101719487A (zh) * | 2009-08-10 | 2010-06-02 | 杭州矽力杰半导体技术有限公司 | 单片集成开关型调节器的倒装封装装置及其封装方法 |
CN101694837A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双排引脚的四面扁平无引脚封装件及其生产方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9123629B2 (en) | 2013-10-31 | 2015-09-01 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Chip package and method for forming the same |
CN109087907A (zh) * | 2017-06-14 | 2018-12-25 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
CN110189993A (zh) * | 2018-02-23 | 2019-08-30 | 东莞新科技术研究开发有限公司 | 半导体表面消除内应力的方法 |
Also Published As
Publication number | Publication date |
---|---|
US20130134567A1 (en) | 2013-05-30 |
TW201322397A (zh) | 2013-06-01 |
US8866273B2 (en) | 2014-10-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C53 | Correction of patent of invention or patent application | ||
CB02 | Change of applicant information |
Address after: 310012 Wensanlu Road, Hangzhou Province, No. 90 East Software Park, science and technology building A1501 Applicant after: Silergy Semiconductor Technology (Hangzhou ) Co., Ltd. Address before: 310012 Wensanlu Road, Hangzhou Province, No. 90 East Software Park, science and technology building A1501 Applicant before: Hangzhou Silergy Semi-conductor Technology Co., Ltd. |
|
COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: HANGZHOU SILERGY SEMI-CONDUCTOR TECHNOLOGY CO., LTD. TO: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) CO., LTD. |
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C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120314 |